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Fixed a typo in command.cpp, moved Changelog to CHANGES.TXT for better coherence.
[proxmark3-svn] / fpga / fpga.v
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6658905f 1//-----------------------------------------------------------------------------\r
2// The FPGA is responsible for interfacing between the A/D, the coil drivers,\r
3// and the ARM. In the low-frequency modes it passes the data straight\r
4// through, so that the ARM gets raw A/D samples over the SSP. In the high-\r
5// frequency modes, the FPGA might perform some demodulation first, to\r
6// reduce the amount of data that we must send to the ARM.\r
7//\r
8// I am not really an FPGA/ASIC designer, so I am sure that a lot of this\r
9// could be improved.\r
10//\r
11// Jonathan Westhues, March 2006\r
12// Added ISO14443-A support by Gerhard de Koning Gans, April 2008\r
13//-----------------------------------------------------------------------------\r
14\r
15`include "lo_read.v"\r
16`include "lo_simulate.v"\r
17`include "hi_read_tx.v"\r
18`include "hi_read_rx_xcorr.v"\r
19`include "hi_simulate.v"\r
20`include "hi_iso14443a.v"\r
21`include "util.v"\r
22\r
23module fpga(\r
24 spck, miso, mosi, ncs,\r
25 pck0i, ck_1356meg, ck_1356megb,\r
26 pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,\r
27 adc_d, adc_clk, adc_noe,\r
28 ssp_frame, ssp_din, ssp_dout, ssp_clk,\r
29 cross_hi, cross_lo,\r
30 dbg\r
31);\r
32 input spck, mosi, ncs;\r
33 output miso;\r
34 input pck0i, ck_1356meg, ck_1356megb;\r
35 output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;\r
36 input [7:0] adc_d;\r
37 output adc_clk, adc_noe;\r
38 input ssp_dout;\r
39 output ssp_frame, ssp_din, ssp_clk;\r
40 input cross_hi, cross_lo;\r
41 output dbg;\r
42\r
43 IBUFG #(.IOSTANDARD("DEFAULT") ) pck0b(\r
44 .O(pck0),\r
45 .I(pck0i)\r
46 );\r
47//assign pck0 = pck0i;\r
48//-----------------------------------------------------------------------------\r
49// The SPI receiver. This sets up the configuration word, which the rest of\r
50// the logic looks at to determine how to connect the A/D and the coil\r
51// drivers (i.e., which section gets it). Also assign some symbolic names\r
52// to the configuration bits, for use below.\r
53//-----------------------------------------------------------------------------\r
54\r
55reg [7:0] conf_word_shift;\r
56reg [7:0] conf_word;\r
57\r
58// We switch modes between transmitting to the 13.56 MHz tag and receiving\r
59// from it, which means that we must make sure that we can do so without\r
60// glitching, or else we will glitch the transmitted carrier.\r
61always @(posedge ncs)\r
62begin\r
63 conf_word <= conf_word_shift;\r
64end\r
65\r
66always @(posedge spck)\r
67begin\r
68 if(~ncs)\r
69 begin\r
70 conf_word_shift[7:1] <= conf_word_shift[6:0];\r
71 conf_word_shift[0] <= mosi;\r
72 end\r
73end\r
74\r
75wire [2:0] major_mode;\r
76assign major_mode = conf_word[7:5];\r
77\r
78// For the low-frequency configuration:\r
79wire lo_is_125khz;\r
80assign lo_is_125khz = conf_word[3];\r
81\r
82// For the high-frequency transmit configuration: modulation depth, either\r
83// 100% (just quite driving antenna, steady LOW), or shallower (tri-state\r
84// some fraction of the buffers)\r
85wire hi_read_tx_shallow_modulation;\r
86assign hi_read_tx_shallow_modulation = conf_word[0];\r
87\r
88// For the high-frequency receive correlator: frequency against which to\r
89// correlate.\r
90wire hi_read_rx_xcorr_848;\r
91assign hi_read_rx_xcorr_848 = conf_word[0];\r
92// and whether to drive the coil (reader) or just short it (snooper)\r
93wire hi_read_rx_xcorr_snoop;\r
94assign hi_read_rx_xcorr_snoop = conf_word[1];\r
95\r
96// For the high-frequency simulated tag: what kind of modulation to use.\r
97wire [2:0] hi_simulate_mod_type;\r
98assign hi_simulate_mod_type = conf_word[2:0];\r
99\r
100//-----------------------------------------------------------------------------\r
101// And then we instantiate the modules corresponding to each of the FPGA's\r
102// major modes, and use muxes to connect the outputs of the active mode to\r
103// the output pins.\r
104//-----------------------------------------------------------------------------\r
105\r
106lo_read lr(\r
107 pck0, ck_1356meg, ck_1356megb,\r
108 lr_pwr_lo, lr_pwr_hi, lr_pwr_oe1, lr_pwr_oe2, lr_pwr_oe3, lr_pwr_oe4,\r
109 adc_d, lr_adc_clk,\r
110 lr_ssp_frame, lr_ssp_din, ssp_dout, lr_ssp_clk,\r
111 cross_hi, cross_lo,\r
112 lr_dbg,\r
113 lo_is_125khz\r
114);\r
115\r
116lo_simulate ls(\r
117 pck0, ck_1356meg, ck_1356megb,\r
118 ls_pwr_lo, ls_pwr_hi, ls_pwr_oe1, ls_pwr_oe2, ls_pwr_oe3, ls_pwr_oe4,\r
119 adc_d, ls_adc_clk,\r
120 ls_ssp_frame, ls_ssp_din, ssp_dout, ls_ssp_clk,\r
121 cross_hi, cross_lo,\r
122 ls_dbg\r
123);\r
124\r
125hi_read_tx ht(\r
126 pck0, ck_1356meg, ck_1356megb,\r
127 ht_pwr_lo, ht_pwr_hi, ht_pwr_oe1, ht_pwr_oe2, ht_pwr_oe3, ht_pwr_oe4,\r
128 adc_d, ht_adc_clk,\r
129 ht_ssp_frame, ht_ssp_din, ssp_dout, ht_ssp_clk,\r
130 cross_hi, cross_lo,\r
131 ht_dbg,\r
132 hi_read_tx_shallow_modulation\r
133);\r
134\r
135hi_read_rx_xcorr hrxc(\r
136 pck0, ck_1356meg, ck_1356megb,\r
137 hrxc_pwr_lo, hrxc_pwr_hi, hrxc_pwr_oe1, hrxc_pwr_oe2, hrxc_pwr_oe3, hrxc_pwr_oe4,\r
138 adc_d, hrxc_adc_clk,\r
139 hrxc_ssp_frame, hrxc_ssp_din, ssp_dout, hrxc_ssp_clk,\r
140 cross_hi, cross_lo,\r
141 hrxc_dbg,\r
142 hi_read_rx_xcorr_848, hi_read_rx_xcorr_snoop\r
143);\r
144\r
145hi_simulate hs(\r
146 pck0, ck_1356meg, ck_1356megb,\r
147 hs_pwr_lo, hs_pwr_hi, hs_pwr_oe1, hs_pwr_oe2, hs_pwr_oe3, hs_pwr_oe4,\r
148 adc_d, hs_adc_clk,\r
149 hs_ssp_frame, hs_ssp_din, ssp_dout, hs_ssp_clk,\r
150 cross_hi, cross_lo,\r
151 hs_dbg,\r
152 hi_simulate_mod_type\r
153);\r
154\r
155hi_iso14443a hisn(\r
156 pck0, ck_1356meg, ck_1356megb,\r
157 hisn_pwr_lo, hisn_pwr_hi, hisn_pwr_oe1, hisn_pwr_oe2, hisn_pwr_oe3, hisn_pwr_oe4,\r
158 adc_d, hisn_adc_clk,\r
159 hisn_ssp_frame, hisn_ssp_din, ssp_dout, hisn_ssp_clk,\r
160 cross_hi, cross_lo,\r
161 hisn_dbg,\r
162 hi_simulate_mod_type\r
163);\r
164\r
165// Major modes:\r
166// 000 -- LF reader (generic)\r
167// 001 -- LF simulated tag (generic)\r
168// 010 -- HF reader, transmitting to tag; modulation depth selectable\r
169// 011 -- HF reader, receiving from tag, correlating as it goes; frequency selectable\r
170// 100 -- HF simulated tag\r
171// 101 -- HF ISO14443-A\r
172// 110 -- unused\r
173// 111 -- everything off\r
174\r
175mux8 mux_ssp_clk (major_mode, ssp_clk, lr_ssp_clk, ls_ssp_clk, ht_ssp_clk, hrxc_ssp_clk, hs_ssp_clk, hisn_ssp_clk, 1'b0, 1'b0);\r
176mux8 mux_ssp_din (major_mode, ssp_din, lr_ssp_din, ls_ssp_din, ht_ssp_din, hrxc_ssp_din, hs_ssp_din, hisn_ssp_din, 1'b0, 1'b0);\r
177mux8 mux_ssp_frame (major_mode, ssp_frame, lr_ssp_frame, ls_ssp_frame, ht_ssp_frame, hrxc_ssp_frame, hs_ssp_frame, hisn_ssp_frame, 1'b0, 1'b0);\r
178mux8 mux_pwr_oe1 (major_mode, pwr_oe1, lr_pwr_oe1, ls_pwr_oe1, ht_pwr_oe1, hrxc_pwr_oe1, hs_pwr_oe1, hisn_pwr_oe1, 1'b0, 1'b0);\r
179mux8 mux_pwr_oe2 (major_mode, pwr_oe2, lr_pwr_oe2, ls_pwr_oe2, ht_pwr_oe2, hrxc_pwr_oe2, hs_pwr_oe2, hisn_pwr_oe2, 1'b0, 1'b0);\r
180mux8 mux_pwr_oe3 (major_mode, pwr_oe3, lr_pwr_oe3, ls_pwr_oe3, ht_pwr_oe3, hrxc_pwr_oe3, hs_pwr_oe3, hisn_pwr_oe3, 1'b0, 1'b0);\r
181mux8 mux_pwr_oe4 (major_mode, pwr_oe4, lr_pwr_oe4, ls_pwr_oe4, ht_pwr_oe4, hrxc_pwr_oe4, hs_pwr_oe4, hisn_pwr_oe4, 1'b0, 1'b0);\r
182mux8 mux_pwr_lo (major_mode, pwr_lo, lr_pwr_lo, ls_pwr_lo, ht_pwr_lo, hrxc_pwr_lo, hs_pwr_lo, hisn_pwr_lo, 1'b0, 1'b0);\r
183mux8 mux_pwr_hi (major_mode, pwr_hi, lr_pwr_hi, ls_pwr_hi, ht_pwr_hi, hrxc_pwr_hi, hs_pwr_hi, hisn_pwr_hi, 1'b0, 1'b0);\r
184mux8 mux_adc_clk (major_mode, adc_clk, lr_adc_clk, ls_adc_clk, ht_adc_clk, hrxc_adc_clk, hs_adc_clk, hisn_adc_clk, 1'b0, 1'b0);\r
185mux8 mux_dbg (major_mode, dbg, lr_dbg, ls_dbg, ht_dbg, hrxc_dbg, hs_dbg, hisn_dbg, 1'b0, 1'b0);\r
186\r
187// In all modes, let the ADC's outputs be enabled.\r
188assign adc_noe = 1'b0;\r
189\r
190endmodule\r
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