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Merge pull request #969 from pwpiwi/gcc10_fixes
[proxmark3-svn] / armsrc / fpgaloader.h
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add4d470 1//-----------------------------------------------------------------------------
2// Jonathan Westhues, April 2006
3// iZsh <izsh at fail0verflow.com>, 2014
4//
5// This code is licensed to you under the terms of the GNU GPL, version 2 or,
6// at your option, any later version. See the LICENSE.txt file for the text of
7// the license.
8//-----------------------------------------------------------------------------
9// Routines to load the FPGA image, and then to configure the FPGA's major
10// mode once it is configured.
11//-----------------------------------------------------------------------------
12
472345da 13#ifndef __FPGALOADER_H
14#define __FPGALOADER_H
15
16#include <stdint.h>
17#include <stdbool.h>
18
add4d470 19void FpgaSendCommand(uint16_t cmd, uint16_t v);
fc52fbd4 20void FpgaWriteConfWord(uint16_t v);
add4d470 21void FpgaDownloadAndGo(int bitstream_version);
cd028159 22void FpgaSetupSsc(uint16_t mode);
add4d470 23void SetupSpi(int mode);
b4ba1eea 24bool FpgaSetupSscDma(uint8_t *buf, uint16_t sample_count);
e2012d1b 25void Fpga_print_status();
fdcfbdcc 26int FpgaGetCurrent();
fc52fbd4 27void FpgaEnableTracing(void);
28void FpgaDisableTracing(void);
d9de20fa 29#define FpgaDisableSscDma(void) AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTDIS;
add4d470 30#define FpgaEnableSscDma(void) AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTEN;
31void SetAdcMuxFor(uint32_t whichGpio);
32
fb228974 33// definitions for multiple FPGA config files support
fb228974 34#define FPGA_BITSTREAM_LF 1
35#define FPGA_BITSTREAM_HF 2
36
add4d470 37// Definitions for the FPGA commands.
7a537397 38#define FPGA_CMD_MASK 0xF000
fc52fbd4 39// BOTH
7a537397 40#define FPGA_CMD_SET_CONFREG (1<<12)
fc52fbd4 41// LF
7a537397 42#define FPGA_CMD_SET_DIVISOR (2<<12)
43#define FPGA_CMD_SET_EDGE_DETECT_THRESHOLD (3<<12)
fc52fbd4 44// HF
7a537397 45#define FPGA_CMD_TRACE_ENABLE (2<<12)
fc52fbd4 46
add4d470 47// Definitions for the FPGA configuration word.
7a537397 48#define FPGA_MAJOR_MODE_MASK 0x01C0
add4d470 49// LF
cd028159 50#define FPGA_MAJOR_MODE_LF_ADC (0<<6)
51#define FPGA_MAJOR_MODE_LF_EDGE_DETECT (1<<6)
52#define FPGA_MAJOR_MODE_LF_PASSTHRU (2<<6)
add4d470 53// HF
cd028159 54#define FPGA_MAJOR_MODE_HF_READER (0<<6)
55#define FPGA_MAJOR_MODE_HF_SIMULATOR (1<<6)
56#define FPGA_MAJOR_MODE_HF_ISO14443A (2<<6)
57#define FPGA_MAJOR_MODE_HF_SNOOP (3<<6)
58#define FPGA_MAJOR_MODE_HF_GET_TRACE (4<<6)
add4d470 59// BOTH
cd028159 60#define FPGA_MAJOR_MODE_OFF (7<<6)
fc52fbd4 61
7a537397 62#define FPGA_MINOR_MODE_MASK 0x003F
add4d470 63// Options for LF_ADC
d9de20fa 64#define FPGA_LF_ADC_READER_FIELD (1<<0)
fc52fbd4 65
add4d470 66// Options for LF_EDGE_DETECT
d9de20fa 67#define FPGA_LF_EDGE_DETECT_READER_FIELD (1<<0)
00848e09 68#define FPGA_LF_EDGE_DETECT_TOGGLE_MODE (2<<0)
fc52fbd4 69
5ea2a248 70// Options for the HF reader
71#define FPGA_HF_READER_MODE_RECEIVE_IQ (0<<0)
72#define FPGA_HF_READER_MODE_RECEIVE_AMPLITUDE (1<<0)
73#define FPGA_HF_READER_MODE_RECEIVE_PHASE (2<<0)
74#define FPGA_HF_READER_MODE_SEND_FULL_MOD (3<<0)
75#define FPGA_HF_READER_MODE_SEND_SHALLOW_MOD (4<<0)
76#define FPGA_HF_READER_MODE_SNOOP_IQ (5<<0)
77#define FPGA_HF_READER_MODE_SNOOP_AMPLITUDE (6<<0)
78#define FPGA_HF_READER_MODE_SNOOP_PHASE (7<<0)
cd028159 79#define FPGA_HF_READER_MODE_SEND_JAM (8<<0)
fc52fbd4 80
cd028159 81#define FPGA_HF_READER_SUBCARRIER_848_KHZ (0<<4)
82#define FPGA_HF_READER_SUBCARRIER_424_KHZ (1<<4)
83#define FPGA_HF_READER_SUBCARRIER_212_KHZ (2<<4)
fc52fbd4 84
add4d470 85// Options for the HF simulated tag, how to modulate
d9de20fa 86#define FPGA_HF_SIMULATOR_NO_MODULATION (0<<0)
87#define FPGA_HF_SIMULATOR_MODULATE_BPSK (1<<0)
88#define FPGA_HF_SIMULATOR_MODULATE_212K (2<<0)
89#define FPGA_HF_SIMULATOR_MODULATE_424K (4<<0)
90#define FPGA_HF_SIMULATOR_MODULATE_424K_8BIT 0x5//101
add4d470 91
92// Options for ISO14443A
d9de20fa 93#define FPGA_HF_ISO14443A_SNIFFER (0<<0)
94#define FPGA_HF_ISO14443A_TAGSIM_LISTEN (1<<0)
95#define FPGA_HF_ISO14443A_TAGSIM_MOD (2<<0)
96#define FPGA_HF_ISO14443A_READER_LISTEN (3<<0)
97#define FPGA_HF_ISO14443A_READER_MOD (4<<0)
472345da 98
99#endif
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