]> git.zerfleddert.de Git - proxmark3-svn/blame - fpga/fpga.ucf
Update README.md
[proxmark3-svn] / fpga / fpga.ucf
CommitLineData
ba06a4b6 1# See the schematic for the pin assignment.
2
5ea2a248 3NET "adc_d<0>" LOC = "P62" ;
4NET "adc_d<1>" LOC = "P60" ;
5NET "adc_d<2>" LOC = "P58" ;
6NET "adc_d<3>" LOC = "P57" ;
7NET "adc_d<4>" LOC = "P56" ;
8NET "adc_d<5>" LOC = "P55" ;
9NET "adc_d<6>" LOC = "P54" ;
10NET "adc_d<7>" LOC = "P53" ;
11NET "cross_hi" LOC = "P88" ;
12#NET "miso" LOC = "P40" ;
ba06a4b6 13#PACE: Start of Constraints generated by PACE
14
15#PACE: Start of PACE I/O Pin Assignments
5ea2a248 16NET "adc_clk" LOC = "P46" ;
17NET "adc_noe" LOC = "P47" ;
18NET "ck_1356meg" LOC = "P91" ;
19NET "ck_1356megb" LOC = "P93" ;
20NET "cross_lo" LOC = "P87" ;
21NET "dbg" LOC = "P22" ;
22NET "mosi" LOC = "P43" ;
23NET "ncs" LOC = "P44" ;
24NET "pck0" LOC = "P36" ;
25NET "pwr_hi" LOC = "P80" ;
26NET "pwr_lo" LOC = "P81" ;
27NET "pwr_oe1" LOC = "P82" ;
28NET "pwr_oe2" LOC = "P83" ;
29NET "pwr_oe3" LOC = "P84" ;
30NET "pwr_oe4" LOC = "P86" ;
31NET "spck" LOC = "P39" ;
32NET "ssp_clk" LOC = "P71" ;
33NET "ssp_din" LOC = "P32" ;
34NET "ssp_dout" LOC = "P34" ;
35NET "ssp_frame" LOC = "P31" ;
ba06a4b6 36
37#PACE: Start of PACE Area Constraints
38
39#PACE: Start of PACE Prohibit Constraints
40
41#PACE: End of Constraints generated by PACE
e691fc45 42
43# definition of Clock nets:
44NET "ck_1356meg" TNM_NET = "clk_net_1356" ;
45NET "ck_1356megb" TNM_NET = "clk_net_1356b" ;
46NET "pck0" TNM_NET = "clk_net_pck0" ;
47NET "spck" TNM_NET = "clk_net_spck" ;
48
49# Timing specs of clock nets:
50TIMEGRP "clk_net_1356_all" = "clk_net_1356" "clk_net_1356b" ;
51TIMESPEC "TS_1356MHz" = PERIOD "clk_net_1356_all" 74 ns HIGH 37 ns ;
52TIMESPEC "TS_24MHz" = PERIOD "clk_net_pck0" 42 ns HIGH 21 ns ;
53TIMESPEC "TS_4MHz" = PERIOD "clk_net_spck" 250 ns HIGH 125 ns ;
54
Impressum, Datenschutz