[proxmark3-svn] / armsrc / fpgaloader.c

//-----------------------------------------------------------------------------
// Jonathan Westhues, April 2006
// iZsh <izsh at fail0verflow.com>, 2014
//
// This code is licensed to you under the terms of the GNU GPL, version 2 or,
// at your option, any later version. See the LICENSE.txt file for the text of
// the license.
//-----------------------------------------------------------------------------
// Routines to load the FPGA image, and then to configure the FPGA's major
// mode once it is configured.
//-----------------------------------------------------------------------------

#include <stdint.h>
#include <stddef.h>
#include <stdbool.h>
#include "fpgaloader.h"
#include "proxmark3.h"
#include "util.h"
#include "string.h"
#include "BigBuf.h"
#include "zlib.h"

extern void Dbprintf(const char *fmt, ...);

// remember which version of the bitstream we have already downloaded to the FPGA
static int downloaded_bitstream = FPGA_BITSTREAM_ERR;

// this is where the bitstreams are located in memory:
extern uint8_t _binary_fpga_lf_bit_start, _binary_fpga_lf_bit_end;
extern uint8_t _binary_fpga_hf_bit_start, _binary_fpga_hf_bit_end;
static uint8_t *fpga_image_ptr = NULL;

static const uint8_t _bitparse_fixed_header[] = {0x00, 0x09, 0x0f, 0xf0, 0x0f, 0xf0, 0x0f, 0xf0, 0x0f, 0xf0, 0x00, 0x00, 0x01};
#define FPGA_BITSTREAM_FIXED_HEADER_SIZE	sizeof(_bitparse_fixed_header)
#define OUTPUT_BUFFER_LEN 80

//-----------------------------------------------------------------------------
// Set up the Serial Peripheral Interface as master
// Used to write the FPGA config word
// May also be used to write to other SPI attached devices like an LCD
//-----------------------------------------------------------------------------
void SetupSpi(int mode)
{
	// PA10 -> SPI_NCS2 chip select (LCD)
	// PA11 -> SPI_NCS0 chip select (FPGA)
	// PA12 -> SPI_MISO Master-In Slave-Out
	// PA13 -> SPI_MOSI Master-Out Slave-In
	// PA14 -> SPI_SPCK Serial Clock

	// Disable PIO control of the following pins, allows use by the SPI peripheral
	AT91C_BASE_PIOA->PIO_PDR =
		GPIO_NCS0	|
		GPIO_NCS2 	|
		GPIO_MISO	|
		GPIO_MOSI	|
		GPIO_SPCK;

	AT91C_BASE_PIOA->PIO_ASR =
		GPIO_NCS0	|
		GPIO_MISO	|
		GPIO_MOSI	|
		GPIO_SPCK;

	AT91C_BASE_PIOA->PIO_BSR = GPIO_NCS2;

	//enable the SPI Peripheral clock
	AT91C_BASE_PMC->PMC_PCER = (1<<AT91C_ID_SPI);
	// Enable SPI
	AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SPIEN;

	switch (mode) {
		case SPI_FPGA_MODE:
			AT91C_BASE_SPI->SPI_MR =
				( 0 << 24)	|	// Delay between chip selects (take default: 6 MCK periods)
				(14 << 16)	|	// Peripheral Chip Select (selects FPGA SPI_NCS0 or PA11)
				( 0 << 7)	|	// Local Loopback Disabled
				( 1 << 4)	|	// Mode Fault Detection disabled
				( 0 << 2)	|	// Chip selects connected directly to peripheral
				( 0 << 1) 	|	// Fixed Peripheral Select
				( 1 << 0);		// Master Mode
			AT91C_BASE_SPI->SPI_CSR[0] =
				( 1 << 24)	|	// Delay between Consecutive Transfers (32 MCK periods)
				( 1 << 16)	|	// Delay Before SPCK (1 MCK period)
				( 6 << 8)	|	// Serial Clock Baud Rate (baudrate = MCK/6 = 24Mhz/6 = 4M baud
				( 8 << 4)	|	// Bits per Transfer (16 bits)
				( 0 << 3)	|	// Chip Select inactive after transfer
				( 1 << 1)	|	// Clock Phase data captured on leading edge, changes on following edge
				( 0 << 0);		// Clock Polarity inactive state is logic 0
			break;
		case SPI_LCD_MODE:
			AT91C_BASE_SPI->SPI_MR =
				( 0 << 24)	|	// Delay between chip selects (take default: 6 MCK periods)
				(11 << 16)	|	// Peripheral Chip Select (selects LCD SPI_NCS2 or PA10)
				( 0 << 7)	|	// Local Loopback Disabled
				( 1 << 4)	|	// Mode Fault Detection disabled
				( 0 << 2)	|	// Chip selects connected directly to peripheral
				( 0 << 1) 	|	// Fixed Peripheral Select
				( 1 << 0);		// Master Mode
			AT91C_BASE_SPI->SPI_CSR[2] =
				( 1 << 24)	|	// Delay between Consecutive Transfers (32 MCK periods)
				( 1 << 16)	|	// Delay Before SPCK (1 MCK period)
				( 6 << 8)	|	// Serial Clock Baud Rate (baudrate = MCK/6 = 24Mhz/6 = 4M baud
				( 1 << 4)	|	// Bits per Transfer (9 bits)
				( 0 << 3)	|	// Chip Select inactive after transfer
				( 1 << 1)	|	// Clock Phase data captured on leading edge, changes on following edge
				( 0 << 0);		// Clock Polarity inactive state is logic 0
			break;
		default:				// Disable SPI
			AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SPIDIS;
			break;
	}
}

//-----------------------------------------------------------------------------
// Set up the synchronous serial port, with the one set of options that we
// always use when we are talking to the FPGA. Both RX and TX are enabled.
//-----------------------------------------------------------------------------
void FpgaSetupSsc(void)
{
	// First configure the GPIOs, and get ourselves a clock.
	AT91C_BASE_PIOA->PIO_ASR =
		GPIO_SSC_FRAME	|
		GPIO_SSC_DIN	|
		GPIO_SSC_DOUT	|
		GPIO_SSC_CLK;
	AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT;

	AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_SSC);

	// Now set up the SSC proper, starting from a known state.
	AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST;

	// RX clock comes from TX clock, RX starts when TX starts, data changes
	// on RX clock rising edge, sampled on falling edge
	AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(1) | SSC_CLOCK_MODE_START(1);

	// 8 bits per transfer, no loopback, MSB first, 1 transfer per sync
	// pulse, no output sync
	AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(8) |	AT91C_SSC_MSBF | SSC_FRAME_MODE_WORDS_PER_TRANSFER(0);

	// clock comes from TK pin, no clock output, outputs change on falling
	// edge of TK, sample on rising edge of TK, start on positive-going edge of sync
	AT91C_BASE_SSC->SSC_TCMR = SSC_CLOCK_MODE_SELECT(2) |	SSC_CLOCK_MODE_START(5);

	// tx framing is the same as the rx framing
	AT91C_BASE_SSC->SSC_TFMR = AT91C_BASE_SSC->SSC_RFMR;

	AT91C_BASE_SSC->SSC_CR = AT91C_SSC_RXEN | AT91C_SSC_TXEN;
}

//-----------------------------------------------------------------------------
// Set up DMA to receive samples from the FPGA. We will use the PDC, with
// a single buffer as a circular buffer (so that we just chain back to
// ourselves, not to another buffer). The stuff to manipulate those buffers
// is in apps.h, because it should be inlined, for speed.
//-----------------------------------------------------------------------------
bool FpgaSetupSscDma(uint8_t *buf, int len)
{
	if (buf == NULL) {
        return false;
    }

	AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTDIS;	// Disable DMA Transfer
	AT91C_BASE_PDC_SSC->PDC_RPR = (uint32_t) buf;		// transfer to this memory address
	AT91C_BASE_PDC_SSC->PDC_RCR = len;					// transfer this many bytes
	AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) buf;		// next transfer to same memory address
	AT91C_BASE_PDC_SSC->PDC_RNCR = len;					// ... with same number of bytes
	AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTEN;		// go!
    
    return true;
}


uint8_t get_from_fpga_stream(z_streamp compressed_fpga_stream, uint8_t *output_buffer)
{
	if (fpga_image_ptr == compressed_fpga_stream->next_out) {	// need more data
		compressed_fpga_stream->next_out = output_buffer;
		compressed_fpga_stream->avail_out = OUTPUT_BUFFER_LEN;
		fpga_image_ptr = output_buffer;
		int res = inflate(compressed_fpga_stream, Z_SYNC_FLUSH);
		// if (res != Z_OK && res != Z_STREAM_END) {
			Dbprintf("inflate returned: %d, %s", res, compressed_fpga_stream->msg);
		// }
	}

	Dbprintf("get_from_fpga_stream() returns %02x", *fpga_image_ptr);
	return *fpga_image_ptr++;
}


static voidpf fpga_inflate_malloc(voidpf opaque, uInt items, uInt size)
{
	Dbprintf("zlib requested %d bytes", items*size);
	return BigBuf_malloc(items*size);
}


static void fpga_inflate_free(voidpf opaque, voidpf address)
{
	Dbprintf("zlib wants to free memory");
	BigBuf_free_keep_EM();
}


void init_fpga_inflate(z_streamp compressed_fpga_stream, uint8_t *fpga_image_start, uint32_t fpga_image_size, uint8_t *output_buffer)
{
	// initialize z_stream structure for inflate:
	compressed_fpga_stream->next_in = fpga_image_start;
	compressed_fpga_stream->avail_in = fpga_image_size;
	compressed_fpga_stream->next_out = output_buffer;
	compressed_fpga_stream->avail_out = OUTPUT_BUFFER_LEN;
	compressed_fpga_stream->zalloc = &fpga_inflate_malloc;
	compressed_fpga_stream->zfree = &fpga_inflate_free;

	// initialize inflate to automatically detect header:
	int res = inflateInit2(compressed_fpga_stream, 15+32);

	fpga_image_ptr = output_buffer;
	
	Dbprintf("InflateInit returned %d", res);
	Dbprintf("fpga_image_ptr pointing at %02x %02x %02x %02x", fpga_image_ptr[0], fpga_image_ptr[1], fpga_image_ptr[2], fpga_image_ptr[3]);
	Dbprintf("zstream->next_in pointing at %02x %02x %02x %02x", compressed_fpga_stream->next_in[0], compressed_fpga_stream->next_in[1], compressed_fpga_stream->next_in[2], compressed_fpga_stream->next_in[3]);
}


bool reset_fpga_stream(int bitstream_version, z_streamp compressed_fpga_stream, uint8_t *output_buffer)
{
	uint8_t header[FPGA_BITSTREAM_FIXED_HEADER_SIZE];
	uint8_t *fpga_image_start;
	uint32_t fpga_image_size;
	
	if (bitstream_version == FPGA_BITSTREAM_LF) {
		fpga_image_start = &_binary_fpga_lf_bit_start;
		fpga_image_size = (uint32_t)&_binary_fpga_lf_bit_end - (uint32_t)&_binary_fpga_lf_bit_start;
	} else if (bitstream_version == FPGA_BITSTREAM_HF) {
		fpga_image_start = &_binary_fpga_hf_bit_start;
		fpga_image_size = (uint32_t)&_binary_fpga_hf_bit_end - (uint32_t)&_binary_fpga_hf_bit_start;
	} else {
		return false;
	}	

	init_fpga_inflate(compressed_fpga_stream, fpga_image_start, fpga_image_size, output_buffer);

	for (uint16_t i = 0; i < FPGA_BITSTREAM_FIXED_HEADER_SIZE; i++) {
		header[i] = get_from_fpga_stream(compressed_fpga_stream, output_buffer);
	}
	
	// Check for a valid .bit file (starts with _bitparse_fixed_header)
	if(memcmp(_bitparse_fixed_header, header, FPGA_BITSTREAM_FIXED_HEADER_SIZE) == 0) {
		return true;
	} else {
		return false;
	}
}


static void DownloadFPGA_byte(unsigned char w)
{
#define SEND_BIT(x) { if(w & (1<<x) ) HIGH(GPIO_FPGA_DIN); else LOW(GPIO_FPGA_DIN); HIGH(GPIO_FPGA_CCLK); LOW(GPIO_FPGA_CCLK); }
	SEND_BIT(7);
	SEND_BIT(6);
	SEND_BIT(5);
	SEND_BIT(4);
	SEND_BIT(3);
	SEND_BIT(2);
	SEND_BIT(1);
	SEND_BIT(0);
}

// Download the fpga image starting at current stream position with length FpgaImageLen bytes
static void DownloadFPGA(int FpgaImageLen, z_streamp compressed_fpga_stream, uint8_t *output_buffer)
{
	Dbprintf("Would have loaded FPGA");
	return;

	int i=0;

	AT91C_BASE_PIOA->PIO_OER = GPIO_FPGA_ON;
	AT91C_BASE_PIOA->PIO_PER = GPIO_FPGA_ON;
	HIGH(GPIO_FPGA_ON);		// ensure everything is powered on

	SpinDelay(50);

	LED_D_ON();

	// These pins are inputs
    AT91C_BASE_PIOA->PIO_ODR =
    	GPIO_FPGA_NINIT |
    	GPIO_FPGA_DONE;
	// PIO controls the following pins
    AT91C_BASE_PIOA->PIO_PER =
    	GPIO_FPGA_NINIT |
    	GPIO_FPGA_DONE;
	// Enable pull-ups
	AT91C_BASE_PIOA->PIO_PPUER =
		GPIO_FPGA_NINIT |
		GPIO_FPGA_DONE;

	// setup initial logic state
	HIGH(GPIO_FPGA_NPROGRAM);
	LOW(GPIO_FPGA_CCLK);
	LOW(GPIO_FPGA_DIN);
	// These pins are outputs
	AT91C_BASE_PIOA->PIO_OER =
		GPIO_FPGA_NPROGRAM	|
		GPIO_FPGA_CCLK		|
		GPIO_FPGA_DIN;

	// enter FPGA configuration mode
	LOW(GPIO_FPGA_NPROGRAM);
	SpinDelay(50);
	HIGH(GPIO_FPGA_NPROGRAM);

	i=100000;
	// wait for FPGA ready to accept data signal
	while ((i) && ( !(AT91C_BASE_PIOA->PIO_PDSR & GPIO_FPGA_NINIT ) ) ) {
		i--;
	}

	// crude error indicator, leave both red LEDs on and return
	if (i==0){
		LED_C_ON();
		LED_D_ON();
		return;
	}

	while(FpgaImageLen-->0) {
		DownloadFPGA_byte(get_from_fpga_stream(compressed_fpga_stream, output_buffer));
	}

	// continue to clock FPGA until ready signal goes high
	i=100000;
	while ( (i--) && ( !(AT91C_BASE_PIOA->PIO_PDSR & GPIO_FPGA_DONE ) ) ) {
		HIGH(GPIO_FPGA_CCLK);
		LOW(GPIO_FPGA_CCLK);
	}
	// crude error indicator, leave both red LEDs on and return
	if (i==0){
		LED_C_ON();
		LED_D_ON();
		return;
	}
	LED_D_OFF();
}


/* Simple Xilinx .bit parser. The file starts with the fixed opaque byte sequence
 * 00 09 0f f0 0f f0 0f f0 0f f0 00 00 01
 * After that the format is 1 byte section type (ASCII character), 2 byte length
 * (big endian), <length> bytes content. Except for section 'e' which has 4 bytes
 * length.
 */
int bitparse_find_section(char section_name, unsigned int *section_length, z_streamp compressed_fpga_stream, uint8_t *output_buffer)
{
	int result = 0;
	#define MAX_FPGA_BIT_STREAM_HEADER_SEARCH 100  // maximum number of bytes to search for the requested section
	uint16_t numbytes = 0;
	while(numbytes < MAX_FPGA_BIT_STREAM_HEADER_SEARCH) {
		char current_name = get_from_fpga_stream(compressed_fpga_stream, output_buffer);
		numbytes++;
		unsigned int current_length = 0;
		if(current_name < 'a' || current_name > 'e') {
			/* Strange section name, abort */
			break;
		}
		current_length = 0;
		switch(current_name) {
		case 'e':
			/* Four byte length field */
			current_length += get_from_fpga_stream(compressed_fpga_stream, output_buffer) << 24;
			current_length += get_from_fpga_stream(compressed_fpga_stream, output_buffer) << 16;
			numbytes += 2;
		default: /* Fall through, two byte length field */
			current_length += get_from_fpga_stream(compressed_fpga_stream, output_buffer) << 8;
			current_length += get_from_fpga_stream(compressed_fpga_stream, output_buffer) << 0;
			numbytes += 2;
		}

		if(current_name != 'e' && current_length > 255) {
			/* Maybe a parse error */
			break;
		}

		if(current_name == section_name) {
			/* Found it */
			*section_length = current_length;
			result = 1;
			break;
		}

		for (uint16_t i = 0; i < current_length && numbytes < MAX_FPGA_BIT_STREAM_HEADER_SEARCH; i++) {
			get_from_fpga_stream(compressed_fpga_stream, output_buffer);
			numbytes++;
		}
	}

	return result;
}


//-----------------------------------------------------------------------------
// Find out which FPGA image format is stored in flash, then call DownloadFPGA
// with the right parameters to download the image
//-----------------------------------------------------------------------------
void FpgaDownloadAndGo(int bitstream_version)
{
	z_stream compressed_fpga_stream;
	uint8_t output_buffer[OUTPUT_BUFFER_LEN];
	
	// check whether or not the bitstream is already loaded
	if (downloaded_bitstream == bitstream_version)
		return;

	if (!reset_fpga_stream(bitstream_version, &compressed_fpga_stream, output_buffer)) {
		return;
	}
	
	unsigned int bitstream_length;
	if(bitparse_find_section('e', &bitstream_length, &compressed_fpga_stream, output_buffer)) {
		DownloadFPGA(bitstream_length, &compressed_fpga_stream, output_buffer);
		downloaded_bitstream = bitstream_version;
		return; /* All done */
	}
}	


void FpgaGatherVersion(int bitstream_version, char *dst, int len)
{
	unsigned int fpga_info_len;
	char tempstr[40];
	z_stream compressed_fpga_stream;
	uint8_t output_buffer[OUTPUT_BUFFER_LEN];
	
	dst[0] = '\0';
	
	if (!reset_fpga_stream(bitstream_version, &compressed_fpga_stream, output_buffer)) {
		return;
	}

	if(bitparse_find_section('a', &fpga_info_len, &compressed_fpga_stream, output_buffer)) {
		for (uint16_t i = 0; i < fpga_info_len; i++) {
			char c = (char)get_from_fpga_stream(&compressed_fpga_stream, output_buffer);
			if (i < sizeof(tempstr)) {
				tempstr[i] = c;
			}
		}
		if (!memcmp("fpga_lf", tempstr, 7))
			strncat(dst, "LF ", len-1);
		else if (!memcmp("fpga_hf", tempstr, 7))
			strncat(dst, "HF ", len-1);
	}
	strncat(dst, "FPGA image built", len-1);
	if(bitparse_find_section('b', &fpga_info_len, &compressed_fpga_stream, output_buffer)) {
		strncat(dst, " for ", len-1);
		for (uint16_t i = 0; i < fpga_info_len; i++) {
			char c = (char)get_from_fpga_stream(&compressed_fpga_stream, output_buffer);
			if (i < sizeof(tempstr)) {
				tempstr[i] = c;
			}
		}
		strncat(dst, tempstr, len-1);
	}
	if(bitparse_find_section('c', &fpga_info_len, &compressed_fpga_stream, output_buffer)) {
		strncat(dst, " on ", len-1);
		for (uint16_t i = 0; i < fpga_info_len; i++) {
			char c = (char)get_from_fpga_stream(&compressed_fpga_stream, output_buffer);
			if (i < sizeof(tempstr)) {
				tempstr[i] = c;
			}
		}
		strncat(dst, tempstr, len-1);
	}
	if(bitparse_find_section('d', &fpga_info_len, &compressed_fpga_stream, output_buffer)) {
		strncat(dst, " at ", len-1);
		for (uint16_t i = 0; i < fpga_info_len; i++) {
			char c = (char)get_from_fpga_stream(&compressed_fpga_stream, output_buffer);
			if (i < sizeof(tempstr)) {
				tempstr[i] = c;
			}
		}
		strncat(dst, tempstr, len-1);
	}
}


//-----------------------------------------------------------------------------
// Send a 16 bit command/data pair to the FPGA.
// The bit format is:  C3 C2 C1 C0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
// where C is the 4 bit command and D is the 12 bit data
//-----------------------------------------------------------------------------
void FpgaSendCommand(uint16_t cmd, uint16_t v)
{
	SetupSpi(SPI_FPGA_MODE);
	while ((AT91C_BASE_SPI->SPI_SR & AT91C_SPI_TXEMPTY) == 0);		// wait for the transfer to complete
	AT91C_BASE_SPI->SPI_TDR = AT91C_SPI_LASTXFER | cmd | v;		// send the data
}
//-----------------------------------------------------------------------------
// Write the FPGA setup word (that determines what mode the logic is in, read
// vs. clone vs. etc.). This is now a special case of FpgaSendCommand() to
// avoid changing this function's occurence everywhere in the source code.
//-----------------------------------------------------------------------------
void FpgaWriteConfWord(uint8_t v)
{
	FpgaSendCommand(FPGA_CMD_SET_CONFREG, v);
}

//-----------------------------------------------------------------------------
// Set up the CMOS switches that mux the ADC: four switches, independently
// closable, but should only close one at a time. Not an FPGA thing, but
// the samples from the ADC always flow through the FPGA.
//-----------------------------------------------------------------------------
void SetAdcMuxFor(uint32_t whichGpio)
{
	AT91C_BASE_PIOA->PIO_OER =
		GPIO_MUXSEL_HIPKD |
		GPIO_MUXSEL_LOPKD |
		GPIO_MUXSEL_LORAW |
		GPIO_MUXSEL_HIRAW;

	AT91C_BASE_PIOA->PIO_PER =
		GPIO_MUXSEL_HIPKD |
		GPIO_MUXSEL_LOPKD |
		GPIO_MUXSEL_LORAW |
		GPIO_MUXSEL_HIRAW;

	LOW(GPIO_MUXSEL_HIPKD);
	LOW(GPIO_MUXSEL_HIRAW);
	LOW(GPIO_MUXSEL_LORAW);
	LOW(GPIO_MUXSEL_LOPKD);

	HIGH(whichGpio);
}
Commit	Line	Data
15c4dc5a	1	//-----------------------------------------------------------------------------
bd20f8f4	2	// Jonathan Westhues, April 2006
62638f87	3	// iZsh <izsh at fail0verflow.com>, 2014
bd20f8f4	4	//
	5	// This code is licensed to you under the terms of the GNU GPL, version 2 or,
	6	// at your option, any later version. See the LICENSE.txt file for the text of
	7	// the license.
	8	//-----------------------------------------------------------------------------
15c4dc5a	9	// Routines to load the FPGA image, and then to configure the FPGA's major
15c4dc5a	10	// mode once it is configured.
15c4dc5a	11	//-----------------------------------------------------------------------------
add4d470	12
	13	#include <stdint.h>
	14	#include <stddef.h>
	15	#include <stdbool.h>
	16	#include "fpgaloader.h"
e30c654b	17	#include "proxmark3.h"
f7e3ed82	18	#include "util.h"
9ab7a6c7	19	#include "string.h"
add4d470	20	#include "BigBuf.h"
	21	#include "zlib.h"
	22
	23	extern void Dbprintf(const char *fmt, ...);
15c4dc5a	24
e6153040	25	// remember which version of the bitstream we have already downloaded to the FPGA
	26	static int downloaded_bitstream = FPGA_BITSTREAM_ERR;
	27
	28	// this is where the bitstreams are located in memory:
	29	extern uint8_t _binary_fpga_lf_bit_start, _binary_fpga_lf_bit_end;
	30	extern uint8_t _binary_fpga_hf_bit_start, _binary_fpga_hf_bit_end;
	31	static uint8_t *fpga_image_ptr = NULL;
	32
	33	static const uint8_t _bitparse_fixed_header[] = {0x00, 0x09, 0x0f, 0xf0, 0x0f, 0xf0, 0x0f, 0xf0, 0x0f, 0xf0, 0x00, 0x00, 0x01};
e6153040	34	#define FPGA_BITSTREAM_FIXED_HEADER_SIZE sizeof(_bitparse_fixed_header)
add4d470	35	#define OUTPUT_BUFFER_LEN 80
e6153040	36
15c4dc5a	37	//-----------------------------------------------------------------------------
	38	// Set up the Serial Peripheral Interface as master
	39	// Used to write the FPGA config word
	40	// May also be used to write to other SPI attached devices like an LCD
	41	//-----------------------------------------------------------------------------
	42	void SetupSpi(int mode)
	43	{
	44	// PA10 -> SPI_NCS2 chip select (LCD)
	45	// PA11 -> SPI_NCS0 chip select (FPGA)
	46	// PA12 -> SPI_MISO Master-In Slave-Out
	47	// PA13 -> SPI_MOSI Master-Out Slave-In
	48	// PA14 -> SPI_SPCK Serial Clock
	49
	50	// Disable PIO control of the following pins, allows use by the SPI peripheral
	51	AT91C_BASE_PIOA->PIO_PDR =
	52	GPIO_NCS0 \|
	53	GPIO_NCS2 \|
	54	GPIO_MISO \|
	55	GPIO_MOSI \|
	56	GPIO_SPCK;
	57
	58	AT91C_BASE_PIOA->PIO_ASR =
	59	GPIO_NCS0 \|
	60	GPIO_MISO \|
	61	GPIO_MOSI \|
	62	GPIO_SPCK;
	63
	64	AT91C_BASE_PIOA->PIO_BSR = GPIO_NCS2;
	65
	66	//enable the SPI Peripheral clock
	67	AT91C_BASE_PMC->PMC_PCER = (1<<AT91C_ID_SPI);
	68	// Enable SPI
	69	AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SPIEN;
	70
	71	switch (mode) {
	72	case SPI_FPGA_MODE:
	73	AT91C_BASE_SPI->SPI_MR =
	74	( 0 << 24) \| // Delay between chip selects (take default: 6 MCK periods)
	75	(14 << 16) \| // Peripheral Chip Select (selects FPGA SPI_NCS0 or PA11)
	76	( 0 << 7) \| // Local Loopback Disabled
	77	( 1 << 4) \| // Mode Fault Detection disabled
	78	( 0 << 2) \| // Chip selects connected directly to peripheral
	79	( 0 << 1) \| // Fixed Peripheral Select
	80	( 1 << 0); // Master Mode
	81	AT91C_BASE_SPI->SPI_CSR[0] =
	82	( 1 << 24) \| // Delay between Consecutive Transfers (32 MCK periods)
	83	( 1 << 16) \| // Delay Before SPCK (1 MCK period)
	84	( 6 << 8) \| // Serial Clock Baud Rate (baudrate = MCK/6 = 24Mhz/6 = 4M baud
	85	( 8 << 4) \| // Bits per Transfer (16 bits)
	86	( 0 << 3) \| // Chip Select inactive after transfer
	87	( 1 << 1) \| // Clock Phase data captured on leading edge, changes on following edge
	88	( 0 << 0); // Clock Polarity inactive state is logic 0
	89	break;
	90	case SPI_LCD_MODE:
	91	AT91C_BASE_SPI->SPI_MR =
	92	( 0 << 24) \| // Delay between chip selects (take default: 6 MCK periods)
	93	(11 << 16) \| // Peripheral Chip Select (selects LCD SPI_NCS2 or PA10)
	94	( 0 << 7) \| // Local Loopback Disabled
	95	( 1 << 4) \| // Mode Fault Detection disabled
	96	( 0 << 2) \| // Chip selects connected directly to peripheral
	97	( 0 << 1) \| // Fixed Peripheral Select
	98	( 1 << 0); // Master Mode
	99	AT91C_BASE_SPI->SPI_CSR[2] =
	100	( 1 << 24) \| // Delay between Consecutive Transfers (32 MCK periods)
101	( 1 << 16) \| // Delay Before SPCK (1 MCK period)
102	( 6 << 8) \| // Serial Clock Baud Rate (baudrate = MCK/6 = 24Mhz/6 = 4M baud
103	( 1 << 4) \| // Bits per Transfer (9 bits)
104	( 0 << 3) \| // Chip Select inactive after transfer
105	( 1 << 1) \| // Clock Phase data captured on leading edge, changes on following edge
106	( 0 << 0); // Clock Polarity inactive state is logic 0
107	break;
108	default: // Disable SPI
109	AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SPIDIS;
110	break;
111	}
112	}
113
114	//-----------------------------------------------------------------------------
115	// Set up the synchronous serial port, with the one set of options that we
116	// always use when we are talking to the FPGA. Both RX and TX are enabled.
117	//-----------------------------------------------------------------------------
118	void FpgaSetupSsc(void)
119	{
120	// First configure the GPIOs, and get ourselves a clock.
121	AT91C_BASE_PIOA->PIO_ASR =
122	GPIO_SSC_FRAME \|
123	GPIO_SSC_DIN \|
124	GPIO_SSC_DOUT \|
125	GPIO_SSC_CLK;
126	AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT;
127
128	AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_SSC);
129
130	// Now set up the SSC proper, starting from a known state.
131	AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST;
132
133	// RX clock comes from TX clock, RX starts when TX starts, data changes
134	// on RX clock rising edge, sampled on falling edge
135	AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(1) \| SSC_CLOCK_MODE_START(1);
136
137	// 8 bits per transfer, no loopback, MSB first, 1 transfer per sync
d714d3ef	138	// pulse, no output sync
902cb3c0	139	AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(8) \| AT91C_SSC_MSBF \| SSC_FRAME_MODE_WORDS_PER_TRANSFER(0);
15c4dc5a	140
15c4dc5a	141	// clock comes from TK pin, no clock output, outputs change on falling
d714d3ef	142	// edge of TK, sample on rising edge of TK, start on positive-going edge of sync
902cb3c0	143	AT91C_BASE_SSC->SSC_TCMR = SSC_CLOCK_MODE_SELECT(2) \| SSC_CLOCK_MODE_START(5);
15c4dc5a	144
	145	// tx framing is the same as the rx framing
	146	AT91C_BASE_SSC->SSC_TFMR = AT91C_BASE_SSC->SSC_RFMR;
	147
	148	AT91C_BASE_SSC->SSC_CR = AT91C_SSC_RXEN \| AT91C_SSC_TXEN;
	149	}
	150
	151	//-----------------------------------------------------------------------------
	152	// Set up DMA to receive samples from the FPGA. We will use the PDC, with
	153	// a single buffer as a circular buffer (so that we just chain back to
	154	// ourselves, not to another buffer). The stuff to manipulate those buffers
	155	// is in apps.h, because it should be inlined, for speed.
	156	//-----------------------------------------------------------------------------
d19929cb	157	bool FpgaSetupSscDma(uint8_t *buf, int len)
15c4dc5a	158	{
d19929cb	159	if (buf == NULL) {
	160	return false;
	161	}
	162
7bc95e2e	163	AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTDIS; // Disable DMA Transfer
	164	AT91C_BASE_PDC_SSC->PDC_RPR = (uint32_t) buf; // transfer to this memory address
	165	AT91C_BASE_PDC_SSC->PDC_RCR = len; // transfer this many bytes
	166	AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) buf; // next transfer to same memory address
	167	AT91C_BASE_PDC_SSC->PDC_RNCR = len; // ... with same number of bytes
	168	AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTEN; // go!
d19929cb	169
d19929cb	170	return true;
15c4dc5a	171	}
15c4dc5a	172
e6153040	173
add4d470	174	uint8_t get_from_fpga_stream(z_streamp compressed_fpga_stream, uint8_t *output_buffer)
e6153040	175	{
add4d470	176	if (fpga_image_ptr == compressed_fpga_stream->next_out) { // need more data
	177	compressed_fpga_stream->next_out = output_buffer;
	178	compressed_fpga_stream->avail_out = OUTPUT_BUFFER_LEN;
	179	fpga_image_ptr = output_buffer;
	180	int res = inflate(compressed_fpga_stream, Z_SYNC_FLUSH);
	181	// if (res != Z_OK && res != Z_STREAM_END) {
	182	Dbprintf("inflate returned: %d, %s", res, compressed_fpga_stream->msg);
	183	// }
	184	}
	185
	186	Dbprintf("get_from_fpga_stream() returns %02x", *fpga_image_ptr);
	187	return *fpga_image_ptr++;
e6153040	188	}
	189
	190
add4d470	191	static voidpf fpga_inflate_malloc(voidpf opaque, uInt items, uInt size)
e6153040	192	{
add4d470	193	Dbprintf("zlib requested %d bytes", items*size);
	194	return BigBuf_malloc(items*size);
	195	}
	196
	197
	198	static void fpga_inflate_free(voidpf opaque, voidpf address)
	199	{
	200	Dbprintf("zlib wants to free memory");
	201	BigBuf_free_keep_EM();
	202	}
	203
	204
	205	void init_fpga_inflate(z_streamp compressed_fpga_stream, uint8_t fpga_image_start, uint32_t fpga_image_size, uint8_t output_buffer)
	206	{
	207	// initialize z_stream structure for inflate:
	208	compressed_fpga_stream->next_in = fpga_image_start;
	209	compressed_fpga_stream->avail_in = fpga_image_size;
	210	compressed_fpga_stream->next_out = output_buffer;
	211	compressed_fpga_stream->avail_out = OUTPUT_BUFFER_LEN;
	212	compressed_fpga_stream->zalloc = &fpga_inflate_malloc;
	213	compressed_fpga_stream->zfree = &fpga_inflate_free;
	214
	215	// initialize inflate to automatically detect header:
	216	int res = inflateInit2(compressed_fpga_stream, 15+32);
	217
	218	fpga_image_ptr = output_buffer;
	219
	220	Dbprintf("InflateInit returned %d", res);
	221	Dbprintf("fpga_image_ptr pointing at %02x %02x %02x %02x", fpga_image_ptr[0], fpga_image_ptr[1], fpga_image_ptr[2], fpga_image_ptr[3]);
	222	Dbprintf("zstream->next_in pointing at %02x %02x %02x %02x", compressed_fpga_stream->next_in[0], compressed_fpga_stream->next_in[1], compressed_fpga_stream->next_in[2], compressed_fpga_stream->next_in[3]);
	223	}
	224
	225
	226	bool reset_fpga_stream(int bitstream_version, z_streamp compressed_fpga_stream, uint8_t *output_buffer)
	227	{
	228	uint8_t header[FPGA_BITSTREAM_FIXED_HEADER_SIZE];
	229	uint8_t *fpga_image_start;
	230	uint32_t fpga_image_size;
	231
	232	if (bitstream_version == FPGA_BITSTREAM_LF) {
	233	fpga_image_start = &_binary_fpga_lf_bit_start;
	234	fpga_image_size = (uint32_t)&_binary_fpga_lf_bit_end - (uint32_t)&_binary_fpga_lf_bit_start;
	235	} else if (bitstream_version == FPGA_BITSTREAM_HF) {
	236	fpga_image_start = &_binary_fpga_hf_bit_start;
	237	fpga_image_size = (uint32_t)&_binary_fpga_hf_bit_end - (uint32_t)&_binary_fpga_hf_bit_start;
	238	} else {
	239	return false;
	240	}
	241
	242	init_fpga_inflate(compressed_fpga_stream, fpga_image_start, fpga_image_size, output_buffer);
	243
	244	for (uint16_t i = 0; i < FPGA_BITSTREAM_FIXED_HEADER_SIZE; i++) {
	245	header[i] = get_from_fpga_stream(compressed_fpga_stream, output_buffer);
	246	}
	247
	248	// Check for a valid .bit file (starts with _bitparse_fixed_header)
	249	if(memcmp(_bitparse_fixed_header, header, FPGA_BITSTREAM_FIXED_HEADER_SIZE) == 0) {
	250	return true;
	251	} else {
	252	return false;
	253	}
e6153040	254	}
	255
	256
15c4dc5a	257	static void DownloadFPGA_byte(unsigned char w)
	258	{
	259	#define SEND_BIT(x) { if(w & (1<<x) ) HIGH(GPIO_FPGA_DIN); else LOW(GPIO_FPGA_DIN); HIGH(GPIO_FPGA_CCLK); LOW(GPIO_FPGA_CCLK); }
	260	SEND_BIT(7);
	261	SEND_BIT(6);
	262	SEND_BIT(5);
	263	SEND_BIT(4);
	264	SEND_BIT(3);
	265	SEND_BIT(2);
	266	SEND_BIT(1);
	267	SEND_BIT(0);
	268	}
	269
e6153040	270	// Download the fpga image starting at current stream position with length FpgaImageLen bytes
add4d470	271	static void DownloadFPGA(int FpgaImageLen, z_streamp compressed_fpga_stream, uint8_t *output_buffer)
15c4dc5a	272	{
add4d470	273	Dbprintf("Would have loaded FPGA");
	274	return;
	275
15c4dc5a	276	int i=0;
	277
	278	AT91C_BASE_PIOA->PIO_OER = GPIO_FPGA_ON;
	279	AT91C_BASE_PIOA->PIO_PER = GPIO_FPGA_ON;
	280	HIGH(GPIO_FPGA_ON); // ensure everything is powered on
	281
	282	SpinDelay(50);
	283
	284	LED_D_ON();
	285
	286	// These pins are inputs
	287	AT91C_BASE_PIOA->PIO_ODR =
	288	GPIO_FPGA_NINIT \|
	289	GPIO_FPGA_DONE;
	290	// PIO controls the following pins
	291	AT91C_BASE_PIOA->PIO_PER =
	292	GPIO_FPGA_NINIT \|
	293	GPIO_FPGA_DONE;
	294	// Enable pull-ups
	295	AT91C_BASE_PIOA->PIO_PPUER =
	296	GPIO_FPGA_NINIT \|
	297	GPIO_FPGA_DONE;
	298
	299	// setup initial logic state
	300	HIGH(GPIO_FPGA_NPROGRAM);
	301	LOW(GPIO_FPGA_CCLK);
	302	LOW(GPIO_FPGA_DIN);
	303	// These pins are outputs
	304	AT91C_BASE_PIOA->PIO_OER =
	305	GPIO_FPGA_NPROGRAM \|
	306	GPIO_FPGA_CCLK \|
	307	GPIO_FPGA_DIN;
	308
	309	// enter FPGA configuration mode
	310	LOW(GPIO_FPGA_NPROGRAM);
	311	SpinDelay(50);
	312	HIGH(GPIO_FPGA_NPROGRAM);
	313
	314	i=100000;
	315	// wait for FPGA ready to accept data signal
	316	while ((i) && ( !(AT91C_BASE_PIOA->PIO_PDSR & GPIO_FPGA_NINIT ) ) ) {
	317	i--;
	318	}
	319
	320	// crude error indicator, leave both red LEDs on and return
	321	if (i==0){
	322	LED_C_ON();
	323	LED_D_ON();
	324	return;
	325	}
	326
e6153040	327	while(FpgaImageLen-->0) {
add4d470	328	DownloadFPGA_byte(get_from_fpga_stream(compressed_fpga_stream, output_buffer));
15c4dc5a	329	}
	330
	331	// continue to clock FPGA until ready signal goes high
	332	i=100000;
	333	while ( (i--) && ( !(AT91C_BASE_PIOA->PIO_PDSR & GPIO_FPGA_DONE ) ) ) {
	334	HIGH(GPIO_FPGA_CCLK);
	335	LOW(GPIO_FPGA_CCLK);
	336	}
	337	// crude error indicator, leave both red LEDs on and return
	338	if (i==0){
	339	LED_C_ON();
	340	LED_D_ON();
	341	return;
	342	}
	343	LED_D_OFF();
	344	}
	345
e6153040	346
15c4dc5a	347	/* Simple Xilinx .bit parser. The file starts with the fixed opaque byte sequence
	348	* 00 09 0f f0 0f f0 0f f0 0f f0 00 00 01
	349	* After that the format is 1 byte section type (ASCII character), 2 byte length
	350	* (big endian), <length> bytes content. Except for section 'e' which has 4 bytes
	351	* length.
	352	*/
add4d470	353	int bitparse_find_section(char section_name, unsigned int section_length, z_streamp compressed_fpga_stream, uint8_t output_buffer)
15c4dc5a	354	{
15c4dc5a	355	int result = 0;
e6153040	356	#define MAX_FPGA_BIT_STREAM_HEADER_SEARCH 100 // maximum number of bytes to search for the requested section
	357	uint16_t numbytes = 0;
	358	while(numbytes < MAX_FPGA_BIT_STREAM_HEADER_SEARCH) {
add4d470	359	char current_name = get_from_fpga_stream(compressed_fpga_stream, output_buffer);
e6153040	360	numbytes++;
15c4dc5a	361	unsigned int current_length = 0;
	362	if(current_name < 'a' \|\| current_name > 'e') {
	363	/* Strange section name, abort */
	364	break;
	365	}
	366	current_length = 0;
	367	switch(current_name) {
	368	case 'e':
	369	/* Four byte length field */
add4d470	370	current_length += get_from_fpga_stream(compressed_fpga_stream, output_buffer) << 24;
add4d470	371	current_length += get_from_fpga_stream(compressed_fpga_stream, output_buffer) << 16;
e6153040	372	numbytes += 2;
15c4dc5a	373	default: /* Fall through, two byte length field */
add4d470	374	current_length += get_from_fpga_stream(compressed_fpga_stream, output_buffer) << 8;
add4d470	375	current_length += get_from_fpga_stream(compressed_fpga_stream, output_buffer) << 0;
e6153040	376	numbytes += 2;
15c4dc5a	377	}
e30c654b	378
15c4dc5a	379	if(current_name != 'e' && current_length > 255) {
	380	/* Maybe a parse error */
	381	break;
	382	}
e30c654b	383
15c4dc5a	384	if(current_name == section_name) {
15c4dc5a	385	/* Found it */
15c4dc5a	386	*section_length = current_length;
	387	result = 1;
	388	break;
	389	}
e30c654b	390
e6153040	391	for (uint16_t i = 0; i < current_length && numbytes < MAX_FPGA_BIT_STREAM_HEADER_SEARCH; i++) {
add4d470	392	get_from_fpga_stream(compressed_fpga_stream, output_buffer);
e6153040	393	numbytes++;
e6153040	394	}
15c4dc5a	395	}
e30c654b	396
15c4dc5a	397	return result;
	398	}
	399
e6153040	400
15c4dc5a	401	//-----------------------------------------------------------------------------
	402	// Find out which FPGA image format is stored in flash, then call DownloadFPGA
	403	// with the right parameters to download the image
	404	//-----------------------------------------------------------------------------
7cc204bf	405	void FpgaDownloadAndGo(int bitstream_version)
15c4dc5a	406	{
add4d470	407	z_stream compressed_fpga_stream;
add4d470	408	uint8_t output_buffer[OUTPUT_BUFFER_LEN];
e6153040	409
7cc204bf	410	// check whether or not the bitstream is already loaded
e6153040	411	if (downloaded_bitstream == bitstream_version)
7cc204bf	412	return;
7cc204bf	413
add4d470	414	if (!reset_fpga_stream(bitstream_version, &compressed_fpga_stream, output_buffer)) {
7cc204bf	415	return;
e6153040	416	}
e6153040	417
add4d470	418	unsigned int bitstream_length;
	419	if(bitparse_find_section('e', &bitstream_length, &compressed_fpga_stream, output_buffer)) {
	420	DownloadFPGA(bitstream_length, &compressed_fpga_stream, output_buffer);
	421	downloaded_bitstream = bitstream_version;
	422	return; /* All done */
15c4dc5a	423	}
e6153040	424	}
15c4dc5a	425
7cc204bf	426
e6153040	427	void FpgaGatherVersion(int bitstream_version, char *dst, int len)
15c4dc5a	428	{
15c4dc5a	429	unsigned int fpga_info_len;
e6153040	430	char tempstr[40];
add4d470	431	z_stream compressed_fpga_stream;
add4d470	432	uint8_t output_buffer[OUTPUT_BUFFER_LEN];
e6153040	433
	434	dst[0] = '\0';
	435
add4d470	436	if (!reset_fpga_stream(bitstream_version, &compressed_fpga_stream, output_buffer)) {
e6153040	437	return;
e6153040	438	}
e6153040	439
add4d470	440	if(bitparse_find_section('a', &fpga_info_len, &compressed_fpga_stream, output_buffer)) {
e6153040	441	for (uint16_t i = 0; i < fpga_info_len; i++) {
add4d470	442	char c = (char)get_from_fpga_stream(&compressed_fpga_stream, output_buffer);
e6153040	443	if (i < sizeof(tempstr)) {
	444	tempstr[i] = c;
	445	}
15c4dc5a	446	}
e6153040	447	if (!memcmp("fpga_lf", tempstr, 7))
	448	strncat(dst, "LF ", len-1);
	449	else if (!memcmp("fpga_hf", tempstr, 7))
	450	strncat(dst, "HF ", len-1);
	451	}
	452	strncat(dst, "FPGA image built", len-1);
add4d470	453	if(bitparse_find_section('b', &fpga_info_len, &compressed_fpga_stream, output_buffer)) {
e6153040	454	strncat(dst, " for ", len-1);
e6153040	455	for (uint16_t i = 0; i < fpga_info_len; i++) {
add4d470	456	char c = (char)get_from_fpga_stream(&compressed_fpga_stream, output_buffer);
e6153040	457	if (i < sizeof(tempstr)) {
	458	tempstr[i] = c;
	459	}
15c4dc5a	460	}
e6153040	461	strncat(dst, tempstr, len-1);
e6153040	462	}
add4d470	463	if(bitparse_find_section('c', &fpga_info_len, &compressed_fpga_stream, output_buffer)) {
e6153040	464	strncat(dst, " on ", len-1);
e6153040	465	for (uint16_t i = 0; i < fpga_info_len; i++) {
add4d470	466	char c = (char)get_from_fpga_stream(&compressed_fpga_stream, output_buffer);
e6153040	467	if (i < sizeof(tempstr)) {
	468	tempstr[i] = c;
	469	}
15c4dc5a	470	}
e6153040	471	strncat(dst, tempstr, len-1);
e6153040	472	}
add4d470	473	if(bitparse_find_section('d', &fpga_info_len, &compressed_fpga_stream, output_buffer)) {
e6153040	474	strncat(dst, " at ", len-1);
e6153040	475	for (uint16_t i = 0; i < fpga_info_len; i++) {
add4d470	476	char c = (char)get_from_fpga_stream(&compressed_fpga_stream, output_buffer);
e6153040	477	if (i < sizeof(tempstr)) {
	478	tempstr[i] = c;
	479	}
15c4dc5a	480	}
e6153040	481	strncat(dst, tempstr, len-1);
15c4dc5a	482	}
	483	}
	484
add4d470	485
15c4dc5a	486	//-----------------------------------------------------------------------------
	487	// Send a 16 bit command/data pair to the FPGA.
	488	// The bit format is: C3 C2 C1 C0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
	489	// where C is the 4 bit command and D is the 12 bit data
	490	//-----------------------------------------------------------------------------
f7e3ed82	491	void FpgaSendCommand(uint16_t cmd, uint16_t v)
15c4dc5a	492	{
	493	SetupSpi(SPI_FPGA_MODE);
	494	while ((AT91C_BASE_SPI->SPI_SR & AT91C_SPI_TXEMPTY) == 0); // wait for the transfer to complete
	495	AT91C_BASE_SPI->SPI_TDR = AT91C_SPI_LASTXFER \| cmd \| v; // send the data
	496	}
	497	//-----------------------------------------------------------------------------
	498	// Write the FPGA setup word (that determines what mode the logic is in, read
	499	// vs. clone vs. etc.). This is now a special case of FpgaSendCommand() to
	500	// avoid changing this function's occurence everywhere in the source code.
	501	//-----------------------------------------------------------------------------
f7e3ed82	502	void FpgaWriteConfWord(uint8_t v)
15c4dc5a	503	{
	504	FpgaSendCommand(FPGA_CMD_SET_CONFREG, v);
	505	}
	506
	507	//-----------------------------------------------------------------------------
	508	// Set up the CMOS switches that mux the ADC: four switches, independently
	509	// closable, but should only close one at a time. Not an FPGA thing, but
	510	// the samples from the ADC always flow through the FPGA.
	511	//-----------------------------------------------------------------------------
f7e3ed82	512	void SetAdcMuxFor(uint32_t whichGpio)
15c4dc5a	513	{
	514	AT91C_BASE_PIOA->PIO_OER =
	515	GPIO_MUXSEL_HIPKD \|
	516	GPIO_MUXSEL_LOPKD \|
	517	GPIO_MUXSEL_LORAW \|
	518	GPIO_MUXSEL_HIRAW;
	519
	520	AT91C_BASE_PIOA->PIO_PER =
	521	GPIO_MUXSEL_HIPKD \|
	522	GPIO_MUXSEL_LOPKD \|
	523	GPIO_MUXSEL_LORAW \|
	524	GPIO_MUXSEL_HIRAW;
	525
	526	LOW(GPIO_MUXSEL_HIPKD);
	527	LOW(GPIO_MUXSEL_HIRAW);
	528	LOW(GPIO_MUXSEL_LORAW);
	529	LOW(GPIO_MUXSEL_LOPKD);
	530
	531	HIGH(whichGpio);
	532	}