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[proxmark3-svn] / armsrc / lfops.c
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e09f21fa 1//-----------------------------------------------------------------------------
2// This code is licensed to you under the terms of the GNU GPL, version 2 or,
3// at your option, any later version. See the LICENSE.txt file for the text of
4// the license.
5//-----------------------------------------------------------------------------
6// Miscellaneous routines for low frequency tag operations.
7// Tags supported here so far are Texas Instruments (TI), HID
8// Also routines for raw mode reading/simulating of LF waveform
9//-----------------------------------------------------------------------------
10
11#include "proxmark3.h"
12#include "apps.h"
13#include "util.h"
14#include "hitag2.h"
15#include "crc16.h"
16#include "string.h"
17#include "lfdemod.h"
18#include "lfsampling.h"
19
20
21/**
22 * Function to do a modulation and then get samples.
23 * @param delay_off
24 * @param period_0
25 * @param period_1
26 * @param command
27 */
28void ModThenAcquireRawAdcSamples125k(int delay_off, int period_0, int period_1, uint8_t *command)
29{
30
31 int divisor_used = 95; // 125 KHz
32 // see if 'h' was specified
33
34 if (command[strlen((char *) command) - 1] == 'h')
35 divisor_used = 88; // 134.8 KHz
36
37 sample_config sc = { 0,0,1, divisor_used, 0};
38 setSamplingConfig(&sc);
39
40 /* Make sure the tag is reset */
41 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
42 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
43 SpinDelay(2500);
44
45 LFSetupFPGAForADC(sc.divisor, 1);
46
47 // And a little more time for the tag to fully power up
48 SpinDelay(2000);
49
50 // now modulate the reader field
51 while(*command != '\0' && *command != ' ') {
52 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
53 LED_D_OFF();
54 SpinDelayUs(delay_off);
55 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc.divisor);
56
57 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
58 LED_D_ON();
59 if(*(command++) == '0')
60 SpinDelayUs(period_0);
61 else
62 SpinDelayUs(period_1);
63 }
64 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
65 LED_D_OFF();
66 SpinDelayUs(delay_off);
67 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc.divisor);
68
69 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
70
71 // now do the read
72 DoAcquisition_config(false);
73}
74
75
76
77/* blank r/w tag data stream
78...0000000000000000 01111111
791010101010101010101010101010101010101010101010101010101010101010
800011010010100001
8101111111
82101010101010101[0]000...
83
84[5555fe852c5555555555555555fe0000]
85*/
86void ReadTItag(void)
87{
88 // some hardcoded initial params
89 // when we read a TI tag we sample the zerocross line at 2Mhz
90 // TI tags modulate a 1 as 16 cycles of 123.2Khz
91 // TI tags modulate a 0 as 16 cycles of 134.2Khz
92 #define FSAMPLE 2000000
93 #define FREQLO 123200
94 #define FREQHI 134200
95
96 signed char *dest = (signed char *)BigBuf_get_addr();
97 uint16_t n = BigBuf_max_traceLen();
98 // 128 bit shift register [shift3:shift2:shift1:shift0]
99 uint32_t shift3 = 0, shift2 = 0, shift1 = 0, shift0 = 0;
100
101 int i, cycles=0, samples=0;
102 // how many sample points fit in 16 cycles of each frequency
103 uint32_t sampleslo = (FSAMPLE<<4)/FREQLO, sampleshi = (FSAMPLE<<4)/FREQHI;
104 // when to tell if we're close enough to one freq or another
105 uint32_t threshold = (sampleslo - sampleshi + 1)>>1;
106
107 // TI tags charge at 134.2Khz
108 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
109 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
110
111 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
112 // connects to SSP_DIN and the SSP_DOUT logic level controls
113 // whether we're modulating the antenna (high)
114 // or listening to the antenna (low)
115 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
116
117 // get TI tag data into the buffer
118 AcquireTiType();
119
120 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
121
122 for (i=0; i<n-1; i++) {
123 // count cycles by looking for lo to hi zero crossings
124 if ( (dest[i]<0) && (dest[i+1]>0) ) {
125 cycles++;
126 // after 16 cycles, measure the frequency
127 if (cycles>15) {
128 cycles=0;
129 samples=i-samples; // number of samples in these 16 cycles
130
131 // TI bits are coming to us lsb first so shift them
132 // right through our 128 bit right shift register
133 shift0 = (shift0>>1) | (shift1 << 31);
134 shift1 = (shift1>>1) | (shift2 << 31);
135 shift2 = (shift2>>1) | (shift3 << 31);
136 shift3 >>= 1;
137
138 // check if the cycles fall close to the number
139 // expected for either the low or high frequency
140 if ( (samples>(sampleslo-threshold)) && (samples<(sampleslo+threshold)) ) {
141 // low frequency represents a 1
142 shift3 |= (1<<31);
143 } else if ( (samples>(sampleshi-threshold)) && (samples<(sampleshi+threshold)) ) {
144 // high frequency represents a 0
145 } else {
146 // probably detected a gay waveform or noise
147 // use this as gaydar or discard shift register and start again
148 shift3 = shift2 = shift1 = shift0 = 0;
149 }
150 samples = i;
151
152 // for each bit we receive, test if we've detected a valid tag
153
154 // if we see 17 zeroes followed by 6 ones, we might have a tag
155 // remember the bits are backwards
156 if ( ((shift0 & 0x7fffff) == 0x7e0000) ) {
157 // if start and end bytes match, we have a tag so break out of the loop
158 if ( ((shift0>>16)&0xff) == ((shift3>>8)&0xff) ) {
159 cycles = 0xF0B; //use this as a flag (ugly but whatever)
160 break;
161 }
162 }
163 }
164 }
165 }
166
167 // if flag is set we have a tag
168 if (cycles!=0xF0B) {
169 DbpString("Info: No valid tag detected.");
170 } else {
171 // put 64 bit data into shift1 and shift0
172 shift0 = (shift0>>24) | (shift1 << 8);
173 shift1 = (shift1>>24) | (shift2 << 8);
174
175 // align 16 bit crc into lower half of shift2
176 shift2 = ((shift2>>24) | (shift3 << 8)) & 0x0ffff;
177
178 // if r/w tag, check ident match
179 if (shift3 & (1<<15) ) {
180 DbpString("Info: TI tag is rewriteable");
181 // only 15 bits compare, last bit of ident is not valid
182 if (((shift3 >> 16) ^ shift0) & 0x7fff ) {
183 DbpString("Error: Ident mismatch!");
184 } else {
185 DbpString("Info: TI tag ident is valid");
186 }
187 } else {
188 DbpString("Info: TI tag is readonly");
189 }
190
191 // WARNING the order of the bytes in which we calc crc below needs checking
192 // i'm 99% sure the crc algorithm is correct, but it may need to eat the
193 // bytes in reverse or something
194 // calculate CRC
195 uint32_t crc=0;
196
197 crc = update_crc16(crc, (shift0)&0xff);
198 crc = update_crc16(crc, (shift0>>8)&0xff);
199 crc = update_crc16(crc, (shift0>>16)&0xff);
200 crc = update_crc16(crc, (shift0>>24)&0xff);
201 crc = update_crc16(crc, (shift1)&0xff);
202 crc = update_crc16(crc, (shift1>>8)&0xff);
203 crc = update_crc16(crc, (shift1>>16)&0xff);
204 crc = update_crc16(crc, (shift1>>24)&0xff);
205
206 Dbprintf("Info: Tag data: %x%08x, crc=%x",
207 (unsigned int)shift1, (unsigned int)shift0, (unsigned int)shift2 & 0xFFFF);
208 if (crc != (shift2&0xffff)) {
209 Dbprintf("Error: CRC mismatch, expected %x", (unsigned int)crc);
210 } else {
211 DbpString("Info: CRC is good");
212 }
213 }
214}
215
216void WriteTIbyte(uint8_t b)
217{
218 int i = 0;
219
220 // modulate 8 bits out to the antenna
221 for (i=0; i<8; i++)
222 {
223 if (b&(1<<i)) {
224 // stop modulating antenna
225 LOW(GPIO_SSC_DOUT);
226 SpinDelayUs(1000);
227 // modulate antenna
228 HIGH(GPIO_SSC_DOUT);
229 SpinDelayUs(1000);
230 } else {
231 // stop modulating antenna
232 LOW(GPIO_SSC_DOUT);
233 SpinDelayUs(300);
234 // modulate antenna
235 HIGH(GPIO_SSC_DOUT);
236 SpinDelayUs(1700);
237 }
238 }
239}
240
241void AcquireTiType(void)
242{
243 int i, j, n;
244 // tag transmission is <20ms, sampling at 2M gives us 40K samples max
245 // each sample is 1 bit stuffed into a uint32_t so we need 1250 uint32_t
246 #define TIBUFLEN 1250
247
248 // clear buffer
249 uint32_t *BigBuf = (uint32_t *)BigBuf_get_addr();
250 memset(BigBuf,0,BigBuf_max_traceLen()/sizeof(uint32_t));
251
252 // Set up the synchronous serial port
253 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DIN;
254 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN;
255
256 // steal this pin from the SSP and use it to control the modulation
257 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
258 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
259
260 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST;
261 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_RXEN | AT91C_SSC_TXEN;
262
263 // Sample at 2 Mbit/s, so TI tags are 16.2 vs. 14.9 clocks long
264 // 48/2 = 24 MHz clock must be divided by 12
265 AT91C_BASE_SSC->SSC_CMR = 12;
266
267 AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(0);
268 AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(32) | AT91C_SSC_MSBF;
269 AT91C_BASE_SSC->SSC_TCMR = 0;
270 AT91C_BASE_SSC->SSC_TFMR = 0;
271
272 LED_D_ON();
273
274 // modulate antenna
275 HIGH(GPIO_SSC_DOUT);
276
277 // Charge TI tag for 50ms.
278 SpinDelay(50);
279
280 // stop modulating antenna and listen
281 LOW(GPIO_SSC_DOUT);
282
283 LED_D_OFF();
284
285 i = 0;
286 for(;;) {
287 if(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
288 BigBuf[i] = AT91C_BASE_SSC->SSC_RHR; // store 32 bit values in buffer
289 i++; if(i >= TIBUFLEN) break;
290 }
291 WDT_HIT();
292 }
293
294 // return stolen pin to SSP
295 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT;
296 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN | GPIO_SSC_DOUT;
297
298 char *dest = (char *)BigBuf_get_addr();
299 n = TIBUFLEN*32;
300 // unpack buffer
301 for (i=TIBUFLEN-1; i>=0; i--) {
302 for (j=0; j<32; j++) {
303 if(BigBuf[i] & (1 << j)) {
304 dest[--n] = 1;
305 } else {
306 dest[--n] = -1;
307 }
308 }
309 }
310}
311
312// arguments: 64bit data split into 32bit idhi:idlo and optional 16bit crc
313// if crc provided, it will be written with the data verbatim (even if bogus)
314// if not provided a valid crc will be computed from the data and written.
315void WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc)
316{
317 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
318 if(crc == 0) {
319 crc = update_crc16(crc, (idlo)&0xff);
320 crc = update_crc16(crc, (idlo>>8)&0xff);
321 crc = update_crc16(crc, (idlo>>16)&0xff);
322 crc = update_crc16(crc, (idlo>>24)&0xff);
323 crc = update_crc16(crc, (idhi)&0xff);
324 crc = update_crc16(crc, (idhi>>8)&0xff);
325 crc = update_crc16(crc, (idhi>>16)&0xff);
326 crc = update_crc16(crc, (idhi>>24)&0xff);
327 }
328 Dbprintf("Writing to tag: %x%08x, crc=%x",
329 (unsigned int) idhi, (unsigned int) idlo, crc);
330
331 // TI tags charge at 134.2Khz
332 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
333 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
334 // connects to SSP_DIN and the SSP_DOUT logic level controls
335 // whether we're modulating the antenna (high)
336 // or listening to the antenna (low)
337 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
338 LED_A_ON();
339
340 // steal this pin from the SSP and use it to control the modulation
341 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
342 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
343
344 // writing algorithm:
345 // a high bit consists of a field off for 1ms and field on for 1ms
346 // a low bit consists of a field off for 0.3ms and field on for 1.7ms
347 // initiate a charge time of 50ms (field on) then immediately start writing bits
348 // start by writing 0xBB (keyword) and 0xEB (password)
349 // then write 80 bits of data (or 64 bit data + 16 bit crc if you prefer)
350 // finally end with 0x0300 (write frame)
351 // all data is sent lsb firts
352 // finish with 15ms programming time
353
354 // modulate antenna
355 HIGH(GPIO_SSC_DOUT);
356 SpinDelay(50); // charge time
357
358 WriteTIbyte(0xbb); // keyword
359 WriteTIbyte(0xeb); // password
360 WriteTIbyte( (idlo )&0xff );
361 WriteTIbyte( (idlo>>8 )&0xff );
362 WriteTIbyte( (idlo>>16)&0xff );
363 WriteTIbyte( (idlo>>24)&0xff );
364 WriteTIbyte( (idhi )&0xff );
365 WriteTIbyte( (idhi>>8 )&0xff );
366 WriteTIbyte( (idhi>>16)&0xff );
367 WriteTIbyte( (idhi>>24)&0xff ); // data hi to lo
368 WriteTIbyte( (crc )&0xff ); // crc lo
369 WriteTIbyte( (crc>>8 )&0xff ); // crc hi
370 WriteTIbyte(0x00); // write frame lo
371 WriteTIbyte(0x03); // write frame hi
372 HIGH(GPIO_SSC_DOUT);
373 SpinDelay(50); // programming time
374
375 LED_A_OFF();
376
377 // get TI tag data into the buffer
378 AcquireTiType();
379
380 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
381 DbpString("Now use tiread to check");
382}
383
384void SimulateTagLowFrequency(int period, int gap, int ledcontrol)
385{
386 int i;
387 uint8_t *tab = BigBuf_get_addr();
388
389 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
390 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT);
391
392 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK;
393
394 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
395 AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK;
396
397 #define SHORT_COIL() LOW(GPIO_SSC_DOUT)
398 #define OPEN_COIL() HIGH(GPIO_SSC_DOUT)
399
400 i = 0;
401 for(;;) {
402 //wait until SSC_CLK goes HIGH
403 while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) {
404 if(BUTTON_PRESS()) {
405 DbpString("Stopped");
406 return;
407 }
408 WDT_HIT();
409 }
410 if (ledcontrol)
411 LED_D_ON();
412
413 if(tab[i])
414 OPEN_COIL();
415 else
416 SHORT_COIL();
417
418 if (ledcontrol)
419 LED_D_OFF();
420 //wait until SSC_CLK goes LOW
421 while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) {
422 if(BUTTON_PRESS()) {
423 DbpString("Stopped");
424 return;
425 }
426 WDT_HIT();
427 }
428
429 i++;
430 if(i == period) {
431
432 i = 0;
433 if (gap) {
434 SHORT_COIL();
435 SpinDelayUs(gap);
436 }
437 }
438 }
439}
440
e09f21fa 441#define DEBUG_FRAME_CONTENTS 1
442void SimulateTagLowFrequencyBidir(int divisor, int t0)
443{
444}
445
446// compose fc/8 fc/10 waveform (FSK2)
447static void fc(int c, int *n)
448{
449 uint8_t *dest = BigBuf_get_addr();
450 int idx;
451
452 // for when we want an fc8 pattern every 4 logical bits
453 if(c==0) {
454 dest[((*n)++)]=1;
455 dest[((*n)++)]=1;
456 dest[((*n)++)]=1;
457 dest[((*n)++)]=1;
458 dest[((*n)++)]=0;
459 dest[((*n)++)]=0;
460 dest[((*n)++)]=0;
461 dest[((*n)++)]=0;
462 }
463
712ebfa6 464 // an fc/8 encoded bit is a bit pattern of 11110000 x6 = 48 samples
e09f21fa 465 if(c==8) {
466 for (idx=0; idx<6; idx++) {
467 dest[((*n)++)]=1;
468 dest[((*n)++)]=1;
469 dest[((*n)++)]=1;
470 dest[((*n)++)]=1;
471 dest[((*n)++)]=0;
472 dest[((*n)++)]=0;
473 dest[((*n)++)]=0;
474 dest[((*n)++)]=0;
475 }
476 }
477
712ebfa6 478 // an fc/10 encoded bit is a bit pattern of 1111100000 x5 = 50 samples
e09f21fa 479 if(c==10) {
480 for (idx=0; idx<5; idx++) {
481 dest[((*n)++)]=1;
482 dest[((*n)++)]=1;
483 dest[((*n)++)]=1;
484 dest[((*n)++)]=1;
485 dest[((*n)++)]=1;
486 dest[((*n)++)]=0;
487 dest[((*n)++)]=0;
488 dest[((*n)++)]=0;
489 dest[((*n)++)]=0;
490 dest[((*n)++)]=0;
491 }
492 }
493}
494// compose fc/X fc/Y waveform (FSKx)
712ebfa6 495static void fcAll(uint8_t fc, int *n, uint8_t clock, uint16_t *modCnt)
e09f21fa 496{
497 uint8_t *dest = BigBuf_get_addr();
712ebfa6 498 uint8_t halfFC = fc/2;
499 uint8_t wavesPerClock = clock/fc;
500 uint8_t mod = clock % fc; //modifier
501 uint8_t modAdj = fc/mod; //how often to apply modifier
502 bool modAdjOk = !(fc % mod); //if (fc % mod==0) modAdjOk=TRUE;
e09f21fa 503 // loop through clock - step field clock
712ebfa6 504 for (uint8_t idx=0; idx < wavesPerClock; idx++){
505 // put 1/2 FC length 1's and 1/2 0's per field clock wave (to create the wave)
506 memset(dest+(*n), 0, fc-halfFC); //in case of odd number use extra here
507 memset(dest+(*n)+(fc-halfFC), 1, halfFC);
508 *n += fc;
e09f21fa 509 }
510 if (mod>0) (*modCnt)++;
511 if ((mod>0) && modAdjOk){ //fsk2
512 if ((*modCnt % modAdj) == 0){ //if 4th 8 length wave in a rf/50 add extra 8 length wave
712ebfa6 513 memset(dest+(*n), 0, fc-halfFC);
514 memset(dest+(*n)+(fc-halfFC), 1, halfFC);
515 *n += fc;
e09f21fa 516 }
517 }
e09f21fa 518 if (mod>0 && !modAdjOk){ //fsk1
712ebfa6 519 memset(dest+(*n), 0, mod-(mod/2));
520 memset(dest+(*n)+(mod-(mod/2)), 1, mod/2);
521 *n += mod;
e09f21fa 522 }
523}
524
525// prepare a waveform pattern in the buffer based on the ID given then
526// simulate a HID tag until the button is pressed
527void CmdHIDsimTAG(int hi, int lo, int ledcontrol)
528{
529 int n=0, i=0;
530 /*
531 HID tag bitstream format
532 The tag contains a 44bit unique code. This is sent out MSB first in sets of 4 bits
533 A 1 bit is represented as 6 fc8 and 5 fc10 patterns
534 A 0 bit is represented as 5 fc10 and 6 fc8 patterns
535 A fc8 is inserted before every 4 bits
536 A special start of frame pattern is used consisting a0b0 where a and b are neither 0
537 nor 1 bits, they are special patterns (a = set of 12 fc8 and b = set of 10 fc10)
538 */
539
540 if (hi>0xFFF) {
78f5b1a7 541 DbpString("Tags can only have 44 bits. - USE lf simfsk for larger tags");
e09f21fa 542 return;
543 }
544 fc(0,&n);
545 // special start of frame marker containing invalid bit sequences
546 fc(8, &n); fc(8, &n); // invalid
547 fc(8, &n); fc(10, &n); // logical 0
548 fc(10, &n); fc(10, &n); // invalid
549 fc(8, &n); fc(10, &n); // logical 0
550
551 WDT_HIT();
552 // manchester encode bits 43 to 32
553 for (i=11; i>=0; i--) {
554 if ((i%4)==3) fc(0,&n);
555 if ((hi>>i)&1) {
556 fc(10, &n); fc(8, &n); // low-high transition
557 } else {
558 fc(8, &n); fc(10, &n); // high-low transition
559 }
560 }
561
562 WDT_HIT();
563 // manchester encode bits 31 to 0
564 for (i=31; i>=0; i--) {
565 if ((i%4)==3) fc(0,&n);
566 if ((lo>>i)&1) {
567 fc(10, &n); fc(8, &n); // low-high transition
568 } else {
569 fc(8, &n); fc(10, &n); // high-low transition
570 }
571 }
572
573 if (ledcontrol)
574 LED_A_ON();
575 SimulateTagLowFrequency(n, 0, ledcontrol);
576
577 if (ledcontrol)
578 LED_A_OFF();
579}
580
581// prepare a waveform pattern in the buffer based on the ID given then
582// simulate a FSK tag until the button is pressed
583// arg1 contains fcHigh and fcLow, arg2 contains invert and clock
584void CmdFSKsimTAG(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
585{
586 int ledcontrol=1;
587 int n=0, i=0;
588 uint8_t fcHigh = arg1 >> 8;
589 uint8_t fcLow = arg1 & 0xFF;
590 uint16_t modCnt = 0;
e09f21fa 591 uint8_t clk = arg2 & 0xFF;
592 uint8_t invert = (arg2 >> 8) & 1;
712ebfa6 593
e09f21fa 594 for (i=0; i<size; i++){
595 if (BitStream[i] == invert){
596 fcAll(fcLow, &n, clk, &modCnt);
597 } else {
598 fcAll(fcHigh, &n, clk, &modCnt);
599 }
600 }
601 Dbprintf("Simulating with fcHigh: %d, fcLow: %d, clk: %d, invert: %d, n: %d",fcHigh, fcLow, clk, invert, n);
712ebfa6 602 /*Dbprintf("DEBUG: First 32:");
e09f21fa 603 uint8_t *dest = BigBuf_get_addr();
604 i=0;
605 Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
606 i+=16;
607 Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
78f5b1a7 608 */
e09f21fa 609 if (ledcontrol)
610 LED_A_ON();
712ebfa6 611
78f5b1a7 612 SimulateTagLowFrequency(n, 0, ledcontrol);
e09f21fa 613
614 if (ledcontrol)
615 LED_A_OFF();
616}
617
618// compose ask waveform for one bit(ASK)
619static void askSimBit(uint8_t c, int *n, uint8_t clock, uint8_t manchester)
620{
621 uint8_t *dest = BigBuf_get_addr();
712ebfa6 622 uint8_t halfClk = clock/2;
e09f21fa 623 // c = current bit 1 or 0
712ebfa6 624 if (manchester){
625 memset(dest+(*n), c, halfClk);
626 memset(dest+(*n) + halfClk, c^1, halfClk);
e09f21fa 627 } else {
712ebfa6 628 memset(dest+(*n), c, clock);
e09f21fa 629 }
712ebfa6 630 *n += clock;
e09f21fa 631}
632
633// args clock, ask/man or askraw, invert, transmission separator
634void CmdASKsimTag(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
635{
636 int ledcontrol = 1;
637 int n=0, i=0;
638 uint8_t clk = (arg1 >> 8) & 0xFF;
639 uint8_t manchester = arg1 & 1;
640 uint8_t separator = arg2 & 1;
641 uint8_t invert = (arg2 >> 8) & 1;
e09f21fa 642 for (i=0; i<size; i++){
643 askSimBit(BitStream[i]^invert, &n, clk, manchester);
644 }
712ebfa6 645 if (separator==1) Dbprintf("sorry but separator option not yet available");
e09f21fa 646
647 Dbprintf("Simulating with clk: %d, invert: %d, manchester: %d, separator: %d, n: %d",clk, invert, manchester, separator, n);
648 //DEBUG
712ebfa6 649 //Dbprintf("First 32:");
e09f21fa 650 //uint8_t *dest = BigBuf_get_addr();
651 //i=0;
652 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
653 //i+=16;
654 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
e09f21fa 655
656 if (ledcontrol)
657 LED_A_ON();
712ebfa6 658
78f5b1a7 659 SimulateTagLowFrequency(n, 0, ledcontrol);
e09f21fa 660
661 if (ledcontrol)
662 LED_A_OFF();
663}
664
665//carrier can be 2,4 or 8
666static void pskSimBit(uint8_t waveLen, int *n, uint8_t clk, uint8_t *curPhase, bool phaseChg)
667{
668 uint8_t *dest = BigBuf_get_addr();
712ebfa6 669 uint8_t halfWave = waveLen/2;
670 //uint8_t idx;
e09f21fa 671 int i = 0;
672 if (phaseChg){
673 // write phase change
712ebfa6 674 memset(dest+(*n), *curPhase^1, halfWave);
675 memset(dest+(*n) + halfWave, *curPhase, halfWave);
676 *n += waveLen;
e09f21fa 677 *curPhase ^= 1;
712ebfa6 678 i += waveLen;
e09f21fa 679 }
680 //write each normal clock wave for the clock duration
681 for (; i < clk; i+=waveLen){
712ebfa6 682 memset(dest+(*n), *curPhase, halfWave);
683 memset(dest+(*n) + halfWave, *curPhase^1, halfWave);
684 *n += waveLen;
e09f21fa 685 }
686}
687
688// args clock, carrier, invert,
689void CmdPSKsimTag(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
690{
691 int ledcontrol=1;
692 int n=0, i=0;
693 uint8_t clk = arg1 >> 8;
694 uint8_t carrier = arg1 & 0xFF;
695 uint8_t invert = arg2 & 0xFF;
78f5b1a7 696 uint8_t curPhase = 0;
e09f21fa 697 for (i=0; i<size; i++){
698 if (BitStream[i] == curPhase){
699 pskSimBit(carrier, &n, clk, &curPhase, FALSE);
700 } else {
701 pskSimBit(carrier, &n, clk, &curPhase, TRUE);
702 }
703 }
704 Dbprintf("Simulating with Carrier: %d, clk: %d, invert: %d, n: %d",carrier, clk, invert, n);
712ebfa6 705 //Dbprintf("DEBUG: First 32:");
706 //uint8_t *dest = BigBuf_get_addr();
707 //i=0;
708 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
709 //i+=16;
710 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
e09f21fa 711
712 if (ledcontrol)
713 LED_A_ON();
78f5b1a7 714 SimulateTagLowFrequency(n, 0, ledcontrol);
e09f21fa 715
716 if (ledcontrol)
717 LED_A_OFF();
718}
719
720// loop to get raw HID waveform then FSK demodulate the TAG ID from it
721void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
722{
723 uint8_t *dest = BigBuf_get_addr();
724 const size_t sizeOfBigBuff = BigBuf_max_traceLen();
725 size_t size = 0;
726 uint32_t hi2=0, hi=0, lo=0;
727 int idx=0;
728 // Configure to go in 125Khz listen mode
729 LFSetupFPGAForADC(95, true);
730
731 while(!BUTTON_PRESS()) {
732
733 WDT_HIT();
734 if (ledcontrol) LED_A_ON();
735
736 DoAcquisition_default(-1,true);
737 // FSK demodulator
738 size = sizeOfBigBuff; //variable size will change after demod so re initialize it before use
739 idx = HIDdemodFSK(dest, &size, &hi2, &hi, &lo);
740
741 if (idx>0 && lo>0){
742 // final loop, go over previously decoded manchester data and decode into usable tag ID
743 // 111000 bit pattern represent start of frame, 01 pattern represents a 1 and 10 represents a 0
744 if (hi2 != 0){ //extra large HID tags
745 Dbprintf("TAG ID: %x%08x%08x (%d)",
746 (unsigned int) hi2, (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
747 }else { //standard HID tags <38 bits
748 //Dbprintf("TAG ID: %x%08x (%d)",(unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF); //old print cmd
749 uint8_t bitlen = 0;
750 uint32_t fc = 0;
751 uint32_t cardnum = 0;
752 if (((hi>>5)&1) == 1){//if bit 38 is set then < 37 bit format is used
753 uint32_t lo2=0;
754 lo2=(((hi & 31) << 12) | (lo>>20)); //get bits 21-37 to check for format len bit
755 uint8_t idx3 = 1;
756 while(lo2 > 1){ //find last bit set to 1 (format len bit)
757 lo2=lo2 >> 1;
758 idx3++;
759 }
760 bitlen = idx3+19;
761 fc =0;
762 cardnum=0;
763 if(bitlen == 26){
764 cardnum = (lo>>1)&0xFFFF;
765 fc = (lo>>17)&0xFF;
766 }
767 if(bitlen == 37){
768 cardnum = (lo>>1)&0x7FFFF;
769 fc = ((hi&0xF)<<12)|(lo>>20);
770 }
771 if(bitlen == 34){
772 cardnum = (lo>>1)&0xFFFF;
773 fc= ((hi&1)<<15)|(lo>>17);
774 }
775 if(bitlen == 35){
776 cardnum = (lo>>1)&0xFFFFF;
777 fc = ((hi&1)<<11)|(lo>>21);
778 }
779 }
780 else { //if bit 38 is not set then 37 bit format is used
781 bitlen= 37;
782 fc =0;
783 cardnum=0;
784 if(bitlen==37){
785 cardnum = (lo>>1)&0x7FFFF;
786 fc = ((hi&0xF)<<12)|(lo>>20);
787 }
788 }
789 //Dbprintf("TAG ID: %x%08x (%d)",
790 // (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
791 Dbprintf("TAG ID: %x%08x (%d) - Format Len: %dbit - FC: %d - Card: %d",
792 (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF,
793 (unsigned int) bitlen, (unsigned int) fc, (unsigned int) cardnum);
794 }
795 if (findone){
796 if (ledcontrol) LED_A_OFF();
797 *high = hi;
798 *low = lo;
799 return;
800 }
801 // reset
802 hi2 = hi = lo = 0;
803 }
804 WDT_HIT();
805 }
806 DbpString("Stopped");
807 if (ledcontrol) LED_A_OFF();
808}
809
810void CmdEM410xdemod(int findone, int *high, int *low, int ledcontrol)
811{
812 uint8_t *dest = BigBuf_get_addr();
813
814 size_t size=0, idx=0;
815 int clk=0, invert=0, errCnt=0, maxErr=20;
816 uint64_t lo=0;
817 // Configure to go in 125Khz listen mode
818 LFSetupFPGAForADC(95, true);
819
820 while(!BUTTON_PRESS()) {
821
822 WDT_HIT();
823 if (ledcontrol) LED_A_ON();
824
825 DoAcquisition_default(-1,true);
826 size = BigBuf_max_traceLen();
827 //Dbprintf("DEBUG: Buffer got");
828 //askdemod and manchester decode
829 errCnt = askmandemod(dest, &size, &clk, &invert, maxErr);
830 //Dbprintf("DEBUG: ASK Got");
831 WDT_HIT();
832
833 if (errCnt>=0){
834 lo = Em410xDecode(dest, &size, &idx);
835 //Dbprintf("DEBUG: EM GOT");
836 if (lo>0){
837 Dbprintf("EM TAG ID: %02x%08x - (%05d_%03d_%08d)",
838 (uint32_t)(lo>>32),
839 (uint32_t)lo,
840 (uint32_t)(lo&0xFFFF),
841 (uint32_t)((lo>>16LL) & 0xFF),
842 (uint32_t)(lo & 0xFFFFFF));
843 }
844 if (findone){
845 if (ledcontrol) LED_A_OFF();
846 *high=lo>>32;
847 *low=lo & 0xFFFFFFFF;
848 return;
849 }
850 } else{
851 //Dbprintf("DEBUG: No Tag");
852 }
853 WDT_HIT();
854 lo = 0;
855 clk=0;
856 invert=0;
857 errCnt=0;
858 size=0;
859 }
860 DbpString("Stopped");
861 if (ledcontrol) LED_A_OFF();
862}
863
864void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
865{
866 uint8_t *dest = BigBuf_get_addr();
867 int idx=0;
868 uint32_t code=0, code2=0;
869 uint8_t version=0;
870 uint8_t facilitycode=0;
871 uint16_t number=0;
872 // Configure to go in 125Khz listen mode
873 LFSetupFPGAForADC(95, true);
874
875 while(!BUTTON_PRESS()) {
876 WDT_HIT();
877 if (ledcontrol) LED_A_ON();
878 DoAcquisition_default(-1,true);
879 //fskdemod and get start index
880 WDT_HIT();
881 idx = IOdemodFSK(dest, BigBuf_max_traceLen());
882 if (idx>0){
883 //valid tag found
884
885 //Index map
886 //0 10 20 30 40 50 60
887 //| | | | | | |
888 //01234567 8 90123456 7 89012345 6 78901234 5 67890123 4 56789012 3 45678901 23
889 //-----------------------------------------------------------------------------
890 //00000000 0 11110000 1 facility 1 version* 1 code*one 1 code*two 1 ???????? 11
891 //
892 //XSF(version)facility:codeone+codetwo
893 //Handle the data
894 if(findone){ //only print binary if we are doing one
895 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx], dest[idx+1], dest[idx+2],dest[idx+3],dest[idx+4],dest[idx+5],dest[idx+6],dest[idx+7],dest[idx+8]);
896 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+9], dest[idx+10],dest[idx+11],dest[idx+12],dest[idx+13],dest[idx+14],dest[idx+15],dest[idx+16],dest[idx+17]);
897 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+18],dest[idx+19],dest[idx+20],dest[idx+21],dest[idx+22],dest[idx+23],dest[idx+24],dest[idx+25],dest[idx+26]);
898 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+27],dest[idx+28],dest[idx+29],dest[idx+30],dest[idx+31],dest[idx+32],dest[idx+33],dest[idx+34],dest[idx+35]);
899 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+36],dest[idx+37],dest[idx+38],dest[idx+39],dest[idx+40],dest[idx+41],dest[idx+42],dest[idx+43],dest[idx+44]);
900 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+45],dest[idx+46],dest[idx+47],dest[idx+48],dest[idx+49],dest[idx+50],dest[idx+51],dest[idx+52],dest[idx+53]);
901 Dbprintf("%d%d%d%d%d%d%d%d %d%d",dest[idx+54],dest[idx+55],dest[idx+56],dest[idx+57],dest[idx+58],dest[idx+59],dest[idx+60],dest[idx+61],dest[idx+62],dest[idx+63]);
902 }
903 code = bytebits_to_byte(dest+idx,32);
904 code2 = bytebits_to_byte(dest+idx+32,32);
905 version = bytebits_to_byte(dest+idx+27,8); //14,4
906 facilitycode = bytebits_to_byte(dest+idx+18,8) ;
907 number = (bytebits_to_byte(dest+idx+36,8)<<8)|(bytebits_to_byte(dest+idx+45,8)); //36,9
908
909 Dbprintf("XSF(%02d)%02x:%05d (%08x%08x)",version,facilitycode,number,code,code2);
910 // if we're only looking for one tag
911 if (findone){
912 if (ledcontrol) LED_A_OFF();
913 //LED_A_OFF();
914 *high=code;
915 *low=code2;
916 return;
917 }
918 code=code2=0;
919 version=facilitycode=0;
920 number=0;
921 idx=0;
922 }
923 WDT_HIT();
924 }
925 DbpString("Stopped");
926 if (ledcontrol) LED_A_OFF();
927}
928
929/*------------------------------
930 * T5555/T5557/T5567 routines
931 *------------------------------
932 */
933
934/* T55x7 configuration register definitions */
935#define T55x7_POR_DELAY 0x00000001
936#define T55x7_ST_TERMINATOR 0x00000008
937#define T55x7_PWD 0x00000010
938#define T55x7_MAXBLOCK_SHIFT 5
939#define T55x7_AOR 0x00000200
940#define T55x7_PSKCF_RF_2 0
941#define T55x7_PSKCF_RF_4 0x00000400
942#define T55x7_PSKCF_RF_8 0x00000800
943#define T55x7_MODULATION_DIRECT 0
944#define T55x7_MODULATION_PSK1 0x00001000
945#define T55x7_MODULATION_PSK2 0x00002000
946#define T55x7_MODULATION_PSK3 0x00003000
947#define T55x7_MODULATION_FSK1 0x00004000
948#define T55x7_MODULATION_FSK2 0x00005000
949#define T55x7_MODULATION_FSK1a 0x00006000
950#define T55x7_MODULATION_FSK2a 0x00007000
951#define T55x7_MODULATION_MANCHESTER 0x00008000
952#define T55x7_MODULATION_BIPHASE 0x00010000
953#define T55x7_BITRATE_RF_8 0
954#define T55x7_BITRATE_RF_16 0x00040000
955#define T55x7_BITRATE_RF_32 0x00080000
956#define T55x7_BITRATE_RF_40 0x000C0000
957#define T55x7_BITRATE_RF_50 0x00100000
958#define T55x7_BITRATE_RF_64 0x00140000
959#define T55x7_BITRATE_RF_100 0x00180000
960#define T55x7_BITRATE_RF_128 0x001C0000
961
962/* T5555 (Q5) configuration register definitions */
963#define T5555_ST_TERMINATOR 0x00000001
964#define T5555_MAXBLOCK_SHIFT 0x00000001
965#define T5555_MODULATION_MANCHESTER 0
966#define T5555_MODULATION_PSK1 0x00000010
967#define T5555_MODULATION_PSK2 0x00000020
968#define T5555_MODULATION_PSK3 0x00000030
969#define T5555_MODULATION_FSK1 0x00000040
970#define T5555_MODULATION_FSK2 0x00000050
971#define T5555_MODULATION_BIPHASE 0x00000060
972#define T5555_MODULATION_DIRECT 0x00000070
973#define T5555_INVERT_OUTPUT 0x00000080
974#define T5555_PSK_RF_2 0
975#define T5555_PSK_RF_4 0x00000100
976#define T5555_PSK_RF_8 0x00000200
977#define T5555_USE_PWD 0x00000400
978#define T5555_USE_AOR 0x00000800
979#define T5555_BITRATE_SHIFT 12
980#define T5555_FAST_WRITE 0x00004000
981#define T5555_PAGE_SELECT 0x00008000
982
983/*
984 * Relevant times in microsecond
985 * To compensate antenna falling times shorten the write times
986 * and enlarge the gap ones.
987 */
988#define START_GAP 250
989#define WRITE_GAP 160
990#define WRITE_0 144 // 192
991#define WRITE_1 400 // 432 for T55x7; 448 for E5550
992
993// Write one bit to card
994void T55xxWriteBit(int bit)
995{
996 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
997 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
998 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
999 if (bit == 0)
1000 SpinDelayUs(WRITE_0);
1001 else
1002 SpinDelayUs(WRITE_1);
1003 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1004 SpinDelayUs(WRITE_GAP);
1005}
1006
1007// Write one card block in page 0, no lock
1008void T55xxWriteBlock(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
1009{
1010 //unsigned int i; //enio adjustment 12/10/14
1011 uint32_t i;
1012
1013 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1014 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1015 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1016
1017 // Give it a bit of time for the resonant antenna to settle.
1018 // And for the tag to fully power up
1019 SpinDelay(150);
1020
1021 // Now start writting
1022 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1023 SpinDelayUs(START_GAP);
1024
1025 // Opcode
1026 T55xxWriteBit(1);
1027 T55xxWriteBit(0); //Page 0
1028 if (PwdMode == 1){
1029 // Pwd
1030 for (i = 0x80000000; i != 0; i >>= 1)
1031 T55xxWriteBit(Pwd & i);
1032 }
1033 // Lock bit
1034 T55xxWriteBit(0);
1035
1036 // Data
1037 for (i = 0x80000000; i != 0; i >>= 1)
1038 T55xxWriteBit(Data & i);
1039
1040 // Block
1041 for (i = 0x04; i != 0; i >>= 1)
1042 T55xxWriteBit(Block & i);
1043
1044 // Now perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550,
1045 // so wait a little more)
1046 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1047 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1048 SpinDelay(20);
1049 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1050}
1051
1052// Read one card block in page 0
1053void T55xxReadBlock(uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
1054{
1055 uint8_t *dest = BigBuf_get_addr();
1056 //int m=0, i=0; //enio adjustment 12/10/14
1057 uint32_t m=0, i=0;
1058 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1059 m = BigBuf_max_traceLen();
1060 // Clear destination buffer before sending the command
1061 memset(dest, 128, m);
1062 // Connect the A/D to the peak-detected low-frequency path.
1063 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1064 // Now set up the SSC to get the ADC samples that are now streaming at us.
1065 FpgaSetupSsc();
1066
1067 LED_D_ON();
1068 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1069 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1070
1071 // Give it a bit of time for the resonant antenna to settle.
1072 // And for the tag to fully power up
1073 SpinDelay(150);
1074
1075 // Now start writting
1076 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1077 SpinDelayUs(START_GAP);
1078
1079 // Opcode
1080 T55xxWriteBit(1);
1081 T55xxWriteBit(0); //Page 0
1082 if (PwdMode == 1){
1083 // Pwd
1084 for (i = 0x80000000; i != 0; i >>= 1)
1085 T55xxWriteBit(Pwd & i);
1086 }
1087 // Lock bit
1088 T55xxWriteBit(0);
1089 // Block
1090 for (i = 0x04; i != 0; i >>= 1)
1091 T55xxWriteBit(Block & i);
1092
1093 // Turn field on to read the response
1094 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1095 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1096
1097 // Now do the acquisition
1098 i = 0;
1099 for(;;) {
1100 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1101 AT91C_BASE_SSC->SSC_THR = 0x43;
1102 }
1103 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1104 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1105 // we don't care about actual value, only if it's more or less than a
1106 // threshold essentially we capture zero crossings for later analysis
1107 // if(dest[i] < 127) dest[i] = 0; else dest[i] = 1;
1108 i++;
1109 if (i >= m) break;
1110 }
1111 }
1112
1113 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1114 LED_D_OFF();
1115 DbpString("DONE!");
1116}
1117
1118// Read card traceability data (page 1)
1119void T55xxReadTrace(void){
1120 uint8_t *dest = BigBuf_get_addr();
1121 int m=0, i=0;
1122
1123 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1124 m = BigBuf_max_traceLen();
1125 // Clear destination buffer before sending the command
1126 memset(dest, 128, m);
1127 // Connect the A/D to the peak-detected low-frequency path.
1128 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1129 // Now set up the SSC to get the ADC samples that are now streaming at us.
1130 FpgaSetupSsc();
1131
1132 LED_D_ON();
1133 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1134 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1135
1136 // Give it a bit of time for the resonant antenna to settle.
1137 // And for the tag to fully power up
1138 SpinDelay(150);
1139
1140 // Now start writting
1141 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1142 SpinDelayUs(START_GAP);
1143
1144 // Opcode
1145 T55xxWriteBit(1);
1146 T55xxWriteBit(1); //Page 1
1147
1148 // Turn field on to read the response
1149 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1150 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1151
1152 // Now do the acquisition
1153 i = 0;
1154 for(;;) {
1155 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1156 AT91C_BASE_SSC->SSC_THR = 0x43;
1157 }
1158 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1159 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1160 i++;
1161 if (i >= m) break;
1162 }
1163 }
1164
1165 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1166 LED_D_OFF();
1167 DbpString("DONE!");
1168}
1169
1170/*-------------- Cloning routines -----------*/
1171// Copy HID id to card and setup block 0 config
1172void CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT)
1173{
1174 int data1=0, data2=0, data3=0, data4=0, data5=0, data6=0; //up to six blocks for long format
1175 int last_block = 0;
1176
1177 if (longFMT){
1178 // Ensure no more than 84 bits supplied
1179 if (hi2>0xFFFFF) {
1180 DbpString("Tags can only have 84 bits.");
1181 return;
1182 }
1183 // Build the 6 data blocks for supplied 84bit ID
1184 last_block = 6;
1185 data1 = 0x1D96A900; // load preamble (1D) & long format identifier (9E manchester encoded)
1186 for (int i=0;i<4;i++) {
1187 if (hi2 & (1<<(19-i)))
1188 data1 |= (1<<(((3-i)*2)+1)); // 1 -> 10
1189 else
1190 data1 |= (1<<((3-i)*2)); // 0 -> 01
1191 }
1192
1193 data2 = 0;
1194 for (int i=0;i<16;i++) {
1195 if (hi2 & (1<<(15-i)))
1196 data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1197 else
1198 data2 |= (1<<((15-i)*2)); // 0 -> 01
1199 }
1200
1201 data3 = 0;
1202 for (int i=0;i<16;i++) {
1203 if (hi & (1<<(31-i)))
1204 data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1205 else
1206 data3 |= (1<<((15-i)*2)); // 0 -> 01
1207 }
1208
1209 data4 = 0;
1210 for (int i=0;i<16;i++) {
1211 if (hi & (1<<(15-i)))
1212 data4 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1213 else
1214 data4 |= (1<<((15-i)*2)); // 0 -> 01
1215 }
1216
1217 data5 = 0;
1218 for (int i=0;i<16;i++) {
1219 if (lo & (1<<(31-i)))
1220 data5 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1221 else
1222 data5 |= (1<<((15-i)*2)); // 0 -> 01
1223 }
1224
1225 data6 = 0;
1226 for (int i=0;i<16;i++) {
1227 if (lo & (1<<(15-i)))
1228 data6 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1229 else
1230 data6 |= (1<<((15-i)*2)); // 0 -> 01
1231 }
1232 }
1233 else {
1234 // Ensure no more than 44 bits supplied
1235 if (hi>0xFFF) {
1236 DbpString("Tags can only have 44 bits.");
1237 return;
1238 }
1239
1240 // Build the 3 data blocks for supplied 44bit ID
1241 last_block = 3;
1242
1243 data1 = 0x1D000000; // load preamble
1244
1245 for (int i=0;i<12;i++) {
1246 if (hi & (1<<(11-i)))
1247 data1 |= (1<<(((11-i)*2)+1)); // 1 -> 10
1248 else
1249 data1 |= (1<<((11-i)*2)); // 0 -> 01
1250 }
1251
1252 data2 = 0;
1253 for (int i=0;i<16;i++) {
1254 if (lo & (1<<(31-i)))
1255 data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1256 else
1257 data2 |= (1<<((15-i)*2)); // 0 -> 01
1258 }
1259
1260 data3 = 0;
1261 for (int i=0;i<16;i++) {
1262 if (lo & (1<<(15-i)))
1263 data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1264 else
1265 data3 |= (1<<((15-i)*2)); // 0 -> 01
1266 }
1267 }
1268
1269 LED_D_ON();
1270 // Program the data blocks for supplied ID
1271 // and the block 0 for HID format
1272 T55xxWriteBlock(data1,1,0,0);
1273 T55xxWriteBlock(data2,2,0,0);
1274 T55xxWriteBlock(data3,3,0,0);
1275
1276 if (longFMT) { // if long format there are 6 blocks
1277 T55xxWriteBlock(data4,4,0,0);
1278 T55xxWriteBlock(data5,5,0,0);
1279 T55xxWriteBlock(data6,6,0,0);
1280 }
1281
1282 // Config for HID (RF/50, FSK2a, Maxblock=3 for short/6 for long)
1283 T55xxWriteBlock(T55x7_BITRATE_RF_50 |
1284 T55x7_MODULATION_FSK2a |
1285 last_block << T55x7_MAXBLOCK_SHIFT,
1286 0,0,0);
1287
1288 LED_D_OFF();
1289
1290 DbpString("DONE!");
1291}
1292
1293void CopyIOtoT55x7(uint32_t hi, uint32_t lo, uint8_t longFMT)
1294{
1295 int data1=0, data2=0; //up to six blocks for long format
1296
1297 data1 = hi; // load preamble
1298 data2 = lo;
1299
1300 LED_D_ON();
1301 // Program the data blocks for supplied ID
1302 // and the block 0 for HID format
1303 T55xxWriteBlock(data1,1,0,0);
1304 T55xxWriteBlock(data2,2,0,0);
1305
1306 //Config Block
1307 T55xxWriteBlock(0x00147040,0,0,0);
1308 LED_D_OFF();
1309
1310 DbpString("DONE!");
1311}
1312
1313// Define 9bit header for EM410x tags
1314#define EM410X_HEADER 0x1FF
1315#define EM410X_ID_LENGTH 40
1316
1317void WriteEM410x(uint32_t card, uint32_t id_hi, uint32_t id_lo)
1318{
1319 int i, id_bit;
1320 uint64_t id = EM410X_HEADER;
1321 uint64_t rev_id = 0; // reversed ID
1322 int c_parity[4]; // column parity
1323 int r_parity = 0; // row parity
1324 uint32_t clock = 0;
1325
1326 // Reverse ID bits given as parameter (for simpler operations)
1327 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1328 if (i < 32) {
1329 rev_id = (rev_id << 1) | (id_lo & 1);
1330 id_lo >>= 1;
1331 } else {
1332 rev_id = (rev_id << 1) | (id_hi & 1);
1333 id_hi >>= 1;
1334 }
1335 }
1336
1337 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1338 id_bit = rev_id & 1;
1339
1340 if (i % 4 == 0) {
1341 // Don't write row parity bit at start of parsing
1342 if (i)
1343 id = (id << 1) | r_parity;
1344 // Start counting parity for new row
1345 r_parity = id_bit;
1346 } else {
1347 // Count row parity
1348 r_parity ^= id_bit;
1349 }
1350
1351 // First elements in column?
1352 if (i < 4)
1353 // Fill out first elements
1354 c_parity[i] = id_bit;
1355 else
1356 // Count column parity
1357 c_parity[i % 4] ^= id_bit;
1358
1359 // Insert ID bit
1360 id = (id << 1) | id_bit;
1361 rev_id >>= 1;
1362 }
1363
1364 // Insert parity bit of last row
1365 id = (id << 1) | r_parity;
1366
1367 // Fill out column parity at the end of tag
1368 for (i = 0; i < 4; ++i)
1369 id = (id << 1) | c_parity[i];
1370
1371 // Add stop bit
1372 id <<= 1;
1373
1374 Dbprintf("Started writing %s tag ...", card ? "T55x7":"T5555");
1375 LED_D_ON();
1376
1377 // Write EM410x ID
1378 T55xxWriteBlock((uint32_t)(id >> 32), 1, 0, 0);
1379 T55xxWriteBlock((uint32_t)id, 2, 0, 0);
1380
1381 // Config for EM410x (RF/64, Manchester, Maxblock=2)
1382 if (card) {
1383 // Clock rate is stored in bits 8-15 of the card value
1384 clock = (card & 0xFF00) >> 8;
1385 Dbprintf("Clock rate: %d", clock);
1386 switch (clock)
1387 {
1388 case 32:
1389 clock = T55x7_BITRATE_RF_32;
1390 break;
1391 case 16:
1392 clock = T55x7_BITRATE_RF_16;
1393 break;
1394 case 0:
1395 // A value of 0 is assumed to be 64 for backwards-compatibility
1396 // Fall through...
1397 case 64:
1398 clock = T55x7_BITRATE_RF_64;
1399 break;
1400 default:
1401 Dbprintf("Invalid clock rate: %d", clock);
1402 return;
1403 }
1404
1405 // Writing configuration for T55x7 tag
1406 T55xxWriteBlock(clock |
1407 T55x7_MODULATION_MANCHESTER |
1408 2 << T55x7_MAXBLOCK_SHIFT,
1409 0, 0, 0);
1410 }
1411 else
1412 // Writing configuration for T5555(Q5) tag
1413 T55xxWriteBlock(0x1F << T5555_BITRATE_SHIFT |
1414 T5555_MODULATION_MANCHESTER |
1415 2 << T5555_MAXBLOCK_SHIFT,
1416 0, 0, 0);
1417
1418 LED_D_OFF();
1419 Dbprintf("Tag %s written with 0x%08x%08x\n", card ? "T55x7":"T5555",
1420 (uint32_t)(id >> 32), (uint32_t)id);
1421}
1422
1423// Clone Indala 64-bit tag by UID to T55x7
1424void CopyIndala64toT55x7(int hi, int lo)
1425{
1426
1427 //Program the 2 data blocks for supplied 64bit UID
1428 // and the block 0 for Indala64 format
1429 T55xxWriteBlock(hi,1,0,0);
1430 T55xxWriteBlock(lo,2,0,0);
1431 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=2)
1432 T55xxWriteBlock(T55x7_BITRATE_RF_32 |
1433 T55x7_MODULATION_PSK1 |
1434 2 << T55x7_MAXBLOCK_SHIFT,
1435 0, 0, 0);
1436 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=2;Inverse data)
1437 // T5567WriteBlock(0x603E1042,0);
1438
1439 DbpString("DONE!");
1440
1441}
1442
1443void CopyIndala224toT55x7(int uid1, int uid2, int uid3, int uid4, int uid5, int uid6, int uid7)
1444{
1445
1446 //Program the 7 data blocks for supplied 224bit UID
1447 // and the block 0 for Indala224 format
1448 T55xxWriteBlock(uid1,1,0,0);
1449 T55xxWriteBlock(uid2,2,0,0);
1450 T55xxWriteBlock(uid3,3,0,0);
1451 T55xxWriteBlock(uid4,4,0,0);
1452 T55xxWriteBlock(uid5,5,0,0);
1453 T55xxWriteBlock(uid6,6,0,0);
1454 T55xxWriteBlock(uid7,7,0,0);
1455 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=7)
1456 T55xxWriteBlock(T55x7_BITRATE_RF_32 |
1457 T55x7_MODULATION_PSK1 |
1458 7 << T55x7_MAXBLOCK_SHIFT,
1459 0,0,0);
1460 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=7;Inverse data)
1461 // T5567WriteBlock(0x603E10E2,0);
1462
1463 DbpString("DONE!");
1464
1465}
1466
1467
1468#define abs(x) ( ((x)<0) ? -(x) : (x) )
1469#define max(x,y) ( x<y ? y:x)
1470
1471int DemodPCF7931(uint8_t **outBlocks) {
1472 uint8_t BitStream[256];
1473 uint8_t Blocks[8][16];
1474 uint8_t *GraphBuffer = BigBuf_get_addr();
1475 int GraphTraceLen = BigBuf_max_traceLen();
1476 int i, j, lastval, bitidx, half_switch;
1477 int clock = 64;
1478 int tolerance = clock / 8;
1479 int pmc, block_done;
1480 int lc, warnings = 0;
1481 int num_blocks = 0;
1482 int lmin=128, lmax=128;
1483 uint8_t dir;
1484
1485 LFSetupFPGAForADC(95, true);
1486 DoAcquisition_default(0, 0);
1487
1488
1489 lmin = 64;
1490 lmax = 192;
1491
1492 i = 2;
1493
1494 /* Find first local max/min */
1495 if(GraphBuffer[1] > GraphBuffer[0]) {
1496 while(i < GraphTraceLen) {
1497 if( !(GraphBuffer[i] > GraphBuffer[i-1]) && GraphBuffer[i] > lmax)
1498 break;
1499 i++;
1500 }
1501 dir = 0;
1502 }
1503 else {
1504 while(i < GraphTraceLen) {
1505 if( !(GraphBuffer[i] < GraphBuffer[i-1]) && GraphBuffer[i] < lmin)
1506 break;
1507 i++;
1508 }
1509 dir = 1;
1510 }
1511
1512 lastval = i++;
1513 half_switch = 0;
1514 pmc = 0;
1515 block_done = 0;
1516
1517 for (bitidx = 0; i < GraphTraceLen; i++)
1518 {
1519 if ( (GraphBuffer[i-1] > GraphBuffer[i] && dir == 1 && GraphBuffer[i] > lmax) || (GraphBuffer[i-1] < GraphBuffer[i] && dir == 0 && GraphBuffer[i] < lmin))
1520 {
1521 lc = i - lastval;
1522 lastval = i;
1523
1524 // Switch depending on lc length:
1525 // Tolerance is 1/8 of clock rate (arbitrary)
1526 if (abs(lc-clock/4) < tolerance) {
1527 // 16T0
1528 if((i - pmc) == lc) { /* 16T0 was previous one */
1529 /* It's a PMC ! */
1530 i += (128+127+16+32+33+16)-1;
1531 lastval = i;
1532 pmc = 0;
1533 block_done = 1;
1534 }
1535 else {
1536 pmc = i;
1537 }
1538 } else if (abs(lc-clock/2) < tolerance) {
1539 // 32TO
1540 if((i - pmc) == lc) { /* 16T0 was previous one */
1541 /* It's a PMC ! */
1542 i += (128+127+16+32+33)-1;
1543 lastval = i;
1544 pmc = 0;
1545 block_done = 1;
1546 }
1547 else if(half_switch == 1) {
1548 BitStream[bitidx++] = 0;
1549 half_switch = 0;
1550 }
1551 else
1552 half_switch++;
1553 } else if (abs(lc-clock) < tolerance) {
1554 // 64TO
1555 BitStream[bitidx++] = 1;
1556 } else {
1557 // Error
1558 warnings++;
1559 if (warnings > 10)
1560 {
1561 Dbprintf("Error: too many detection errors, aborting.");
1562 return 0;
1563 }
1564 }
1565
1566 if(block_done == 1) {
1567 if(bitidx == 128) {
1568 for(j=0; j<16; j++) {
1569 Blocks[num_blocks][j] = 128*BitStream[j*8+7]+
1570 64*BitStream[j*8+6]+
1571 32*BitStream[j*8+5]+
1572 16*BitStream[j*8+4]+
1573 8*BitStream[j*8+3]+
1574 4*BitStream[j*8+2]+
1575 2*BitStream[j*8+1]+
1576 BitStream[j*8];
1577 }
1578 num_blocks++;
1579 }
1580 bitidx = 0;
1581 block_done = 0;
1582 half_switch = 0;
1583 }
1584 if(i < GraphTraceLen)
1585 {
1586 if (GraphBuffer[i-1] > GraphBuffer[i]) dir=0;
1587 else dir = 1;
1588 }
1589 }
1590 if(bitidx==255)
1591 bitidx=0;
1592 warnings = 0;
1593 if(num_blocks == 4) break;
1594 }
1595 memcpy(outBlocks, Blocks, 16*num_blocks);
1596 return num_blocks;
1597}
1598
1599int IsBlock0PCF7931(uint8_t *Block) {
1600 // Assume RFU means 0 :)
1601 if((memcmp(Block, "\x00\x00\x00\x00\x00\x00\x00\x01", 8) == 0) && memcmp(Block+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) // PAC enabled
1602 return 1;
1603 if((memcmp(Block+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) && Block[7] == 0) // PAC disabled, can it *really* happen ?
1604 return 1;
1605 return 0;
1606}
1607
1608int IsBlock1PCF7931(uint8_t *Block) {
1609 // Assume RFU means 0 :)
1610 if(Block[10] == 0 && Block[11] == 0 && Block[12] == 0 && Block[13] == 0)
1611 if((Block[14] & 0x7f) <= 9 && Block[15] <= 9)
1612 return 1;
1613
1614 return 0;
1615}
1616
1617#define ALLOC 16
1618
1619void ReadPCF7931() {
1620 uint8_t Blocks[8][17];
1621 uint8_t tmpBlocks[4][16];
1622 int i, j, ind, ind2, n;
1623 int num_blocks = 0;
1624 int max_blocks = 8;
1625 int ident = 0;
1626 int error = 0;
1627 int tries = 0;
1628
1629 memset(Blocks, 0, 8*17*sizeof(uint8_t));
1630
1631 do {
1632 memset(tmpBlocks, 0, 4*16*sizeof(uint8_t));
1633 n = DemodPCF7931((uint8_t**)tmpBlocks);
1634 if(!n)
1635 error++;
1636 if(error==10 && num_blocks == 0) {
1637 Dbprintf("Error, no tag or bad tag");
1638 return;
1639 }
1640 else if (tries==20 || error==10) {
1641 Dbprintf("Error reading the tag");
1642 Dbprintf("Here is the partial content");
1643 goto end;
1644 }
1645
1646 for(i=0; i<n; i++)
1647 Dbprintf("(dbg) %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
1648 tmpBlocks[i][0], tmpBlocks[i][1], tmpBlocks[i][2], tmpBlocks[i][3], tmpBlocks[i][4], tmpBlocks[i][5], tmpBlocks[i][6], tmpBlocks[i][7],
1649 tmpBlocks[i][8], tmpBlocks[i][9], tmpBlocks[i][10], tmpBlocks[i][11], tmpBlocks[i][12], tmpBlocks[i][13], tmpBlocks[i][14], tmpBlocks[i][15]);
1650 if(!ident) {
1651 for(i=0; i<n; i++) {
1652 if(IsBlock0PCF7931(tmpBlocks[i])) {
1653 // Found block 0 ?
1654 if(i < n-1 && IsBlock1PCF7931(tmpBlocks[i+1])) {
1655 // Found block 1!
1656 // \o/
1657 ident = 1;
1658 memcpy(Blocks[0], tmpBlocks[i], 16);
1659 Blocks[0][ALLOC] = 1;
1660 memcpy(Blocks[1], tmpBlocks[i+1], 16);
1661 Blocks[1][ALLOC] = 1;
1662 max_blocks = max((Blocks[1][14] & 0x7f), Blocks[1][15]) + 1;
1663 // Debug print
1664 Dbprintf("(dbg) Max blocks: %d", max_blocks);
1665 num_blocks = 2;
1666 // Handle following blocks
1667 for(j=i+2, ind2=2; j!=i; j++, ind2++, num_blocks++) {
1668 if(j==n) j=0;
1669 if(j==i) break;
1670 memcpy(Blocks[ind2], tmpBlocks[j], 16);
1671 Blocks[ind2][ALLOC] = 1;
1672 }
1673 break;
1674 }
1675 }
1676 }
1677 }
1678 else {
1679 for(i=0; i<n; i++) { // Look for identical block in known blocks
1680 if(memcmp(tmpBlocks[i], "\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00", 16)) { // Block is not full of 00
1681 for(j=0; j<max_blocks; j++) {
1682 if(Blocks[j][ALLOC] == 1 && !memcmp(tmpBlocks[i], Blocks[j], 16)) {
1683 // Found an identical block
1684 for(ind=i-1,ind2=j-1; ind >= 0; ind--,ind2--) {
1685 if(ind2 < 0)
1686 ind2 = max_blocks;
1687 if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found
1688 // Dbprintf("Tmp %d -> Block %d", ind, ind2);
1689 memcpy(Blocks[ind2], tmpBlocks[ind], 16);
1690 Blocks[ind2][ALLOC] = 1;
1691 num_blocks++;
1692 if(num_blocks == max_blocks) goto end;
1693 }
1694 }
1695 for(ind=i+1,ind2=j+1; ind < n; ind++,ind2++) {
1696 if(ind2 > max_blocks)
1697 ind2 = 0;
1698 if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found
1699 // Dbprintf("Tmp %d -> Block %d", ind, ind2);
1700 memcpy(Blocks[ind2], tmpBlocks[ind], 16);
1701 Blocks[ind2][ALLOC] = 1;
1702 num_blocks++;
1703 if(num_blocks == max_blocks) goto end;
1704 }
1705 }
1706 }
1707 }
1708 }
1709 }
1710 }
1711 tries++;
1712 if (BUTTON_PRESS()) return;
1713 } while (num_blocks != max_blocks);
1714 end:
1715 Dbprintf("-----------------------------------------");
1716 Dbprintf("Memory content:");
1717 Dbprintf("-----------------------------------------");
1718 for(i=0; i<max_blocks; i++) {
1719 if(Blocks[i][ALLOC]==1)
1720 Dbprintf("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
1721 Blocks[i][0], Blocks[i][1], Blocks[i][2], Blocks[i][3], Blocks[i][4], Blocks[i][5], Blocks[i][6], Blocks[i][7],
1722 Blocks[i][8], Blocks[i][9], Blocks[i][10], Blocks[i][11], Blocks[i][12], Blocks[i][13], Blocks[i][14], Blocks[i][15]);
1723 else
1724 Dbprintf("<missing block %d>", i);
1725 }
1726 Dbprintf("-----------------------------------------");
1727
1728 return ;
1729}
1730
1731
1732//-----------------------------------
1733// EM4469 / EM4305 routines
1734//-----------------------------------
1735#define FWD_CMD_LOGIN 0xC //including the even parity, binary mirrored
1736#define FWD_CMD_WRITE 0xA
1737#define FWD_CMD_READ 0x9
1738#define FWD_CMD_DISABLE 0x5
1739
1740
1741uint8_t forwardLink_data[64]; //array of forwarded bits
1742uint8_t * forward_ptr; //ptr for forward message preparation
1743uint8_t fwd_bit_sz; //forwardlink bit counter
1744uint8_t * fwd_write_ptr; //forwardlink bit pointer
1745
1746//====================================================================
1747// prepares command bits
1748// see EM4469 spec
1749//====================================================================
1750//--------------------------------------------------------------------
1751uint8_t Prepare_Cmd( uint8_t cmd ) {
1752 //--------------------------------------------------------------------
1753
1754 *forward_ptr++ = 0; //start bit
1755 *forward_ptr++ = 0; //second pause for 4050 code
1756
1757 *forward_ptr++ = cmd;
1758 cmd >>= 1;
1759 *forward_ptr++ = cmd;
1760 cmd >>= 1;
1761 *forward_ptr++ = cmd;
1762 cmd >>= 1;
1763 *forward_ptr++ = cmd;
1764
1765 return 6; //return number of emited bits
1766}
1767
1768//====================================================================
1769// prepares address bits
1770// see EM4469 spec
1771//====================================================================
1772
1773//--------------------------------------------------------------------
1774uint8_t Prepare_Addr( uint8_t addr ) {
1775 //--------------------------------------------------------------------
1776
1777 register uint8_t line_parity;
1778
1779 uint8_t i;
1780 line_parity = 0;
1781 for(i=0;i<6;i++) {
1782 *forward_ptr++ = addr;
1783 line_parity ^= addr;
1784 addr >>= 1;
1785 }
1786
1787 *forward_ptr++ = (line_parity & 1);
1788
1789 return 7; //return number of emited bits
1790}
1791
1792//====================================================================
1793// prepares data bits intreleaved with parity bits
1794// see EM4469 spec
1795//====================================================================
1796
1797//--------------------------------------------------------------------
1798uint8_t Prepare_Data( uint16_t data_low, uint16_t data_hi) {
1799 //--------------------------------------------------------------------
1800
1801 register uint8_t line_parity;
1802 register uint8_t column_parity;
1803 register uint8_t i, j;
1804 register uint16_t data;
1805
1806 data = data_low;
1807 column_parity = 0;
1808
1809 for(i=0; i<4; i++) {
1810 line_parity = 0;
1811 for(j=0; j<8; j++) {
1812 line_parity ^= data;
1813 column_parity ^= (data & 1) << j;
1814 *forward_ptr++ = data;
1815 data >>= 1;
1816 }
1817 *forward_ptr++ = line_parity;
1818 if(i == 1)
1819 data = data_hi;
1820 }
1821
1822 for(j=0; j<8; j++) {
1823 *forward_ptr++ = column_parity;
1824 column_parity >>= 1;
1825 }
1826 *forward_ptr = 0;
1827
1828 return 45; //return number of emited bits
1829}
1830
1831//====================================================================
1832// Forward Link send function
1833// Requires: forwarLink_data filled with valid bits (1 bit per byte)
1834// fwd_bit_count set with number of bits to be sent
1835//====================================================================
1836void SendForward(uint8_t fwd_bit_count) {
1837
1838 fwd_write_ptr = forwardLink_data;
1839 fwd_bit_sz = fwd_bit_count;
1840
1841 LED_D_ON();
1842
1843 //Field on
1844 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1845 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1846 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1847
1848 // Give it a bit of time for the resonant antenna to settle.
1849 // And for the tag to fully power up
1850 SpinDelay(150);
1851
1852 // force 1st mod pulse (start gap must be longer for 4305)
1853 fwd_bit_sz--; //prepare next bit modulation
1854 fwd_write_ptr++;
1855 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1856 SpinDelayUs(55*8); //55 cycles off (8us each)for 4305
1857 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1858 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1859 SpinDelayUs(16*8); //16 cycles on (8us each)
1860
1861 // now start writting
1862 while(fwd_bit_sz-- > 0) { //prepare next bit modulation
1863 if(((*fwd_write_ptr++) & 1) == 1)
1864 SpinDelayUs(32*8); //32 cycles at 125Khz (8us each)
1865 else {
1866 //These timings work for 4469/4269/4305 (with the 55*8 above)
1867 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1868 SpinDelayUs(23*8); //16-4 cycles off (8us each)
1869 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1870 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1871 SpinDelayUs(9*8); //16 cycles on (8us each)
1872 }
1873 }
1874}
1875
1876void EM4xLogin(uint32_t Password) {
1877
1878 uint8_t fwd_bit_count;
1879
1880 forward_ptr = forwardLink_data;
1881 fwd_bit_count = Prepare_Cmd( FWD_CMD_LOGIN );
1882 fwd_bit_count += Prepare_Data( Password&0xFFFF, Password>>16 );
1883
1884 SendForward(fwd_bit_count);
1885
1886 //Wait for command to complete
1887 SpinDelay(20);
1888
1889}
1890
1891void EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1892
1893 uint8_t fwd_bit_count;
1894 uint8_t *dest = BigBuf_get_addr();
1895 int m=0, i=0;
1896
1897 //If password mode do login
1898 if (PwdMode == 1) EM4xLogin(Pwd);
1899
1900 forward_ptr = forwardLink_data;
1901 fwd_bit_count = Prepare_Cmd( FWD_CMD_READ );
1902 fwd_bit_count += Prepare_Addr( Address );
1903
1904 m = BigBuf_max_traceLen();
1905 // Clear destination buffer before sending the command
1906 memset(dest, 128, m);
1907 // Connect the A/D to the peak-detected low-frequency path.
1908 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1909 // Now set up the SSC to get the ADC samples that are now streaming at us.
1910 FpgaSetupSsc();
1911
1912 SendForward(fwd_bit_count);
1913
1914 // Now do the acquisition
1915 i = 0;
1916 for(;;) {
1917 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1918 AT91C_BASE_SSC->SSC_THR = 0x43;
1919 }
1920 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1921 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1922 i++;
1923 if (i >= m) break;
1924 }
1925 }
1926 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1927 LED_D_OFF();
1928}
1929
1930void EM4xWriteWord(uint32_t Data, uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1931
1932 uint8_t fwd_bit_count;
1933
1934 //If password mode do login
1935 if (PwdMode == 1) EM4xLogin(Pwd);
1936
1937 forward_ptr = forwardLink_data;
1938 fwd_bit_count = Prepare_Cmd( FWD_CMD_WRITE );
1939 fwd_bit_count += Prepare_Addr( Address );
1940 fwd_bit_count += Prepare_Data( Data&0xFFFF, Data>>16 );
1941
1942 SendForward(fwd_bit_count);
1943
1944 //Wait for write to complete
1945 SpinDelay(20);
1946 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1947 LED_D_OFF();
1948}
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