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[proxmark3-svn] / armsrc / lfops.c
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e09f21fa 1//-----------------------------------------------------------------------------
2// This code is licensed to you under the terms of the GNU GPL, version 2 or,
3// at your option, any later version. See the LICENSE.txt file for the text of
4// the license.
5//-----------------------------------------------------------------------------
6// Miscellaneous routines for low frequency tag operations.
7// Tags supported here so far are Texas Instruments (TI), HID
8// Also routines for raw mode reading/simulating of LF waveform
9//-----------------------------------------------------------------------------
10
11#include "proxmark3.h"
12#include "apps.h"
13#include "util.h"
14#include "hitag2.h"
15#include "crc16.h"
16#include "string.h"
17#include "lfdemod.h"
18#include "lfsampling.h"
19
20
21/**
22 * Function to do a modulation and then get samples.
23 * @param delay_off
24 * @param period_0
25 * @param period_1
26 * @param command
27 */
28void ModThenAcquireRawAdcSamples125k(int delay_off, int period_0, int period_1, uint8_t *command)
29{
30
31 int divisor_used = 95; // 125 KHz
32 // see if 'h' was specified
33
34 if (command[strlen((char *) command) - 1] == 'h')
35 divisor_used = 88; // 134.8 KHz
36
37 sample_config sc = { 0,0,1, divisor_used, 0};
38 setSamplingConfig(&sc);
39
40 /* Make sure the tag is reset */
41 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
42 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
43 SpinDelay(2500);
44
45 LFSetupFPGAForADC(sc.divisor, 1);
46
47 // And a little more time for the tag to fully power up
48 SpinDelay(2000);
49
50 // now modulate the reader field
51 while(*command != '\0' && *command != ' ') {
52 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
53 LED_D_OFF();
54 SpinDelayUs(delay_off);
55 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc.divisor);
56
57 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
58 LED_D_ON();
59 if(*(command++) == '0')
60 SpinDelayUs(period_0);
61 else
62 SpinDelayUs(period_1);
63 }
64 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
65 LED_D_OFF();
66 SpinDelayUs(delay_off);
67 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc.divisor);
68
69 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
70
71 // now do the read
72 DoAcquisition_config(false);
73}
74
75
76
77/* blank r/w tag data stream
78...0000000000000000 01111111
791010101010101010101010101010101010101010101010101010101010101010
800011010010100001
8101111111
82101010101010101[0]000...
83
84[5555fe852c5555555555555555fe0000]
85*/
86void ReadTItag(void)
87{
88 // some hardcoded initial params
89 // when we read a TI tag we sample the zerocross line at 2Mhz
90 // TI tags modulate a 1 as 16 cycles of 123.2Khz
91 // TI tags modulate a 0 as 16 cycles of 134.2Khz
92 #define FSAMPLE 2000000
93 #define FREQLO 123200
94 #define FREQHI 134200
95
96 signed char *dest = (signed char *)BigBuf_get_addr();
97 uint16_t n = BigBuf_max_traceLen();
98 // 128 bit shift register [shift3:shift2:shift1:shift0]
99 uint32_t shift3 = 0, shift2 = 0, shift1 = 0, shift0 = 0;
100
101 int i, cycles=0, samples=0;
102 // how many sample points fit in 16 cycles of each frequency
103 uint32_t sampleslo = (FSAMPLE<<4)/FREQLO, sampleshi = (FSAMPLE<<4)/FREQHI;
104 // when to tell if we're close enough to one freq or another
105 uint32_t threshold = (sampleslo - sampleshi + 1)>>1;
106
107 // TI tags charge at 134.2Khz
108 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
109 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
110
111 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
112 // connects to SSP_DIN and the SSP_DOUT logic level controls
113 // whether we're modulating the antenna (high)
114 // or listening to the antenna (low)
115 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
116
117 // get TI tag data into the buffer
118 AcquireTiType();
119
120 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
121
122 for (i=0; i<n-1; i++) {
123 // count cycles by looking for lo to hi zero crossings
124 if ( (dest[i]<0) && (dest[i+1]>0) ) {
125 cycles++;
126 // after 16 cycles, measure the frequency
127 if (cycles>15) {
128 cycles=0;
129 samples=i-samples; // number of samples in these 16 cycles
130
131 // TI bits are coming to us lsb first so shift them
132 // right through our 128 bit right shift register
133 shift0 = (shift0>>1) | (shift1 << 31);
134 shift1 = (shift1>>1) | (shift2 << 31);
135 shift2 = (shift2>>1) | (shift3 << 31);
136 shift3 >>= 1;
137
138 // check if the cycles fall close to the number
139 // expected for either the low or high frequency
140 if ( (samples>(sampleslo-threshold)) && (samples<(sampleslo+threshold)) ) {
141 // low frequency represents a 1
142 shift3 |= (1<<31);
143 } else if ( (samples>(sampleshi-threshold)) && (samples<(sampleshi+threshold)) ) {
144 // high frequency represents a 0
145 } else {
146 // probably detected a gay waveform or noise
147 // use this as gaydar or discard shift register and start again
148 shift3 = shift2 = shift1 = shift0 = 0;
149 }
150 samples = i;
151
152 // for each bit we receive, test if we've detected a valid tag
153
154 // if we see 17 zeroes followed by 6 ones, we might have a tag
155 // remember the bits are backwards
156 if ( ((shift0 & 0x7fffff) == 0x7e0000) ) {
157 // if start and end bytes match, we have a tag so break out of the loop
158 if ( ((shift0>>16)&0xff) == ((shift3>>8)&0xff) ) {
159 cycles = 0xF0B; //use this as a flag (ugly but whatever)
160 break;
161 }
162 }
163 }
164 }
165 }
166
167 // if flag is set we have a tag
168 if (cycles!=0xF0B) {
169 DbpString("Info: No valid tag detected.");
170 } else {
171 // put 64 bit data into shift1 and shift0
172 shift0 = (shift0>>24) | (shift1 << 8);
173 shift1 = (shift1>>24) | (shift2 << 8);
174
175 // align 16 bit crc into lower half of shift2
176 shift2 = ((shift2>>24) | (shift3 << 8)) & 0x0ffff;
177
178 // if r/w tag, check ident match
179 if (shift3 & (1<<15) ) {
180 DbpString("Info: TI tag is rewriteable");
181 // only 15 bits compare, last bit of ident is not valid
182 if (((shift3 >> 16) ^ shift0) & 0x7fff ) {
183 DbpString("Error: Ident mismatch!");
184 } else {
185 DbpString("Info: TI tag ident is valid");
186 }
187 } else {
188 DbpString("Info: TI tag is readonly");
189 }
190
191 // WARNING the order of the bytes in which we calc crc below needs checking
192 // i'm 99% sure the crc algorithm is correct, but it may need to eat the
193 // bytes in reverse or something
194 // calculate CRC
195 uint32_t crc=0;
196
197 crc = update_crc16(crc, (shift0)&0xff);
198 crc = update_crc16(crc, (shift0>>8)&0xff);
199 crc = update_crc16(crc, (shift0>>16)&0xff);
200 crc = update_crc16(crc, (shift0>>24)&0xff);
201 crc = update_crc16(crc, (shift1)&0xff);
202 crc = update_crc16(crc, (shift1>>8)&0xff);
203 crc = update_crc16(crc, (shift1>>16)&0xff);
204 crc = update_crc16(crc, (shift1>>24)&0xff);
205
206 Dbprintf("Info: Tag data: %x%08x, crc=%x",
207 (unsigned int)shift1, (unsigned int)shift0, (unsigned int)shift2 & 0xFFFF);
208 if (crc != (shift2&0xffff)) {
209 Dbprintf("Error: CRC mismatch, expected %x", (unsigned int)crc);
210 } else {
211 DbpString("Info: CRC is good");
212 }
213 }
214}
215
216void WriteTIbyte(uint8_t b)
217{
218 int i = 0;
219
220 // modulate 8 bits out to the antenna
221 for (i=0; i<8; i++)
222 {
223 if (b&(1<<i)) {
224 // stop modulating antenna
225 LOW(GPIO_SSC_DOUT);
226 SpinDelayUs(1000);
227 // modulate antenna
228 HIGH(GPIO_SSC_DOUT);
229 SpinDelayUs(1000);
230 } else {
231 // stop modulating antenna
232 LOW(GPIO_SSC_DOUT);
233 SpinDelayUs(300);
234 // modulate antenna
235 HIGH(GPIO_SSC_DOUT);
236 SpinDelayUs(1700);
237 }
238 }
239}
240
241void AcquireTiType(void)
242{
243 int i, j, n;
244 // tag transmission is <20ms, sampling at 2M gives us 40K samples max
245 // each sample is 1 bit stuffed into a uint32_t so we need 1250 uint32_t
246 #define TIBUFLEN 1250
247
248 // clear buffer
249 uint32_t *BigBuf = (uint32_t *)BigBuf_get_addr();
250 memset(BigBuf,0,BigBuf_max_traceLen()/sizeof(uint32_t));
251
252 // Set up the synchronous serial port
253 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DIN;
254 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN;
255
256 // steal this pin from the SSP and use it to control the modulation
257 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
258 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
259
260 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST;
261 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_RXEN | AT91C_SSC_TXEN;
262
263 // Sample at 2 Mbit/s, so TI tags are 16.2 vs. 14.9 clocks long
264 // 48/2 = 24 MHz clock must be divided by 12
265 AT91C_BASE_SSC->SSC_CMR = 12;
266
267 AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(0);
268 AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(32) | AT91C_SSC_MSBF;
269 AT91C_BASE_SSC->SSC_TCMR = 0;
270 AT91C_BASE_SSC->SSC_TFMR = 0;
271
272 LED_D_ON();
273
274 // modulate antenna
275 HIGH(GPIO_SSC_DOUT);
276
277 // Charge TI tag for 50ms.
278 SpinDelay(50);
279
280 // stop modulating antenna and listen
281 LOW(GPIO_SSC_DOUT);
282
283 LED_D_OFF();
284
285 i = 0;
286 for(;;) {
287 if(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
288 BigBuf[i] = AT91C_BASE_SSC->SSC_RHR; // store 32 bit values in buffer
289 i++; if(i >= TIBUFLEN) break;
290 }
291 WDT_HIT();
292 }
293
294 // return stolen pin to SSP
295 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT;
296 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN | GPIO_SSC_DOUT;
297
298 char *dest = (char *)BigBuf_get_addr();
299 n = TIBUFLEN*32;
300 // unpack buffer
301 for (i=TIBUFLEN-1; i>=0; i--) {
302 for (j=0; j<32; j++) {
303 if(BigBuf[i] & (1 << j)) {
304 dest[--n] = 1;
305 } else {
306 dest[--n] = -1;
307 }
308 }
309 }
310}
311
312// arguments: 64bit data split into 32bit idhi:idlo and optional 16bit crc
313// if crc provided, it will be written with the data verbatim (even if bogus)
314// if not provided a valid crc will be computed from the data and written.
315void WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc)
316{
317 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
318 if(crc == 0) {
319 crc = update_crc16(crc, (idlo)&0xff);
320 crc = update_crc16(crc, (idlo>>8)&0xff);
321 crc = update_crc16(crc, (idlo>>16)&0xff);
322 crc = update_crc16(crc, (idlo>>24)&0xff);
323 crc = update_crc16(crc, (idhi)&0xff);
324 crc = update_crc16(crc, (idhi>>8)&0xff);
325 crc = update_crc16(crc, (idhi>>16)&0xff);
326 crc = update_crc16(crc, (idhi>>24)&0xff);
327 }
328 Dbprintf("Writing to tag: %x%08x, crc=%x",
329 (unsigned int) idhi, (unsigned int) idlo, crc);
330
331 // TI tags charge at 134.2Khz
332 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
333 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
334 // connects to SSP_DIN and the SSP_DOUT logic level controls
335 // whether we're modulating the antenna (high)
336 // or listening to the antenna (low)
337 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
338 LED_A_ON();
339
340 // steal this pin from the SSP and use it to control the modulation
341 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
342 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
343
344 // writing algorithm:
345 // a high bit consists of a field off for 1ms and field on for 1ms
346 // a low bit consists of a field off for 0.3ms and field on for 1.7ms
347 // initiate a charge time of 50ms (field on) then immediately start writing bits
348 // start by writing 0xBB (keyword) and 0xEB (password)
349 // then write 80 bits of data (or 64 bit data + 16 bit crc if you prefer)
350 // finally end with 0x0300 (write frame)
351 // all data is sent lsb firts
352 // finish with 15ms programming time
353
354 // modulate antenna
355 HIGH(GPIO_SSC_DOUT);
356 SpinDelay(50); // charge time
357
358 WriteTIbyte(0xbb); // keyword
359 WriteTIbyte(0xeb); // password
360 WriteTIbyte( (idlo )&0xff );
361 WriteTIbyte( (idlo>>8 )&0xff );
362 WriteTIbyte( (idlo>>16)&0xff );
363 WriteTIbyte( (idlo>>24)&0xff );
364 WriteTIbyte( (idhi )&0xff );
365 WriteTIbyte( (idhi>>8 )&0xff );
366 WriteTIbyte( (idhi>>16)&0xff );
367 WriteTIbyte( (idhi>>24)&0xff ); // data hi to lo
368 WriteTIbyte( (crc )&0xff ); // crc lo
369 WriteTIbyte( (crc>>8 )&0xff ); // crc hi
370 WriteTIbyte(0x00); // write frame lo
371 WriteTIbyte(0x03); // write frame hi
372 HIGH(GPIO_SSC_DOUT);
373 SpinDelay(50); // programming time
374
375 LED_A_OFF();
376
377 // get TI tag data into the buffer
378 AcquireTiType();
379
380 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
381 DbpString("Now use tiread to check");
382}
383
384void SimulateTagLowFrequency(int period, int gap, int ledcontrol)
385{
386 int i;
387 uint8_t *tab = BigBuf_get_addr();
388
389 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
390 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT);
391
392 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK;
393
394 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
395 AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK;
396
397 #define SHORT_COIL() LOW(GPIO_SSC_DOUT)
398 #define OPEN_COIL() HIGH(GPIO_SSC_DOUT)
399
400 i = 0;
401 for(;;) {
402 //wait until SSC_CLK goes HIGH
403 while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) {
404 if(BUTTON_PRESS()) {
405 DbpString("Stopped");
406 return;
407 }
408 WDT_HIT();
409 }
410 if (ledcontrol)
411 LED_D_ON();
412
413 if(tab[i])
414 OPEN_COIL();
415 else
416 SHORT_COIL();
417
418 if (ledcontrol)
419 LED_D_OFF();
420 //wait until SSC_CLK goes LOW
421 while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) {
422 if(BUTTON_PRESS()) {
423 DbpString("Stopped");
424 return;
425 }
426 WDT_HIT();
427 }
428
429 i++;
430 if(i == period) {
431
432 i = 0;
433 if (gap) {
434 SHORT_COIL();
435 SpinDelayUs(gap);
436 }
437 }
438 }
439}
440
e09f21fa 441#define DEBUG_FRAME_CONTENTS 1
442void SimulateTagLowFrequencyBidir(int divisor, int t0)
443{
444}
445
446// compose fc/8 fc/10 waveform (FSK2)
447static void fc(int c, int *n)
448{
449 uint8_t *dest = BigBuf_get_addr();
450 int idx;
451
452 // for when we want an fc8 pattern every 4 logical bits
453 if(c==0) {
454 dest[((*n)++)]=1;
455 dest[((*n)++)]=1;
456 dest[((*n)++)]=1;
457 dest[((*n)++)]=1;
458 dest[((*n)++)]=0;
459 dest[((*n)++)]=0;
460 dest[((*n)++)]=0;
461 dest[((*n)++)]=0;
462 }
463
464 // an fc/8 encoded bit is a bit pattern of 11000000 x6 = 48 samples
465 if(c==8) {
466 for (idx=0; idx<6; idx++) {
467 dest[((*n)++)]=1;
468 dest[((*n)++)]=1;
469 dest[((*n)++)]=1;
470 dest[((*n)++)]=1;
471 dest[((*n)++)]=0;
472 dest[((*n)++)]=0;
473 dest[((*n)++)]=0;
474 dest[((*n)++)]=0;
475 }
476 }
477
478 // an fc/10 encoded bit is a bit pattern of 1110000000 x5 = 50 samples
479 if(c==10) {
480 for (idx=0; idx<5; idx++) {
481 dest[((*n)++)]=1;
482 dest[((*n)++)]=1;
483 dest[((*n)++)]=1;
484 dest[((*n)++)]=1;
485 dest[((*n)++)]=1;
486 dest[((*n)++)]=0;
487 dest[((*n)++)]=0;
488 dest[((*n)++)]=0;
489 dest[((*n)++)]=0;
490 dest[((*n)++)]=0;
491 }
492 }
493}
494// compose fc/X fc/Y waveform (FSKx)
495static void fcAll(uint8_t c, int *n, uint8_t clock, uint16_t *modCnt)
496{
497 uint8_t *dest = BigBuf_get_addr();
498 uint8_t idx;
499 uint8_t fcCnt;
500 // c = count of field clock for this bit
501 uint8_t mod = clock % c;
502 uint8_t modAdj = c/mod;
503 bool modAdjOk=FALSE;
504 if (c % mod==0) modAdjOk=TRUE;
505 // loop through clock - step field clock
506 for (idx=0; idx < (uint8_t) clock/c; idx++){
507 // loop through field clock length - put 1/2 FC length 1's and 1/2 0's per field clock wave (to create the wave)
508 for (fcCnt=0; fcCnt < c; fcCnt++){ //fudge slow transition from low to high - shorten wave by 1
78f5b1a7 509 if (fcCnt < c/2){
e09f21fa 510 dest[((*n)++)]=0;
511 } else {
512 //fudge low to high transition
513 //if (idx==clock/c && dest[*n-1]==1 && mod>0) dest[((*n++))]=0;
514 //if (c==8 && fcCnt==5) continue;
515 dest[((*n)++)]=1;
516 }
517 }
518 }
519 if (mod>0) (*modCnt)++;
520 if ((mod>0) && modAdjOk){ //fsk2
521 if ((*modCnt % modAdj) == 0){ //if 4th 8 length wave in a rf/50 add extra 8 length wave
522 for (fcCnt=0; fcCnt < c; fcCnt++){ //fudge slow transition from low to high - shorten wave by 1
78f5b1a7 523 if (fcCnt < c/2){
e09f21fa 524 dest[((*n)++)]=0;
525 } else {
526 //if (c==8 && fcCnt==5) continue;
527 dest[((*n)++)]=1;
528 }
529 }
530 }
531 }
532 //Dbprintf("mod: %d, modAdj %d, modc %d",mod, modAdj, c % mod);
533 if (mod>0 && !modAdjOk){ //fsk1
534 for (idx=0; idx < mod; idx++){
535 if (idx < mod/2) {
536 dest[((*n)++)]=0;
537 } else {
538 dest[((*n)++)]=1;
539 }
540 }
541 }
542}
543
544// prepare a waveform pattern in the buffer based on the ID given then
545// simulate a HID tag until the button is pressed
546void CmdHIDsimTAG(int hi, int lo, int ledcontrol)
547{
548 int n=0, i=0;
549 /*
550 HID tag bitstream format
551 The tag contains a 44bit unique code. This is sent out MSB first in sets of 4 bits
552 A 1 bit is represented as 6 fc8 and 5 fc10 patterns
553 A 0 bit is represented as 5 fc10 and 6 fc8 patterns
554 A fc8 is inserted before every 4 bits
555 A special start of frame pattern is used consisting a0b0 where a and b are neither 0
556 nor 1 bits, they are special patterns (a = set of 12 fc8 and b = set of 10 fc10)
557 */
558
559 if (hi>0xFFF) {
78f5b1a7 560 DbpString("Tags can only have 44 bits. - USE lf simfsk for larger tags");
e09f21fa 561 return;
562 }
563 fc(0,&n);
564 // special start of frame marker containing invalid bit sequences
565 fc(8, &n); fc(8, &n); // invalid
566 fc(8, &n); fc(10, &n); // logical 0
567 fc(10, &n); fc(10, &n); // invalid
568 fc(8, &n); fc(10, &n); // logical 0
569
570 WDT_HIT();
571 // manchester encode bits 43 to 32
572 for (i=11; i>=0; i--) {
573 if ((i%4)==3) fc(0,&n);
574 if ((hi>>i)&1) {
575 fc(10, &n); fc(8, &n); // low-high transition
576 } else {
577 fc(8, &n); fc(10, &n); // high-low transition
578 }
579 }
580
581 WDT_HIT();
582 // manchester encode bits 31 to 0
583 for (i=31; i>=0; i--) {
584 if ((i%4)==3) fc(0,&n);
585 if ((lo>>i)&1) {
586 fc(10, &n); fc(8, &n); // low-high transition
587 } else {
588 fc(8, &n); fc(10, &n); // high-low transition
589 }
590 }
591
592 if (ledcontrol)
593 LED_A_ON();
594 SimulateTagLowFrequency(n, 0, ledcontrol);
595
596 if (ledcontrol)
597 LED_A_OFF();
598}
599
600// prepare a waveform pattern in the buffer based on the ID given then
601// simulate a FSK tag until the button is pressed
602// arg1 contains fcHigh and fcLow, arg2 contains invert and clock
603void CmdFSKsimTAG(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
604{
605 int ledcontrol=1;
606 int n=0, i=0;
607 uint8_t fcHigh = arg1 >> 8;
608 uint8_t fcLow = arg1 & 0xFF;
609 uint16_t modCnt = 0;
610 //spacer bit
611 uint8_t clk = arg2 & 0xFF;
612 uint8_t invert = (arg2 >> 8) & 1;
613 //fcAll(0, &n, clk);
614
615 WDT_HIT();
616 for (i=0; i<size; i++){
617 if (BitStream[i] == invert){
618 fcAll(fcLow, &n, clk, &modCnt);
619 } else {
620 fcAll(fcHigh, &n, clk, &modCnt);
621 }
622 }
623 Dbprintf("Simulating with fcHigh: %d, fcLow: %d, clk: %d, invert: %d, n: %d",fcHigh, fcLow, clk, invert, n);
78f5b1a7 624 WDT_HIT();
625 /*Dbprintf("First 64:");
e09f21fa 626 uint8_t *dest = BigBuf_get_addr();
627 i=0;
628 Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
629 i+=16;
630 Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
631 i+=16;
632 Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
633 i+=16;
634 Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
635 i+=16;
636 Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
637 i+=16;
638 Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
639 i+=16;
640 Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
641 i+=16;
642 Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
643 i+=16;
644 Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
645 i+=16;
646 Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
647 i+=16;
648 Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
649 i+=16;
650 Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
651 i+=16;
652 Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
653 i+=16;
654 Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
655 i+=16;
656 Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
78f5b1a7 657 */
e09f21fa 658 if (ledcontrol)
659 LED_A_ON();
78f5b1a7 660 SimulateTagLowFrequency(n, 0, ledcontrol);
e09f21fa 661
662 if (ledcontrol)
663 LED_A_OFF();
664}
665
666// compose ask waveform for one bit(ASK)
667static void askSimBit(uint8_t c, int *n, uint8_t clock, uint8_t manchester)
668{
669 uint8_t *dest = BigBuf_get_addr();
670 uint8_t idx;
671 // c = current bit 1 or 0
672 int i = 0;
673 // for when we want a separator
674 if (c==2) { //separator
675 for (i=0; i<clock/2; i++){
676 dest[((*n)++)]=0;
677 }
678 } else {
679 if (manchester){
680 for (idx=0; idx < (uint8_t) clock/2; idx++){
681 dest[((*n)++)]=c;
682 }
683 for (idx=0; idx < (uint8_t) clock/2; idx++){
684 dest[((*n)++)]=c^1;
685 }
686 } else {
687 for (idx=0; idx < (uint8_t) clock; idx++){
688 dest[((*n)++)]=c;
689 }
690 }
691 }
692}
693
694// args clock, ask/man or askraw, invert, transmission separator
695void CmdASKsimTag(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
696{
697 int ledcontrol = 1;
698 int n=0, i=0;
699 uint8_t clk = (arg1 >> 8) & 0xFF;
700 uint8_t manchester = arg1 & 1;
701 uint8_t separator = arg2 & 1;
702 uint8_t invert = (arg2 >> 8) & 1;
e09f21fa 703 for (i=0; i<size; i++){
704 askSimBit(BitStream[i]^invert, &n, clk, manchester);
705 }
706 if (separator==1) Dbprintf("sorry but separator option not yet available"); //askSimBit(2, &n, clk, manchester);
707
708 Dbprintf("Simulating with clk: %d, invert: %d, manchester: %d, separator: %d, n: %d",clk, invert, manchester, separator, n);
709 //DEBUG
710 //Dbprintf("First 64:");
711 //uint8_t *dest = BigBuf_get_addr();
712 //i=0;
713 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
714 //i+=16;
715 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
716 //i+=16;
717 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
718 //i+=16;
719 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
720
721
722 if (ledcontrol)
723 LED_A_ON();
78f5b1a7 724 SimulateTagLowFrequency(n, 0, ledcontrol);
e09f21fa 725
726 if (ledcontrol)
727 LED_A_OFF();
728}
729
730//carrier can be 2,4 or 8
731static void pskSimBit(uint8_t waveLen, int *n, uint8_t clk, uint8_t *curPhase, bool phaseChg)
732{
733 uint8_t *dest = BigBuf_get_addr();
734 uint8_t idx;
735 int i = 0;
736 if (phaseChg){
737 // write phase change
78f5b1a7 738 for (idx=0; idx < waveLen/2; idx++){
e09f21fa 739 dest[((*n)++)] = *curPhase^1;
740 }
78f5b1a7 741 for (idx=0; idx < waveLen/2; idx++){
e09f21fa 742 dest[((*n)++)] = *curPhase;
743 }
744 *curPhase ^= 1;
78f5b1a7 745 i+=waveLen;
e09f21fa 746 }
747 //write each normal clock wave for the clock duration
748 for (; i < clk; i+=waveLen){
749 for (idx=0; idx<waveLen/2; idx++){
750 dest[((*n)++)] = *curPhase;
751 }
752 for (idx=0; idx<waveLen/2; idx++){
753 dest[((*n)++)] = *curPhase^1;
754 }
755 }
756}
757
758// args clock, carrier, invert,
759void CmdPSKsimTag(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
760{
761 int ledcontrol=1;
762 int n=0, i=0;
763 uint8_t clk = arg1 >> 8;
764 uint8_t carrier = arg1 & 0xFF;
765 uint8_t invert = arg2 & 0xFF;
766 //uint8_t phase = carrier/2; //extra phase changing bits = 1/2 a carrier wave to change the phase
767 //uint8_t invert = (arg2 >> 8) & 1;
e09f21fa 768 WDT_HIT();
78f5b1a7 769 uint8_t curPhase = 0;
e09f21fa 770 for (i=0; i<size; i++){
771 if (BitStream[i] == curPhase){
772 pskSimBit(carrier, &n, clk, &curPhase, FALSE);
773 } else {
774 pskSimBit(carrier, &n, clk, &curPhase, TRUE);
775 }
776 }
777 Dbprintf("Simulating with Carrier: %d, clk: %d, invert: %d, n: %d",carrier, clk, invert, n);
78f5b1a7 778 WDT_HIT();
e09f21fa 779 Dbprintf("First 128:");
780 uint8_t *dest = BigBuf_get_addr();
781 i=0;
782 Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
783 i+=16;
784 Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
785 i+=16;
786 Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
787 i+=16;
788 Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
789 i+=16;
790 Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
791 i+=16;
792 Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
793 i+=16;
794 Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
795 i+=16;
796 Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
797
798 if (ledcontrol)
799 LED_A_ON();
78f5b1a7 800 SimulateTagLowFrequency(n, 0, ledcontrol);
e09f21fa 801
802 if (ledcontrol)
803 LED_A_OFF();
804}
805
806// loop to get raw HID waveform then FSK demodulate the TAG ID from it
807void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
808{
809 uint8_t *dest = BigBuf_get_addr();
810 const size_t sizeOfBigBuff = BigBuf_max_traceLen();
811 size_t size = 0;
812 uint32_t hi2=0, hi=0, lo=0;
813 int idx=0;
814 // Configure to go in 125Khz listen mode
815 LFSetupFPGAForADC(95, true);
816
817 while(!BUTTON_PRESS()) {
818
819 WDT_HIT();
820 if (ledcontrol) LED_A_ON();
821
822 DoAcquisition_default(-1,true);
823 // FSK demodulator
824 size = sizeOfBigBuff; //variable size will change after demod so re initialize it before use
825 idx = HIDdemodFSK(dest, &size, &hi2, &hi, &lo);
826
827 if (idx>0 && lo>0){
828 // final loop, go over previously decoded manchester data and decode into usable tag ID
829 // 111000 bit pattern represent start of frame, 01 pattern represents a 1 and 10 represents a 0
830 if (hi2 != 0){ //extra large HID tags
831 Dbprintf("TAG ID: %x%08x%08x (%d)",
832 (unsigned int) hi2, (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
833 }else { //standard HID tags <38 bits
834 //Dbprintf("TAG ID: %x%08x (%d)",(unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF); //old print cmd
835 uint8_t bitlen = 0;
836 uint32_t fc = 0;
837 uint32_t cardnum = 0;
838 if (((hi>>5)&1) == 1){//if bit 38 is set then < 37 bit format is used
839 uint32_t lo2=0;
840 lo2=(((hi & 31) << 12) | (lo>>20)); //get bits 21-37 to check for format len bit
841 uint8_t idx3 = 1;
842 while(lo2 > 1){ //find last bit set to 1 (format len bit)
843 lo2=lo2 >> 1;
844 idx3++;
845 }
846 bitlen = idx3+19;
847 fc =0;
848 cardnum=0;
849 if(bitlen == 26){
850 cardnum = (lo>>1)&0xFFFF;
851 fc = (lo>>17)&0xFF;
852 }
853 if(bitlen == 37){
854 cardnum = (lo>>1)&0x7FFFF;
855 fc = ((hi&0xF)<<12)|(lo>>20);
856 }
857 if(bitlen == 34){
858 cardnum = (lo>>1)&0xFFFF;
859 fc= ((hi&1)<<15)|(lo>>17);
860 }
861 if(bitlen == 35){
862 cardnum = (lo>>1)&0xFFFFF;
863 fc = ((hi&1)<<11)|(lo>>21);
864 }
865 }
866 else { //if bit 38 is not set then 37 bit format is used
867 bitlen= 37;
868 fc =0;
869 cardnum=0;
870 if(bitlen==37){
871 cardnum = (lo>>1)&0x7FFFF;
872 fc = ((hi&0xF)<<12)|(lo>>20);
873 }
874 }
875 //Dbprintf("TAG ID: %x%08x (%d)",
876 // (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
877 Dbprintf("TAG ID: %x%08x (%d) - Format Len: %dbit - FC: %d - Card: %d",
878 (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF,
879 (unsigned int) bitlen, (unsigned int) fc, (unsigned int) cardnum);
880 }
881 if (findone){
882 if (ledcontrol) LED_A_OFF();
883 *high = hi;
884 *low = lo;
885 return;
886 }
887 // reset
888 hi2 = hi = lo = 0;
889 }
890 WDT_HIT();
891 }
892 DbpString("Stopped");
893 if (ledcontrol) LED_A_OFF();
894}
895
896void CmdEM410xdemod(int findone, int *high, int *low, int ledcontrol)
897{
898 uint8_t *dest = BigBuf_get_addr();
899
900 size_t size=0, idx=0;
901 int clk=0, invert=0, errCnt=0, maxErr=20;
902 uint64_t lo=0;
903 // Configure to go in 125Khz listen mode
904 LFSetupFPGAForADC(95, true);
905
906 while(!BUTTON_PRESS()) {
907
908 WDT_HIT();
909 if (ledcontrol) LED_A_ON();
910
911 DoAcquisition_default(-1,true);
912 size = BigBuf_max_traceLen();
913 //Dbprintf("DEBUG: Buffer got");
914 //askdemod and manchester decode
915 errCnt = askmandemod(dest, &size, &clk, &invert, maxErr);
916 //Dbprintf("DEBUG: ASK Got");
917 WDT_HIT();
918
919 if (errCnt>=0){
920 lo = Em410xDecode(dest, &size, &idx);
921 //Dbprintf("DEBUG: EM GOT");
922 if (lo>0){
923 Dbprintf("EM TAG ID: %02x%08x - (%05d_%03d_%08d)",
924 (uint32_t)(lo>>32),
925 (uint32_t)lo,
926 (uint32_t)(lo&0xFFFF),
927 (uint32_t)((lo>>16LL) & 0xFF),
928 (uint32_t)(lo & 0xFFFFFF));
929 }
930 if (findone){
931 if (ledcontrol) LED_A_OFF();
932 *high=lo>>32;
933 *low=lo & 0xFFFFFFFF;
934 return;
935 }
936 } else{
937 //Dbprintf("DEBUG: No Tag");
938 }
939 WDT_HIT();
940 lo = 0;
941 clk=0;
942 invert=0;
943 errCnt=0;
944 size=0;
945 }
946 DbpString("Stopped");
947 if (ledcontrol) LED_A_OFF();
948}
949
950void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
951{
952 uint8_t *dest = BigBuf_get_addr();
953 int idx=0;
954 uint32_t code=0, code2=0;
955 uint8_t version=0;
956 uint8_t facilitycode=0;
957 uint16_t number=0;
958 // Configure to go in 125Khz listen mode
959 LFSetupFPGAForADC(95, true);
960
961 while(!BUTTON_PRESS()) {
962 WDT_HIT();
963 if (ledcontrol) LED_A_ON();
964 DoAcquisition_default(-1,true);
965 //fskdemod and get start index
966 WDT_HIT();
967 idx = IOdemodFSK(dest, BigBuf_max_traceLen());
968 if (idx>0){
969 //valid tag found
970
971 //Index map
972 //0 10 20 30 40 50 60
973 //| | | | | | |
974 //01234567 8 90123456 7 89012345 6 78901234 5 67890123 4 56789012 3 45678901 23
975 //-----------------------------------------------------------------------------
976 //00000000 0 11110000 1 facility 1 version* 1 code*one 1 code*two 1 ???????? 11
977 //
978 //XSF(version)facility:codeone+codetwo
979 //Handle the data
980 if(findone){ //only print binary if we are doing one
981 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx], dest[idx+1], dest[idx+2],dest[idx+3],dest[idx+4],dest[idx+5],dest[idx+6],dest[idx+7],dest[idx+8]);
982 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+9], dest[idx+10],dest[idx+11],dest[idx+12],dest[idx+13],dest[idx+14],dest[idx+15],dest[idx+16],dest[idx+17]);
983 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+18],dest[idx+19],dest[idx+20],dest[idx+21],dest[idx+22],dest[idx+23],dest[idx+24],dest[idx+25],dest[idx+26]);
984 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+27],dest[idx+28],dest[idx+29],dest[idx+30],dest[idx+31],dest[idx+32],dest[idx+33],dest[idx+34],dest[idx+35]);
985 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+36],dest[idx+37],dest[idx+38],dest[idx+39],dest[idx+40],dest[idx+41],dest[idx+42],dest[idx+43],dest[idx+44]);
986 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+45],dest[idx+46],dest[idx+47],dest[idx+48],dest[idx+49],dest[idx+50],dest[idx+51],dest[idx+52],dest[idx+53]);
987 Dbprintf("%d%d%d%d%d%d%d%d %d%d",dest[idx+54],dest[idx+55],dest[idx+56],dest[idx+57],dest[idx+58],dest[idx+59],dest[idx+60],dest[idx+61],dest[idx+62],dest[idx+63]);
988 }
989 code = bytebits_to_byte(dest+idx,32);
990 code2 = bytebits_to_byte(dest+idx+32,32);
991 version = bytebits_to_byte(dest+idx+27,8); //14,4
992 facilitycode = bytebits_to_byte(dest+idx+18,8) ;
993 number = (bytebits_to_byte(dest+idx+36,8)<<8)|(bytebits_to_byte(dest+idx+45,8)); //36,9
994
995 Dbprintf("XSF(%02d)%02x:%05d (%08x%08x)",version,facilitycode,number,code,code2);
996 // if we're only looking for one tag
997 if (findone){
998 if (ledcontrol) LED_A_OFF();
999 //LED_A_OFF();
1000 *high=code;
1001 *low=code2;
1002 return;
1003 }
1004 code=code2=0;
1005 version=facilitycode=0;
1006 number=0;
1007 idx=0;
1008 }
1009 WDT_HIT();
1010 }
1011 DbpString("Stopped");
1012 if (ledcontrol) LED_A_OFF();
1013}
1014
1015/*------------------------------
1016 * T5555/T5557/T5567 routines
1017 *------------------------------
1018 */
1019
1020/* T55x7 configuration register definitions */
1021#define T55x7_POR_DELAY 0x00000001
1022#define T55x7_ST_TERMINATOR 0x00000008
1023#define T55x7_PWD 0x00000010
1024#define T55x7_MAXBLOCK_SHIFT 5
1025#define T55x7_AOR 0x00000200
1026#define T55x7_PSKCF_RF_2 0
1027#define T55x7_PSKCF_RF_4 0x00000400
1028#define T55x7_PSKCF_RF_8 0x00000800
1029#define T55x7_MODULATION_DIRECT 0
1030#define T55x7_MODULATION_PSK1 0x00001000
1031#define T55x7_MODULATION_PSK2 0x00002000
1032#define T55x7_MODULATION_PSK3 0x00003000
1033#define T55x7_MODULATION_FSK1 0x00004000
1034#define T55x7_MODULATION_FSK2 0x00005000
1035#define T55x7_MODULATION_FSK1a 0x00006000
1036#define T55x7_MODULATION_FSK2a 0x00007000
1037#define T55x7_MODULATION_MANCHESTER 0x00008000
1038#define T55x7_MODULATION_BIPHASE 0x00010000
1039#define T55x7_BITRATE_RF_8 0
1040#define T55x7_BITRATE_RF_16 0x00040000
1041#define T55x7_BITRATE_RF_32 0x00080000
1042#define T55x7_BITRATE_RF_40 0x000C0000
1043#define T55x7_BITRATE_RF_50 0x00100000
1044#define T55x7_BITRATE_RF_64 0x00140000
1045#define T55x7_BITRATE_RF_100 0x00180000
1046#define T55x7_BITRATE_RF_128 0x001C0000
1047
1048/* T5555 (Q5) configuration register definitions */
1049#define T5555_ST_TERMINATOR 0x00000001
1050#define T5555_MAXBLOCK_SHIFT 0x00000001
1051#define T5555_MODULATION_MANCHESTER 0
1052#define T5555_MODULATION_PSK1 0x00000010
1053#define T5555_MODULATION_PSK2 0x00000020
1054#define T5555_MODULATION_PSK3 0x00000030
1055#define T5555_MODULATION_FSK1 0x00000040
1056#define T5555_MODULATION_FSK2 0x00000050
1057#define T5555_MODULATION_BIPHASE 0x00000060
1058#define T5555_MODULATION_DIRECT 0x00000070
1059#define T5555_INVERT_OUTPUT 0x00000080
1060#define T5555_PSK_RF_2 0
1061#define T5555_PSK_RF_4 0x00000100
1062#define T5555_PSK_RF_8 0x00000200
1063#define T5555_USE_PWD 0x00000400
1064#define T5555_USE_AOR 0x00000800
1065#define T5555_BITRATE_SHIFT 12
1066#define T5555_FAST_WRITE 0x00004000
1067#define T5555_PAGE_SELECT 0x00008000
1068
1069/*
1070 * Relevant times in microsecond
1071 * To compensate antenna falling times shorten the write times
1072 * and enlarge the gap ones.
1073 */
1074#define START_GAP 250
1075#define WRITE_GAP 160
1076#define WRITE_0 144 // 192
1077#define WRITE_1 400 // 432 for T55x7; 448 for E5550
1078
1079// Write one bit to card
1080void T55xxWriteBit(int bit)
1081{
1082 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1083 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1084 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1085 if (bit == 0)
1086 SpinDelayUs(WRITE_0);
1087 else
1088 SpinDelayUs(WRITE_1);
1089 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1090 SpinDelayUs(WRITE_GAP);
1091}
1092
1093// Write one card block in page 0, no lock
1094void T55xxWriteBlock(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
1095{
1096 //unsigned int i; //enio adjustment 12/10/14
1097 uint32_t i;
1098
1099 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1100 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1101 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1102
1103 // Give it a bit of time for the resonant antenna to settle.
1104 // And for the tag to fully power up
1105 SpinDelay(150);
1106
1107 // Now start writting
1108 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1109 SpinDelayUs(START_GAP);
1110
1111 // Opcode
1112 T55xxWriteBit(1);
1113 T55xxWriteBit(0); //Page 0
1114 if (PwdMode == 1){
1115 // Pwd
1116 for (i = 0x80000000; i != 0; i >>= 1)
1117 T55xxWriteBit(Pwd & i);
1118 }
1119 // Lock bit
1120 T55xxWriteBit(0);
1121
1122 // Data
1123 for (i = 0x80000000; i != 0; i >>= 1)
1124 T55xxWriteBit(Data & i);
1125
1126 // Block
1127 for (i = 0x04; i != 0; i >>= 1)
1128 T55xxWriteBit(Block & i);
1129
1130 // Now perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550,
1131 // so wait a little more)
1132 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1133 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1134 SpinDelay(20);
1135 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1136}
1137
1138// Read one card block in page 0
1139void T55xxReadBlock(uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
1140{
1141 uint8_t *dest = BigBuf_get_addr();
1142 //int m=0, i=0; //enio adjustment 12/10/14
1143 uint32_t m=0, i=0;
1144 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1145 m = BigBuf_max_traceLen();
1146 // Clear destination buffer before sending the command
1147 memset(dest, 128, m);
1148 // Connect the A/D to the peak-detected low-frequency path.
1149 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1150 // Now set up the SSC to get the ADC samples that are now streaming at us.
1151 FpgaSetupSsc();
1152
1153 LED_D_ON();
1154 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1155 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1156
1157 // Give it a bit of time for the resonant antenna to settle.
1158 // And for the tag to fully power up
1159 SpinDelay(150);
1160
1161 // Now start writting
1162 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1163 SpinDelayUs(START_GAP);
1164
1165 // Opcode
1166 T55xxWriteBit(1);
1167 T55xxWriteBit(0); //Page 0
1168 if (PwdMode == 1){
1169 // Pwd
1170 for (i = 0x80000000; i != 0; i >>= 1)
1171 T55xxWriteBit(Pwd & i);
1172 }
1173 // Lock bit
1174 T55xxWriteBit(0);
1175 // Block
1176 for (i = 0x04; i != 0; i >>= 1)
1177 T55xxWriteBit(Block & i);
1178
1179 // Turn field on to read the response
1180 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1181 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1182
1183 // Now do the acquisition
1184 i = 0;
1185 for(;;) {
1186 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1187 AT91C_BASE_SSC->SSC_THR = 0x43;
1188 }
1189 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1190 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1191 // we don't care about actual value, only if it's more or less than a
1192 // threshold essentially we capture zero crossings for later analysis
1193 // if(dest[i] < 127) dest[i] = 0; else dest[i] = 1;
1194 i++;
1195 if (i >= m) break;
1196 }
1197 }
1198
1199 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1200 LED_D_OFF();
1201 DbpString("DONE!");
1202}
1203
1204// Read card traceability data (page 1)
1205void T55xxReadTrace(void){
1206 uint8_t *dest = BigBuf_get_addr();
1207 int m=0, i=0;
1208
1209 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1210 m = BigBuf_max_traceLen();
1211 // Clear destination buffer before sending the command
1212 memset(dest, 128, m);
1213 // Connect the A/D to the peak-detected low-frequency path.
1214 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1215 // Now set up the SSC to get the ADC samples that are now streaming at us.
1216 FpgaSetupSsc();
1217
1218 LED_D_ON();
1219 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1220 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1221
1222 // Give it a bit of time for the resonant antenna to settle.
1223 // And for the tag to fully power up
1224 SpinDelay(150);
1225
1226 // Now start writting
1227 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1228 SpinDelayUs(START_GAP);
1229
1230 // Opcode
1231 T55xxWriteBit(1);
1232 T55xxWriteBit(1); //Page 1
1233
1234 // Turn field on to read the response
1235 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1236 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1237
1238 // Now do the acquisition
1239 i = 0;
1240 for(;;) {
1241 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1242 AT91C_BASE_SSC->SSC_THR = 0x43;
1243 }
1244 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1245 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1246 i++;
1247 if (i >= m) break;
1248 }
1249 }
1250
1251 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1252 LED_D_OFF();
1253 DbpString("DONE!");
1254}
1255
1256/*-------------- Cloning routines -----------*/
1257// Copy HID id to card and setup block 0 config
1258void CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT)
1259{
1260 int data1=0, data2=0, data3=0, data4=0, data5=0, data6=0; //up to six blocks for long format
1261 int last_block = 0;
1262
1263 if (longFMT){
1264 // Ensure no more than 84 bits supplied
1265 if (hi2>0xFFFFF) {
1266 DbpString("Tags can only have 84 bits.");
1267 return;
1268 }
1269 // Build the 6 data blocks for supplied 84bit ID
1270 last_block = 6;
1271 data1 = 0x1D96A900; // load preamble (1D) & long format identifier (9E manchester encoded)
1272 for (int i=0;i<4;i++) {
1273 if (hi2 & (1<<(19-i)))
1274 data1 |= (1<<(((3-i)*2)+1)); // 1 -> 10
1275 else
1276 data1 |= (1<<((3-i)*2)); // 0 -> 01
1277 }
1278
1279 data2 = 0;
1280 for (int i=0;i<16;i++) {
1281 if (hi2 & (1<<(15-i)))
1282 data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1283 else
1284 data2 |= (1<<((15-i)*2)); // 0 -> 01
1285 }
1286
1287 data3 = 0;
1288 for (int i=0;i<16;i++) {
1289 if (hi & (1<<(31-i)))
1290 data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1291 else
1292 data3 |= (1<<((15-i)*2)); // 0 -> 01
1293 }
1294
1295 data4 = 0;
1296 for (int i=0;i<16;i++) {
1297 if (hi & (1<<(15-i)))
1298 data4 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1299 else
1300 data4 |= (1<<((15-i)*2)); // 0 -> 01
1301 }
1302
1303 data5 = 0;
1304 for (int i=0;i<16;i++) {
1305 if (lo & (1<<(31-i)))
1306 data5 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1307 else
1308 data5 |= (1<<((15-i)*2)); // 0 -> 01
1309 }
1310
1311 data6 = 0;
1312 for (int i=0;i<16;i++) {
1313 if (lo & (1<<(15-i)))
1314 data6 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1315 else
1316 data6 |= (1<<((15-i)*2)); // 0 -> 01
1317 }
1318 }
1319 else {
1320 // Ensure no more than 44 bits supplied
1321 if (hi>0xFFF) {
1322 DbpString("Tags can only have 44 bits.");
1323 return;
1324 }
1325
1326 // Build the 3 data blocks for supplied 44bit ID
1327 last_block = 3;
1328
1329 data1 = 0x1D000000; // load preamble
1330
1331 for (int i=0;i<12;i++) {
1332 if (hi & (1<<(11-i)))
1333 data1 |= (1<<(((11-i)*2)+1)); // 1 -> 10
1334 else
1335 data1 |= (1<<((11-i)*2)); // 0 -> 01
1336 }
1337
1338 data2 = 0;
1339 for (int i=0;i<16;i++) {
1340 if (lo & (1<<(31-i)))
1341 data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1342 else
1343 data2 |= (1<<((15-i)*2)); // 0 -> 01
1344 }
1345
1346 data3 = 0;
1347 for (int i=0;i<16;i++) {
1348 if (lo & (1<<(15-i)))
1349 data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1350 else
1351 data3 |= (1<<((15-i)*2)); // 0 -> 01
1352 }
1353 }
1354
1355 LED_D_ON();
1356 // Program the data blocks for supplied ID
1357 // and the block 0 for HID format
1358 T55xxWriteBlock(data1,1,0,0);
1359 T55xxWriteBlock(data2,2,0,0);
1360 T55xxWriteBlock(data3,3,0,0);
1361
1362 if (longFMT) { // if long format there are 6 blocks
1363 T55xxWriteBlock(data4,4,0,0);
1364 T55xxWriteBlock(data5,5,0,0);
1365 T55xxWriteBlock(data6,6,0,0);
1366 }
1367
1368 // Config for HID (RF/50, FSK2a, Maxblock=3 for short/6 for long)
1369 T55xxWriteBlock(T55x7_BITRATE_RF_50 |
1370 T55x7_MODULATION_FSK2a |
1371 last_block << T55x7_MAXBLOCK_SHIFT,
1372 0,0,0);
1373
1374 LED_D_OFF();
1375
1376 DbpString("DONE!");
1377}
1378
1379void CopyIOtoT55x7(uint32_t hi, uint32_t lo, uint8_t longFMT)
1380{
1381 int data1=0, data2=0; //up to six blocks for long format
1382
1383 data1 = hi; // load preamble
1384 data2 = lo;
1385
1386 LED_D_ON();
1387 // Program the data blocks for supplied ID
1388 // and the block 0 for HID format
1389 T55xxWriteBlock(data1,1,0,0);
1390 T55xxWriteBlock(data2,2,0,0);
1391
1392 //Config Block
1393 T55xxWriteBlock(0x00147040,0,0,0);
1394 LED_D_OFF();
1395
1396 DbpString("DONE!");
1397}
1398
1399// Define 9bit header for EM410x tags
1400#define EM410X_HEADER 0x1FF
1401#define EM410X_ID_LENGTH 40
1402
1403void WriteEM410x(uint32_t card, uint32_t id_hi, uint32_t id_lo)
1404{
1405 int i, id_bit;
1406 uint64_t id = EM410X_HEADER;
1407 uint64_t rev_id = 0; // reversed ID
1408 int c_parity[4]; // column parity
1409 int r_parity = 0; // row parity
1410 uint32_t clock = 0;
1411
1412 // Reverse ID bits given as parameter (for simpler operations)
1413 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1414 if (i < 32) {
1415 rev_id = (rev_id << 1) | (id_lo & 1);
1416 id_lo >>= 1;
1417 } else {
1418 rev_id = (rev_id << 1) | (id_hi & 1);
1419 id_hi >>= 1;
1420 }
1421 }
1422
1423 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1424 id_bit = rev_id & 1;
1425
1426 if (i % 4 == 0) {
1427 // Don't write row parity bit at start of parsing
1428 if (i)
1429 id = (id << 1) | r_parity;
1430 // Start counting parity for new row
1431 r_parity = id_bit;
1432 } else {
1433 // Count row parity
1434 r_parity ^= id_bit;
1435 }
1436
1437 // First elements in column?
1438 if (i < 4)
1439 // Fill out first elements
1440 c_parity[i] = id_bit;
1441 else
1442 // Count column parity
1443 c_parity[i % 4] ^= id_bit;
1444
1445 // Insert ID bit
1446 id = (id << 1) | id_bit;
1447 rev_id >>= 1;
1448 }
1449
1450 // Insert parity bit of last row
1451 id = (id << 1) | r_parity;
1452
1453 // Fill out column parity at the end of tag
1454 for (i = 0; i < 4; ++i)
1455 id = (id << 1) | c_parity[i];
1456
1457 // Add stop bit
1458 id <<= 1;
1459
1460 Dbprintf("Started writing %s tag ...", card ? "T55x7":"T5555");
1461 LED_D_ON();
1462
1463 // Write EM410x ID
1464 T55xxWriteBlock((uint32_t)(id >> 32), 1, 0, 0);
1465 T55xxWriteBlock((uint32_t)id, 2, 0, 0);
1466
1467 // Config for EM410x (RF/64, Manchester, Maxblock=2)
1468 if (card) {
1469 // Clock rate is stored in bits 8-15 of the card value
1470 clock = (card & 0xFF00) >> 8;
1471 Dbprintf("Clock rate: %d", clock);
1472 switch (clock)
1473 {
1474 case 32:
1475 clock = T55x7_BITRATE_RF_32;
1476 break;
1477 case 16:
1478 clock = T55x7_BITRATE_RF_16;
1479 break;
1480 case 0:
1481 // A value of 0 is assumed to be 64 for backwards-compatibility
1482 // Fall through...
1483 case 64:
1484 clock = T55x7_BITRATE_RF_64;
1485 break;
1486 default:
1487 Dbprintf("Invalid clock rate: %d", clock);
1488 return;
1489 }
1490
1491 // Writing configuration for T55x7 tag
1492 T55xxWriteBlock(clock |
1493 T55x7_MODULATION_MANCHESTER |
1494 2 << T55x7_MAXBLOCK_SHIFT,
1495 0, 0, 0);
1496 }
1497 else
1498 // Writing configuration for T5555(Q5) tag
1499 T55xxWriteBlock(0x1F << T5555_BITRATE_SHIFT |
1500 T5555_MODULATION_MANCHESTER |
1501 2 << T5555_MAXBLOCK_SHIFT,
1502 0, 0, 0);
1503
1504 LED_D_OFF();
1505 Dbprintf("Tag %s written with 0x%08x%08x\n", card ? "T55x7":"T5555",
1506 (uint32_t)(id >> 32), (uint32_t)id);
1507}
1508
1509// Clone Indala 64-bit tag by UID to T55x7
1510void CopyIndala64toT55x7(int hi, int lo)
1511{
1512
1513 //Program the 2 data blocks for supplied 64bit UID
1514 // and the block 0 for Indala64 format
1515 T55xxWriteBlock(hi,1,0,0);
1516 T55xxWriteBlock(lo,2,0,0);
1517 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=2)
1518 T55xxWriteBlock(T55x7_BITRATE_RF_32 |
1519 T55x7_MODULATION_PSK1 |
1520 2 << T55x7_MAXBLOCK_SHIFT,
1521 0, 0, 0);
1522 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=2;Inverse data)
1523 // T5567WriteBlock(0x603E1042,0);
1524
1525 DbpString("DONE!");
1526
1527}
1528
1529void CopyIndala224toT55x7(int uid1, int uid2, int uid3, int uid4, int uid5, int uid6, int uid7)
1530{
1531
1532 //Program the 7 data blocks for supplied 224bit UID
1533 // and the block 0 for Indala224 format
1534 T55xxWriteBlock(uid1,1,0,0);
1535 T55xxWriteBlock(uid2,2,0,0);
1536 T55xxWriteBlock(uid3,3,0,0);
1537 T55xxWriteBlock(uid4,4,0,0);
1538 T55xxWriteBlock(uid5,5,0,0);
1539 T55xxWriteBlock(uid6,6,0,0);
1540 T55xxWriteBlock(uid7,7,0,0);
1541 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=7)
1542 T55xxWriteBlock(T55x7_BITRATE_RF_32 |
1543 T55x7_MODULATION_PSK1 |
1544 7 << T55x7_MAXBLOCK_SHIFT,
1545 0,0,0);
1546 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=7;Inverse data)
1547 // T5567WriteBlock(0x603E10E2,0);
1548
1549 DbpString("DONE!");
1550
1551}
1552
1553
1554#define abs(x) ( ((x)<0) ? -(x) : (x) )
1555#define max(x,y) ( x<y ? y:x)
1556
1557int DemodPCF7931(uint8_t **outBlocks) {
1558 uint8_t BitStream[256];
1559 uint8_t Blocks[8][16];
1560 uint8_t *GraphBuffer = BigBuf_get_addr();
1561 int GraphTraceLen = BigBuf_max_traceLen();
1562 int i, j, lastval, bitidx, half_switch;
1563 int clock = 64;
1564 int tolerance = clock / 8;
1565 int pmc, block_done;
1566 int lc, warnings = 0;
1567 int num_blocks = 0;
1568 int lmin=128, lmax=128;
1569 uint8_t dir;
1570
1571 LFSetupFPGAForADC(95, true);
1572 DoAcquisition_default(0, 0);
1573
1574
1575 lmin = 64;
1576 lmax = 192;
1577
1578 i = 2;
1579
1580 /* Find first local max/min */
1581 if(GraphBuffer[1] > GraphBuffer[0]) {
1582 while(i < GraphTraceLen) {
1583 if( !(GraphBuffer[i] > GraphBuffer[i-1]) && GraphBuffer[i] > lmax)
1584 break;
1585 i++;
1586 }
1587 dir = 0;
1588 }
1589 else {
1590 while(i < GraphTraceLen) {
1591 if( !(GraphBuffer[i] < GraphBuffer[i-1]) && GraphBuffer[i] < lmin)
1592 break;
1593 i++;
1594 }
1595 dir = 1;
1596 }
1597
1598 lastval = i++;
1599 half_switch = 0;
1600 pmc = 0;
1601 block_done = 0;
1602
1603 for (bitidx = 0; i < GraphTraceLen; i++)
1604 {
1605 if ( (GraphBuffer[i-1] > GraphBuffer[i] && dir == 1 && GraphBuffer[i] > lmax) || (GraphBuffer[i-1] < GraphBuffer[i] && dir == 0 && GraphBuffer[i] < lmin))
1606 {
1607 lc = i - lastval;
1608 lastval = i;
1609
1610 // Switch depending on lc length:
1611 // Tolerance is 1/8 of clock rate (arbitrary)
1612 if (abs(lc-clock/4) < tolerance) {
1613 // 16T0
1614 if((i - pmc) == lc) { /* 16T0 was previous one */
1615 /* It's a PMC ! */
1616 i += (128+127+16+32+33+16)-1;
1617 lastval = i;
1618 pmc = 0;
1619 block_done = 1;
1620 }
1621 else {
1622 pmc = i;
1623 }
1624 } else if (abs(lc-clock/2) < tolerance) {
1625 // 32TO
1626 if((i - pmc) == lc) { /* 16T0 was previous one */
1627 /* It's a PMC ! */
1628 i += (128+127+16+32+33)-1;
1629 lastval = i;
1630 pmc = 0;
1631 block_done = 1;
1632 }
1633 else if(half_switch == 1) {
1634 BitStream[bitidx++] = 0;
1635 half_switch = 0;
1636 }
1637 else
1638 half_switch++;
1639 } else if (abs(lc-clock) < tolerance) {
1640 // 64TO
1641 BitStream[bitidx++] = 1;
1642 } else {
1643 // Error
1644 warnings++;
1645 if (warnings > 10)
1646 {
1647 Dbprintf("Error: too many detection errors, aborting.");
1648 return 0;
1649 }
1650 }
1651
1652 if(block_done == 1) {
1653 if(bitidx == 128) {
1654 for(j=0; j<16; j++) {
1655 Blocks[num_blocks][j] = 128*BitStream[j*8+7]+
1656 64*BitStream[j*8+6]+
1657 32*BitStream[j*8+5]+
1658 16*BitStream[j*8+4]+
1659 8*BitStream[j*8+3]+
1660 4*BitStream[j*8+2]+
1661 2*BitStream[j*8+1]+
1662 BitStream[j*8];
1663 }
1664 num_blocks++;
1665 }
1666 bitidx = 0;
1667 block_done = 0;
1668 half_switch = 0;
1669 }
1670 if(i < GraphTraceLen)
1671 {
1672 if (GraphBuffer[i-1] > GraphBuffer[i]) dir=0;
1673 else dir = 1;
1674 }
1675 }
1676 if(bitidx==255)
1677 bitidx=0;
1678 warnings = 0;
1679 if(num_blocks == 4) break;
1680 }
1681 memcpy(outBlocks, Blocks, 16*num_blocks);
1682 return num_blocks;
1683}
1684
1685int IsBlock0PCF7931(uint8_t *Block) {
1686 // Assume RFU means 0 :)
1687 if((memcmp(Block, "\x00\x00\x00\x00\x00\x00\x00\x01", 8) == 0) && memcmp(Block+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) // PAC enabled
1688 return 1;
1689 if((memcmp(Block+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) && Block[7] == 0) // PAC disabled, can it *really* happen ?
1690 return 1;
1691 return 0;
1692}
1693
1694int IsBlock1PCF7931(uint8_t *Block) {
1695 // Assume RFU means 0 :)
1696 if(Block[10] == 0 && Block[11] == 0 && Block[12] == 0 && Block[13] == 0)
1697 if((Block[14] & 0x7f) <= 9 && Block[15] <= 9)
1698 return 1;
1699
1700 return 0;
1701}
1702
1703#define ALLOC 16
1704
1705void ReadPCF7931() {
1706 uint8_t Blocks[8][17];
1707 uint8_t tmpBlocks[4][16];
1708 int i, j, ind, ind2, n;
1709 int num_blocks = 0;
1710 int max_blocks = 8;
1711 int ident = 0;
1712 int error = 0;
1713 int tries = 0;
1714
1715 memset(Blocks, 0, 8*17*sizeof(uint8_t));
1716
1717 do {
1718 memset(tmpBlocks, 0, 4*16*sizeof(uint8_t));
1719 n = DemodPCF7931((uint8_t**)tmpBlocks);
1720 if(!n)
1721 error++;
1722 if(error==10 && num_blocks == 0) {
1723 Dbprintf("Error, no tag or bad tag");
1724 return;
1725 }
1726 else if (tries==20 || error==10) {
1727 Dbprintf("Error reading the tag");
1728 Dbprintf("Here is the partial content");
1729 goto end;
1730 }
1731
1732 for(i=0; i<n; i++)
1733 Dbprintf("(dbg) %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
1734 tmpBlocks[i][0], tmpBlocks[i][1], tmpBlocks[i][2], tmpBlocks[i][3], tmpBlocks[i][4], tmpBlocks[i][5], tmpBlocks[i][6], tmpBlocks[i][7],
1735 tmpBlocks[i][8], tmpBlocks[i][9], tmpBlocks[i][10], tmpBlocks[i][11], tmpBlocks[i][12], tmpBlocks[i][13], tmpBlocks[i][14], tmpBlocks[i][15]);
1736 if(!ident) {
1737 for(i=0; i<n; i++) {
1738 if(IsBlock0PCF7931(tmpBlocks[i])) {
1739 // Found block 0 ?
1740 if(i < n-1 && IsBlock1PCF7931(tmpBlocks[i+1])) {
1741 // Found block 1!
1742 // \o/
1743 ident = 1;
1744 memcpy(Blocks[0], tmpBlocks[i], 16);
1745 Blocks[0][ALLOC] = 1;
1746 memcpy(Blocks[1], tmpBlocks[i+1], 16);
1747 Blocks[1][ALLOC] = 1;
1748 max_blocks = max((Blocks[1][14] & 0x7f), Blocks[1][15]) + 1;
1749 // Debug print
1750 Dbprintf("(dbg) Max blocks: %d", max_blocks);
1751 num_blocks = 2;
1752 // Handle following blocks
1753 for(j=i+2, ind2=2; j!=i; j++, ind2++, num_blocks++) {
1754 if(j==n) j=0;
1755 if(j==i) break;
1756 memcpy(Blocks[ind2], tmpBlocks[j], 16);
1757 Blocks[ind2][ALLOC] = 1;
1758 }
1759 break;
1760 }
1761 }
1762 }
1763 }
1764 else {
1765 for(i=0; i<n; i++) { // Look for identical block in known blocks
1766 if(memcmp(tmpBlocks[i], "\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00", 16)) { // Block is not full of 00
1767 for(j=0; j<max_blocks; j++) {
1768 if(Blocks[j][ALLOC] == 1 && !memcmp(tmpBlocks[i], Blocks[j], 16)) {
1769 // Found an identical block
1770 for(ind=i-1,ind2=j-1; ind >= 0; ind--,ind2--) {
1771 if(ind2 < 0)
1772 ind2 = max_blocks;
1773 if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found
1774 // Dbprintf("Tmp %d -> Block %d", ind, ind2);
1775 memcpy(Blocks[ind2], tmpBlocks[ind], 16);
1776 Blocks[ind2][ALLOC] = 1;
1777 num_blocks++;
1778 if(num_blocks == max_blocks) goto end;
1779 }
1780 }
1781 for(ind=i+1,ind2=j+1; ind < n; ind++,ind2++) {
1782 if(ind2 > max_blocks)
1783 ind2 = 0;
1784 if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found
1785 // Dbprintf("Tmp %d -> Block %d", ind, ind2);
1786 memcpy(Blocks[ind2], tmpBlocks[ind], 16);
1787 Blocks[ind2][ALLOC] = 1;
1788 num_blocks++;
1789 if(num_blocks == max_blocks) goto end;
1790 }
1791 }
1792 }
1793 }
1794 }
1795 }
1796 }
1797 tries++;
1798 if (BUTTON_PRESS()) return;
1799 } while (num_blocks != max_blocks);
1800 end:
1801 Dbprintf("-----------------------------------------");
1802 Dbprintf("Memory content:");
1803 Dbprintf("-----------------------------------------");
1804 for(i=0; i<max_blocks; i++) {
1805 if(Blocks[i][ALLOC]==1)
1806 Dbprintf("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
1807 Blocks[i][0], Blocks[i][1], Blocks[i][2], Blocks[i][3], Blocks[i][4], Blocks[i][5], Blocks[i][6], Blocks[i][7],
1808 Blocks[i][8], Blocks[i][9], Blocks[i][10], Blocks[i][11], Blocks[i][12], Blocks[i][13], Blocks[i][14], Blocks[i][15]);
1809 else
1810 Dbprintf("<missing block %d>", i);
1811 }
1812 Dbprintf("-----------------------------------------");
1813
1814 return ;
1815}
1816
1817
1818//-----------------------------------
1819// EM4469 / EM4305 routines
1820//-----------------------------------
1821#define FWD_CMD_LOGIN 0xC //including the even parity, binary mirrored
1822#define FWD_CMD_WRITE 0xA
1823#define FWD_CMD_READ 0x9
1824#define FWD_CMD_DISABLE 0x5
1825
1826
1827uint8_t forwardLink_data[64]; //array of forwarded bits
1828uint8_t * forward_ptr; //ptr for forward message preparation
1829uint8_t fwd_bit_sz; //forwardlink bit counter
1830uint8_t * fwd_write_ptr; //forwardlink bit pointer
1831
1832//====================================================================
1833// prepares command bits
1834// see EM4469 spec
1835//====================================================================
1836//--------------------------------------------------------------------
1837uint8_t Prepare_Cmd( uint8_t cmd ) {
1838 //--------------------------------------------------------------------
1839
1840 *forward_ptr++ = 0; //start bit
1841 *forward_ptr++ = 0; //second pause for 4050 code
1842
1843 *forward_ptr++ = cmd;
1844 cmd >>= 1;
1845 *forward_ptr++ = cmd;
1846 cmd >>= 1;
1847 *forward_ptr++ = cmd;
1848 cmd >>= 1;
1849 *forward_ptr++ = cmd;
1850
1851 return 6; //return number of emited bits
1852}
1853
1854//====================================================================
1855// prepares address bits
1856// see EM4469 spec
1857//====================================================================
1858
1859//--------------------------------------------------------------------
1860uint8_t Prepare_Addr( uint8_t addr ) {
1861 //--------------------------------------------------------------------
1862
1863 register uint8_t line_parity;
1864
1865 uint8_t i;
1866 line_parity = 0;
1867 for(i=0;i<6;i++) {
1868 *forward_ptr++ = addr;
1869 line_parity ^= addr;
1870 addr >>= 1;
1871 }
1872
1873 *forward_ptr++ = (line_parity & 1);
1874
1875 return 7; //return number of emited bits
1876}
1877
1878//====================================================================
1879// prepares data bits intreleaved with parity bits
1880// see EM4469 spec
1881//====================================================================
1882
1883//--------------------------------------------------------------------
1884uint8_t Prepare_Data( uint16_t data_low, uint16_t data_hi) {
1885 //--------------------------------------------------------------------
1886
1887 register uint8_t line_parity;
1888 register uint8_t column_parity;
1889 register uint8_t i, j;
1890 register uint16_t data;
1891
1892 data = data_low;
1893 column_parity = 0;
1894
1895 for(i=0; i<4; i++) {
1896 line_parity = 0;
1897 for(j=0; j<8; j++) {
1898 line_parity ^= data;
1899 column_parity ^= (data & 1) << j;
1900 *forward_ptr++ = data;
1901 data >>= 1;
1902 }
1903 *forward_ptr++ = line_parity;
1904 if(i == 1)
1905 data = data_hi;
1906 }
1907
1908 for(j=0; j<8; j++) {
1909 *forward_ptr++ = column_parity;
1910 column_parity >>= 1;
1911 }
1912 *forward_ptr = 0;
1913
1914 return 45; //return number of emited bits
1915}
1916
1917//====================================================================
1918// Forward Link send function
1919// Requires: forwarLink_data filled with valid bits (1 bit per byte)
1920// fwd_bit_count set with number of bits to be sent
1921//====================================================================
1922void SendForward(uint8_t fwd_bit_count) {
1923
1924 fwd_write_ptr = forwardLink_data;
1925 fwd_bit_sz = fwd_bit_count;
1926
1927 LED_D_ON();
1928
1929 //Field on
1930 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1931 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1932 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1933
1934 // Give it a bit of time for the resonant antenna to settle.
1935 // And for the tag to fully power up
1936 SpinDelay(150);
1937
1938 // force 1st mod pulse (start gap must be longer for 4305)
1939 fwd_bit_sz--; //prepare next bit modulation
1940 fwd_write_ptr++;
1941 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1942 SpinDelayUs(55*8); //55 cycles off (8us each)for 4305
1943 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1944 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1945 SpinDelayUs(16*8); //16 cycles on (8us each)
1946
1947 // now start writting
1948 while(fwd_bit_sz-- > 0) { //prepare next bit modulation
1949 if(((*fwd_write_ptr++) & 1) == 1)
1950 SpinDelayUs(32*8); //32 cycles at 125Khz (8us each)
1951 else {
1952 //These timings work for 4469/4269/4305 (with the 55*8 above)
1953 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1954 SpinDelayUs(23*8); //16-4 cycles off (8us each)
1955 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1956 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1957 SpinDelayUs(9*8); //16 cycles on (8us each)
1958 }
1959 }
1960}
1961
1962void EM4xLogin(uint32_t Password) {
1963
1964 uint8_t fwd_bit_count;
1965
1966 forward_ptr = forwardLink_data;
1967 fwd_bit_count = Prepare_Cmd( FWD_CMD_LOGIN );
1968 fwd_bit_count += Prepare_Data( Password&0xFFFF, Password>>16 );
1969
1970 SendForward(fwd_bit_count);
1971
1972 //Wait for command to complete
1973 SpinDelay(20);
1974
1975}
1976
1977void EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1978
1979 uint8_t fwd_bit_count;
1980 uint8_t *dest = BigBuf_get_addr();
1981 int m=0, i=0;
1982
1983 //If password mode do login
1984 if (PwdMode == 1) EM4xLogin(Pwd);
1985
1986 forward_ptr = forwardLink_data;
1987 fwd_bit_count = Prepare_Cmd( FWD_CMD_READ );
1988 fwd_bit_count += Prepare_Addr( Address );
1989
1990 m = BigBuf_max_traceLen();
1991 // Clear destination buffer before sending the command
1992 memset(dest, 128, m);
1993 // Connect the A/D to the peak-detected low-frequency path.
1994 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1995 // Now set up the SSC to get the ADC samples that are now streaming at us.
1996 FpgaSetupSsc();
1997
1998 SendForward(fwd_bit_count);
1999
2000 // Now do the acquisition
2001 i = 0;
2002 for(;;) {
2003 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
2004 AT91C_BASE_SSC->SSC_THR = 0x43;
2005 }
2006 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
2007 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
2008 i++;
2009 if (i >= m) break;
2010 }
2011 }
2012 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
2013 LED_D_OFF();
2014}
2015
2016void EM4xWriteWord(uint32_t Data, uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
2017
2018 uint8_t fwd_bit_count;
2019
2020 //If password mode do login
2021 if (PwdMode == 1) EM4xLogin(Pwd);
2022
2023 forward_ptr = forwardLink_data;
2024 fwd_bit_count = Prepare_Cmd( FWD_CMD_WRITE );
2025 fwd_bit_count += Prepare_Addr( Address );
2026 fwd_bit_count += Prepare_Data( Data&0xFFFF, Data>>16 );
2027
2028 SendForward(fwd_bit_count);
2029
2030 //Wait for write to complete
2031 SpinDelay(20);
2032 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
2033 LED_D_OFF();
2034}
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