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Fixed indents to Tabs from Spaces
[proxmark3-svn] / armsrc / lfops.c
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e09f21fa 1//-----------------------------------------------------------------------------
2// This code is licensed to you under the terms of the GNU GPL, version 2 or,
3// at your option, any later version. See the LICENSE.txt file for the text of
4// the license.
5//-----------------------------------------------------------------------------
6// Miscellaneous routines for low frequency tag operations.
7// Tags supported here so far are Texas Instruments (TI), HID
8// Also routines for raw mode reading/simulating of LF waveform
9//-----------------------------------------------------------------------------
10
11#include "proxmark3.h"
12#include "apps.h"
13#include "util.h"
14#include "hitag2.h"
15#include "crc16.h"
16#include "string.h"
17#include "lfdemod.h"
18#include "lfsampling.h"
f7048dc8 19#include "usb_cdc.h"
e09f21fa 20
21
22/**
23 * Function to do a modulation and then get samples.
24 * @param delay_off
25 * @param period_0
26 * @param period_1
27 * @param command
28 */
29void ModThenAcquireRawAdcSamples125k(int delay_off, int period_0, int period_1, uint8_t *command)
30{
31
e0165dcf 32 int divisor_used = 95; // 125 KHz
33 // see if 'h' was specified
e09f21fa 34
e0165dcf 35 if (command[strlen((char *) command) - 1] == 'h')
36 divisor_used = 88; // 134.8 KHz
e09f21fa 37
38 sample_config sc = { 0,0,1, divisor_used, 0};
39 setSamplingConfig(&sc);
40
41 /* Make sure the tag is reset */
42 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
43 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
44 SpinDelay(2500);
45
46 LFSetupFPGAForADC(sc.divisor, 1);
47
48 // And a little more time for the tag to fully power up
49 SpinDelay(2000);
50
e0165dcf 51 // now modulate the reader field
52 while(*command != '\0' && *command != ' ') {
53 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
54 LED_D_OFF();
55 SpinDelayUs(delay_off);
e09f21fa 56 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc.divisor);
57
e0165dcf 58 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
59 LED_D_ON();
60 if(*(command++) == '0')
61 SpinDelayUs(period_0);
62 else
63 SpinDelayUs(period_1);
64 }
65 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
66 LED_D_OFF();
67 SpinDelayUs(delay_off);
e09f21fa 68 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc.divisor);
69
e0165dcf 70 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
e09f21fa 71
e0165dcf 72 // now do the read
e09f21fa 73 DoAcquisition_config(false);
74}
75
76
77
78/* blank r/w tag data stream
79...0000000000000000 01111111
801010101010101010101010101010101010101010101010101010101010101010
810011010010100001
8201111111
83101010101010101[0]000...
84
85[5555fe852c5555555555555555fe0000]
86*/
87void ReadTItag(void)
88{
e0165dcf 89 // some hardcoded initial params
90 // when we read a TI tag we sample the zerocross line at 2Mhz
91 // TI tags modulate a 1 as 16 cycles of 123.2Khz
92 // TI tags modulate a 0 as 16 cycles of 134.2Khz
e09f21fa 93 #define FSAMPLE 2000000
94 #define FREQLO 123200
95 #define FREQHI 134200
96
e0165dcf 97 signed char *dest = (signed char *)BigBuf_get_addr();
98 uint16_t n = BigBuf_max_traceLen();
99 // 128 bit shift register [shift3:shift2:shift1:shift0]
100 uint32_t shift3 = 0, shift2 = 0, shift1 = 0, shift0 = 0;
101
102 int i, cycles=0, samples=0;
103 // how many sample points fit in 16 cycles of each frequency
104 uint32_t sampleslo = (FSAMPLE<<4)/FREQLO, sampleshi = (FSAMPLE<<4)/FREQHI;
105 // when to tell if we're close enough to one freq or another
106 uint32_t threshold = (sampleslo - sampleshi + 1)>>1;
107
108 // TI tags charge at 134.2Khz
109 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
110 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
111
112 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
113 // connects to SSP_DIN and the SSP_DOUT logic level controls
114 // whether we're modulating the antenna (high)
115 // or listening to the antenna (low)
116 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
117
118 // get TI tag data into the buffer
119 AcquireTiType();
120
121 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
122
123 for (i=0; i<n-1; i++) {
124 // count cycles by looking for lo to hi zero crossings
125 if ( (dest[i]<0) && (dest[i+1]>0) ) {
126 cycles++;
127 // after 16 cycles, measure the frequency
128 if (cycles>15) {
129 cycles=0;
130 samples=i-samples; // number of samples in these 16 cycles
131
132 // TI bits are coming to us lsb first so shift them
133 // right through our 128 bit right shift register
134 shift0 = (shift0>>1) | (shift1 << 31);
135 shift1 = (shift1>>1) | (shift2 << 31);
136 shift2 = (shift2>>1) | (shift3 << 31);
137 shift3 >>= 1;
138
139 // check if the cycles fall close to the number
140 // expected for either the low or high frequency
141 if ( (samples>(sampleslo-threshold)) && (samples<(sampleslo+threshold)) ) {
142 // low frequency represents a 1
143 shift3 |= (1<<31);
144 } else if ( (samples>(sampleshi-threshold)) && (samples<(sampleshi+threshold)) ) {
145 // high frequency represents a 0
146 } else {
147 // probably detected a gay waveform or noise
148 // use this as gaydar or discard shift register and start again
149 shift3 = shift2 = shift1 = shift0 = 0;
150 }
151 samples = i;
152
153 // for each bit we receive, test if we've detected a valid tag
154
155 // if we see 17 zeroes followed by 6 ones, we might have a tag
156 // remember the bits are backwards
157 if ( ((shift0 & 0x7fffff) == 0x7e0000) ) {
158 // if start and end bytes match, we have a tag so break out of the loop
159 if ( ((shift0>>16)&0xff) == ((shift3>>8)&0xff) ) {
160 cycles = 0xF0B; //use this as a flag (ugly but whatever)
161 break;
162 }
163 }
164 }
165 }
166 }
167
168 // if flag is set we have a tag
169 if (cycles!=0xF0B) {
170 DbpString("Info: No valid tag detected.");
171 } else {
172 // put 64 bit data into shift1 and shift0
173 shift0 = (shift0>>24) | (shift1 << 8);
174 shift1 = (shift1>>24) | (shift2 << 8);
175
176 // align 16 bit crc into lower half of shift2
177 shift2 = ((shift2>>24) | (shift3 << 8)) & 0x0ffff;
178
179 // if r/w tag, check ident match
e09f21fa 180 if (shift3 & (1<<15) ) {
e0165dcf 181 DbpString("Info: TI tag is rewriteable");
182 // only 15 bits compare, last bit of ident is not valid
e09f21fa 183 if (((shift3 >> 16) ^ shift0) & 0x7fff ) {
e0165dcf 184 DbpString("Error: Ident mismatch!");
185 } else {
186 DbpString("Info: TI tag ident is valid");
187 }
188 } else {
189 DbpString("Info: TI tag is readonly");
190 }
191
192 // WARNING the order of the bytes in which we calc crc below needs checking
193 // i'm 99% sure the crc algorithm is correct, but it may need to eat the
194 // bytes in reverse or something
195 // calculate CRC
196 uint32_t crc=0;
197
198 crc = update_crc16(crc, (shift0)&0xff);
199 crc = update_crc16(crc, (shift0>>8)&0xff);
200 crc = update_crc16(crc, (shift0>>16)&0xff);
201 crc = update_crc16(crc, (shift0>>24)&0xff);
202 crc = update_crc16(crc, (shift1)&0xff);
203 crc = update_crc16(crc, (shift1>>8)&0xff);
204 crc = update_crc16(crc, (shift1>>16)&0xff);
205 crc = update_crc16(crc, (shift1>>24)&0xff);
206
207 Dbprintf("Info: Tag data: %x%08x, crc=%x",
208 (unsigned int)shift1, (unsigned int)shift0, (unsigned int)shift2 & 0xFFFF);
209 if (crc != (shift2&0xffff)) {
210 Dbprintf("Error: CRC mismatch, expected %x", (unsigned int)crc);
211 } else {
212 DbpString("Info: CRC is good");
213 }
214 }
e09f21fa 215}
216
217void WriteTIbyte(uint8_t b)
218{
e0165dcf 219 int i = 0;
220
221 // modulate 8 bits out to the antenna
222 for (i=0; i<8; i++)
223 {
224 if (b&(1<<i)) {
225 // stop modulating antenna
226 LOW(GPIO_SSC_DOUT);
227 SpinDelayUs(1000);
228 // modulate antenna
229 HIGH(GPIO_SSC_DOUT);
230 SpinDelayUs(1000);
231 } else {
232 // stop modulating antenna
233 LOW(GPIO_SSC_DOUT);
234 SpinDelayUs(300);
235 // modulate antenna
236 HIGH(GPIO_SSC_DOUT);
237 SpinDelayUs(1700);
238 }
239 }
e09f21fa 240}
241
242void AcquireTiType(void)
243{
e0165dcf 244 int i, j, n;
245 // tag transmission is <20ms, sampling at 2M gives us 40K samples max
246 // each sample is 1 bit stuffed into a uint32_t so we need 1250 uint32_t
e09f21fa 247 #define TIBUFLEN 1250
248
e0165dcf 249 // clear buffer
e09f21fa 250 uint32_t *BigBuf = (uint32_t *)BigBuf_get_addr();
e0165dcf 251 memset(BigBuf,0,BigBuf_max_traceLen()/sizeof(uint32_t));
252
253 // Set up the synchronous serial port
254 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DIN;
255 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN;
256
257 // steal this pin from the SSP and use it to control the modulation
258 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
259 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
260
261 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST;
262 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_RXEN | AT91C_SSC_TXEN;
263
264 // Sample at 2 Mbit/s, so TI tags are 16.2 vs. 14.9 clocks long
265 // 48/2 = 24 MHz clock must be divided by 12
266 AT91C_BASE_SSC->SSC_CMR = 12;
267
268 AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(0);
269 AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(32) | AT91C_SSC_MSBF;
270 AT91C_BASE_SSC->SSC_TCMR = 0;
271 AT91C_BASE_SSC->SSC_TFMR = 0;
272
273 LED_D_ON();
274
275 // modulate antenna
276 HIGH(GPIO_SSC_DOUT);
277
278 // Charge TI tag for 50ms.
279 SpinDelay(50);
280
281 // stop modulating antenna and listen
282 LOW(GPIO_SSC_DOUT);
283
284 LED_D_OFF();
285
286 i = 0;
287 for(;;) {
288 if(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
289 BigBuf[i] = AT91C_BASE_SSC->SSC_RHR; // store 32 bit values in buffer
290 i++; if(i >= TIBUFLEN) break;
291 }
292 WDT_HIT();
293 }
294
295 // return stolen pin to SSP
296 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT;
297 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN | GPIO_SSC_DOUT;
298
299 char *dest = (char *)BigBuf_get_addr();
300 n = TIBUFLEN*32;
301 // unpack buffer
302 for (i=TIBUFLEN-1; i>=0; i--) {
303 for (j=0; j<32; j++) {
304 if(BigBuf[i] & (1 << j)) {
305 dest[--n] = 1;
306 } else {
307 dest[--n] = -1;
308 }
309 }
310 }
e09f21fa 311}
312
313// arguments: 64bit data split into 32bit idhi:idlo and optional 16bit crc
314// if crc provided, it will be written with the data verbatim (even if bogus)
315// if not provided a valid crc will be computed from the data and written.
316void WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc)
317{
e0165dcf 318 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
319 if(crc == 0) {
320 crc = update_crc16(crc, (idlo)&0xff);
321 crc = update_crc16(crc, (idlo>>8)&0xff);
322 crc = update_crc16(crc, (idlo>>16)&0xff);
323 crc = update_crc16(crc, (idlo>>24)&0xff);
324 crc = update_crc16(crc, (idhi)&0xff);
325 crc = update_crc16(crc, (idhi>>8)&0xff);
326 crc = update_crc16(crc, (idhi>>16)&0xff);
327 crc = update_crc16(crc, (idhi>>24)&0xff);
328 }
329 Dbprintf("Writing to tag: %x%08x, crc=%x",
330 (unsigned int) idhi, (unsigned int) idlo, crc);
331
332 // TI tags charge at 134.2Khz
333 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
334 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
335 // connects to SSP_DIN and the SSP_DOUT logic level controls
336 // whether we're modulating the antenna (high)
337 // or listening to the antenna (low)
338 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
339 LED_A_ON();
340
341 // steal this pin from the SSP and use it to control the modulation
342 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
343 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
344
345 // writing algorithm:
346 // a high bit consists of a field off for 1ms and field on for 1ms
347 // a low bit consists of a field off for 0.3ms and field on for 1.7ms
348 // initiate a charge time of 50ms (field on) then immediately start writing bits
349 // start by writing 0xBB (keyword) and 0xEB (password)
350 // then write 80 bits of data (or 64 bit data + 16 bit crc if you prefer)
351 // finally end with 0x0300 (write frame)
352 // all data is sent lsb firts
353 // finish with 15ms programming time
354
355 // modulate antenna
356 HIGH(GPIO_SSC_DOUT);
357 SpinDelay(50); // charge time
358
359 WriteTIbyte(0xbb); // keyword
360 WriteTIbyte(0xeb); // password
361 WriteTIbyte( (idlo )&0xff );
362 WriteTIbyte( (idlo>>8 )&0xff );
363 WriteTIbyte( (idlo>>16)&0xff );
364 WriteTIbyte( (idlo>>24)&0xff );
365 WriteTIbyte( (idhi )&0xff );
366 WriteTIbyte( (idhi>>8 )&0xff );
367 WriteTIbyte( (idhi>>16)&0xff );
368 WriteTIbyte( (idhi>>24)&0xff ); // data hi to lo
369 WriteTIbyte( (crc )&0xff ); // crc lo
370 WriteTIbyte( (crc>>8 )&0xff ); // crc hi
371 WriteTIbyte(0x00); // write frame lo
372 WriteTIbyte(0x03); // write frame hi
373 HIGH(GPIO_SSC_DOUT);
374 SpinDelay(50); // programming time
375
376 LED_A_OFF();
377
378 // get TI tag data into the buffer
379 AcquireTiType();
380
381 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
382 DbpString("Now use tiread to check");
e09f21fa 383}
384
385void SimulateTagLowFrequency(int period, int gap, int ledcontrol)
386{
e0165dcf 387 int i;
388 uint8_t *tab = BigBuf_get_addr();
e09f21fa 389
e0165dcf 390 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
391 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT);
e09f21fa 392
e0165dcf 393 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK;
e09f21fa 394
e0165dcf 395 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
396 AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK;
e09f21fa 397
398 #define SHORT_COIL() LOW(GPIO_SSC_DOUT)
399 #define OPEN_COIL() HIGH(GPIO_SSC_DOUT)
400
e0165dcf 401 i = 0;
402 for(;;) {
403 //wait until SSC_CLK goes HIGH
404 while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) {
f7048dc8 405 if(BUTTON_PRESS() || usb_poll()) {
e0165dcf 406 DbpString("Stopped");
407 return;
408 }
409 WDT_HIT();
410 }
411 if (ledcontrol)
412 LED_D_ON();
413
414 if(tab[i])
415 OPEN_COIL();
416 else
417 SHORT_COIL();
418
419 if (ledcontrol)
420 LED_D_OFF();
421 //wait until SSC_CLK goes LOW
422 while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) {
423 if(BUTTON_PRESS()) {
424 DbpString("Stopped");
425 return;
426 }
427 WDT_HIT();
428 }
429
430 i++;
431 if(i == period) {
432
433 i = 0;
434 if (gap) {
435 SHORT_COIL();
436 SpinDelayUs(gap);
437 }
438 }
439 }
e09f21fa 440}
441
e09f21fa 442#define DEBUG_FRAME_CONTENTS 1
443void SimulateTagLowFrequencyBidir(int divisor, int t0)
444{
445}
446
447// compose fc/8 fc/10 waveform (FSK2)
448static void fc(int c, int *n)
449{
e0165dcf 450 uint8_t *dest = BigBuf_get_addr();
451 int idx;
452
453 // for when we want an fc8 pattern every 4 logical bits
454 if(c==0) {
455 dest[((*n)++)]=1;
456 dest[((*n)++)]=1;
457 dest[((*n)++)]=1;
458 dest[((*n)++)]=1;
459 dest[((*n)++)]=0;
460 dest[((*n)++)]=0;
461 dest[((*n)++)]=0;
462 dest[((*n)++)]=0;
463 }
464
465 // an fc/8 encoded bit is a bit pattern of 11110000 x6 = 48 samples
466 if(c==8) {
467 for (idx=0; idx<6; idx++) {
468 dest[((*n)++)]=1;
469 dest[((*n)++)]=1;
470 dest[((*n)++)]=1;
471 dest[((*n)++)]=1;
472 dest[((*n)++)]=0;
473 dest[((*n)++)]=0;
474 dest[((*n)++)]=0;
475 dest[((*n)++)]=0;
476 }
477 }
478
479 // an fc/10 encoded bit is a bit pattern of 1111100000 x5 = 50 samples
480 if(c==10) {
481 for (idx=0; idx<5; idx++) {
482 dest[((*n)++)]=1;
483 dest[((*n)++)]=1;
484 dest[((*n)++)]=1;
485 dest[((*n)++)]=1;
486 dest[((*n)++)]=1;
487 dest[((*n)++)]=0;
488 dest[((*n)++)]=0;
489 dest[((*n)++)]=0;
490 dest[((*n)++)]=0;
491 dest[((*n)++)]=0;
492 }
493 }
e09f21fa 494}
495// compose fc/X fc/Y waveform (FSKx)
712ebfa6 496static void fcAll(uint8_t fc, int *n, uint8_t clock, uint16_t *modCnt)
e09f21fa 497{
e0165dcf 498 uint8_t *dest = BigBuf_get_addr();
499 uint8_t halfFC = fc/2;
500 uint8_t wavesPerClock = clock/fc;
501 uint8_t mod = clock % fc; //modifier
502 uint8_t modAdj = fc/mod; //how often to apply modifier
503 bool modAdjOk = !(fc % mod); //if (fc % mod==0) modAdjOk=TRUE;
504 // loop through clock - step field clock
505 for (uint8_t idx=0; idx < wavesPerClock; idx++){
506 // put 1/2 FC length 1's and 1/2 0's per field clock wave (to create the wave)
507 memset(dest+(*n), 0, fc-halfFC); //in case of odd number use extra here
508 memset(dest+(*n)+(fc-halfFC), 1, halfFC);
509 *n += fc;
510 }
511 if (mod>0) (*modCnt)++;
512 if ((mod>0) && modAdjOk){ //fsk2
513 if ((*modCnt % modAdj) == 0){ //if 4th 8 length wave in a rf/50 add extra 8 length wave
514 memset(dest+(*n), 0, fc-halfFC);
515 memset(dest+(*n)+(fc-halfFC), 1, halfFC);
516 *n += fc;
517 }
518 }
519 if (mod>0 && !modAdjOk){ //fsk1
520 memset(dest+(*n), 0, mod-(mod/2));
521 memset(dest+(*n)+(mod-(mod/2)), 1, mod/2);
522 *n += mod;
523 }
e09f21fa 524}
525
526// prepare a waveform pattern in the buffer based on the ID given then
527// simulate a HID tag until the button is pressed
528void CmdHIDsimTAG(int hi, int lo, int ledcontrol)
529{
e0165dcf 530 int n=0, i=0;
531 /*
532 HID tag bitstream format
533 The tag contains a 44bit unique code. This is sent out MSB first in sets of 4 bits
534 A 1 bit is represented as 6 fc8 and 5 fc10 patterns
535 A 0 bit is represented as 5 fc10 and 6 fc8 patterns
536 A fc8 is inserted before every 4 bits
537 A special start of frame pattern is used consisting a0b0 where a and b are neither 0
538 nor 1 bits, they are special patterns (a = set of 12 fc8 and b = set of 10 fc10)
539 */
540
541 if (hi>0xFFF) {
542 DbpString("Tags can only have 44 bits. - USE lf simfsk for larger tags");
543 return;
544 }
545 fc(0,&n);
546 // special start of frame marker containing invalid bit sequences
547 fc(8, &n); fc(8, &n); // invalid
548 fc(8, &n); fc(10, &n); // logical 0
549 fc(10, &n); fc(10, &n); // invalid
550 fc(8, &n); fc(10, &n); // logical 0
551
552 WDT_HIT();
553 // manchester encode bits 43 to 32
554 for (i=11; i>=0; i--) {
555 if ((i%4)==3) fc(0,&n);
556 if ((hi>>i)&1) {
557 fc(10, &n); fc(8, &n); // low-high transition
558 } else {
559 fc(8, &n); fc(10, &n); // high-low transition
560 }
561 }
562
563 WDT_HIT();
564 // manchester encode bits 31 to 0
565 for (i=31; i>=0; i--) {
566 if ((i%4)==3) fc(0,&n);
567 if ((lo>>i)&1) {
568 fc(10, &n); fc(8, &n); // low-high transition
569 } else {
570 fc(8, &n); fc(10, &n); // high-low transition
571 }
572 }
573
574 if (ledcontrol)
575 LED_A_ON();
576 SimulateTagLowFrequency(n, 0, ledcontrol);
577
578 if (ledcontrol)
579 LED_A_OFF();
e09f21fa 580}
581
582// prepare a waveform pattern in the buffer based on the ID given then
583// simulate a FSK tag until the button is pressed
584// arg1 contains fcHigh and fcLow, arg2 contains invert and clock
585void CmdFSKsimTAG(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
586{
e0165dcf 587 int ledcontrol=1;
588 int n=0, i=0;
589 uint8_t fcHigh = arg1 >> 8;
590 uint8_t fcLow = arg1 & 0xFF;
591 uint16_t modCnt = 0;
592 uint8_t clk = arg2 & 0xFF;
593 uint8_t invert = (arg2 >> 8) & 1;
594
595 for (i=0; i<size; i++){
596 if (BitStream[i] == invert){
597 fcAll(fcLow, &n, clk, &modCnt);
598 } else {
599 fcAll(fcHigh, &n, clk, &modCnt);
600 }
601 }
602 Dbprintf("Simulating with fcHigh: %d, fcLow: %d, clk: %d, invert: %d, n: %d",fcHigh, fcLow, clk, invert, n);
603 /*Dbprintf("DEBUG: First 32:");
604 uint8_t *dest = BigBuf_get_addr();
605 i=0;
606 Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
607 i+=16;
608 Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
609 */
610 if (ledcontrol)
611 LED_A_ON();
612
613 SimulateTagLowFrequency(n, 0, ledcontrol);
614
615 if (ledcontrol)
616 LED_A_OFF();
e09f21fa 617}
618
619// compose ask waveform for one bit(ASK)
e0165dcf 620static void askSimBit(uint8_t c, int *n, uint8_t clock, uint8_t manchester)
e09f21fa 621{
e0165dcf 622 uint8_t *dest = BigBuf_get_addr();
623 uint8_t halfClk = clock/2;
624 // c = current bit 1 or 0
625 if (manchester==1){
626 memset(dest+(*n), c, halfClk);
627 memset(dest+(*n) + halfClk, c^1, halfClk);
628 } else {
629 memset(dest+(*n), c, clock);
630 }
631 *n += clock;
e09f21fa 632}
633
b41534d1 634static void biphaseSimBit(uint8_t c, int *n, uint8_t clock, uint8_t *phase)
635{
e0165dcf 636 uint8_t *dest = BigBuf_get_addr();
637 uint8_t halfClk = clock/2;
638 if (c){
639 memset(dest+(*n), c ^ 1 ^ *phase, halfClk);
640 memset(dest+(*n) + halfClk, c ^ *phase, halfClk);
641 } else {
642 memset(dest+(*n), c ^ *phase, clock);
643 *phase ^= 1;
644 }
b41534d1 645
646}
647
e09f21fa 648// args clock, ask/man or askraw, invert, transmission separator
649void CmdASKsimTag(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
650{
e0165dcf 651 int ledcontrol = 1;
652 int n=0, i=0;
653 uint8_t clk = (arg1 >> 8) & 0xFF;
654 uint8_t encoding = arg1 & 1;
655 uint8_t separator = arg2 & 1;
656 uint8_t invert = (arg2 >> 8) & 1;
657
658 if (encoding==2){ //biphase
659 uint8_t phase=0;
660 for (i=0; i<size; i++){
661 biphaseSimBit(BitStream[i]^invert, &n, clk, &phase);
662 }
663 if (BitStream[0]==BitStream[size-1]){ //run a second set inverted to keep phase in check
664 for (i=0; i<size; i++){
665 biphaseSimBit(BitStream[i]^invert, &n, clk, &phase);
666 }
667 }
668 } else { // ask/manchester || ask/raw
669 for (i=0; i<size; i++){
670 askSimBit(BitStream[i]^invert, &n, clk, encoding);
671 }
672 if (encoding==0 && BitStream[0]==BitStream[size-1]){ //run a second set inverted (for biphase phase)
673 for (i=0; i<size; i++){
674 askSimBit(BitStream[i]^invert^1, &n, clk, encoding);
675 }
676 }
677 }
678
679 if (separator==1) Dbprintf("sorry but separator option not yet available");
680
681 Dbprintf("Simulating with clk: %d, invert: %d, encoding: %d, separator: %d, n: %d",clk, invert, encoding, separator, n);
682 //DEBUG
683 //Dbprintf("First 32:");
684 //uint8_t *dest = BigBuf_get_addr();
685 //i=0;
686 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
687 //i+=16;
688 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
689
690 if (ledcontrol)
691 LED_A_ON();
692
693 SimulateTagLowFrequency(n, 0, ledcontrol);
694
695 if (ledcontrol)
696 LED_A_OFF();
e09f21fa 697}
698
699//carrier can be 2,4 or 8
700static void pskSimBit(uint8_t waveLen, int *n, uint8_t clk, uint8_t *curPhase, bool phaseChg)
701{
e0165dcf 702 uint8_t *dest = BigBuf_get_addr();
703 uint8_t halfWave = waveLen/2;
704 //uint8_t idx;
705 int i = 0;
706 if (phaseChg){
707 // write phase change
708 memset(dest+(*n), *curPhase^1, halfWave);
709 memset(dest+(*n) + halfWave, *curPhase, halfWave);
710 *n += waveLen;
711 *curPhase ^= 1;
712 i += waveLen;
713 }
714 //write each normal clock wave for the clock duration
715 for (; i < clk; i+=waveLen){
716 memset(dest+(*n), *curPhase, halfWave);
717 memset(dest+(*n) + halfWave, *curPhase^1, halfWave);
718 *n += waveLen;
719 }
e09f21fa 720}
721
722// args clock, carrier, invert,
723void CmdPSKsimTag(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
724{
e0165dcf 725 int ledcontrol=1;
726 int n=0, i=0;
727 uint8_t clk = arg1 >> 8;
728 uint8_t carrier = arg1 & 0xFF;
729 uint8_t invert = arg2 & 0xFF;
730 uint8_t curPhase = 0;
731 for (i=0; i<size; i++){
732 if (BitStream[i] == curPhase){
733 pskSimBit(carrier, &n, clk, &curPhase, FALSE);
734 } else {
735 pskSimBit(carrier, &n, clk, &curPhase, TRUE);
736 }
737 }
738 Dbprintf("Simulating with Carrier: %d, clk: %d, invert: %d, n: %d",carrier, clk, invert, n);
739 //Dbprintf("DEBUG: First 32:");
740 //uint8_t *dest = BigBuf_get_addr();
741 //i=0;
742 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
743 //i+=16;
744 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
745
746 if (ledcontrol)
747 LED_A_ON();
748 SimulateTagLowFrequency(n, 0, ledcontrol);
749
750 if (ledcontrol)
751 LED_A_OFF();
e09f21fa 752}
753
754// loop to get raw HID waveform then FSK demodulate the TAG ID from it
755void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
756{
e0165dcf 757 uint8_t *dest = BigBuf_get_addr();
758 const size_t sizeOfBigBuff = BigBuf_max_traceLen();
759 size_t size = 0;
760 uint32_t hi2=0, hi=0, lo=0;
761 int idx=0;
762 // Configure to go in 125Khz listen mode
763 LFSetupFPGAForADC(95, true);
e09f21fa 764
e0165dcf 765 while(!BUTTON_PRESS()) {
e09f21fa 766
e0165dcf 767 WDT_HIT();
768 if (ledcontrol) LED_A_ON();
e09f21fa 769
770 DoAcquisition_default(-1,true);
771 // FSK demodulator
e0165dcf 772 size = sizeOfBigBuff; //variable size will change after demod so re initialize it before use
e09f21fa 773 idx = HIDdemodFSK(dest, &size, &hi2, &hi, &lo);
e0165dcf 774
e09f21fa 775 if (idx>0 && lo>0){
e0165dcf 776 // final loop, go over previously decoded manchester data and decode into usable tag ID
777 // 111000 bit pattern represent start of frame, 01 pattern represents a 1 and 10 represents a 0
778 if (hi2 != 0){ //extra large HID tags
779 Dbprintf("TAG ID: %x%08x%08x (%d)",
780 (unsigned int) hi2, (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
781 }else { //standard HID tags <38 bits
782 //Dbprintf("TAG ID: %x%08x (%d)",(unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF); //old print cmd
783 uint8_t bitlen = 0;
784 uint32_t fc = 0;
785 uint32_t cardnum = 0;
e09f21fa 786 if (((hi>>5)&1) == 1){//if bit 38 is set then < 37 bit format is used
e0165dcf 787 uint32_t lo2=0;
788 lo2=(((hi & 31) << 12) | (lo>>20)); //get bits 21-37 to check for format len bit
789 uint8_t idx3 = 1;
e09f21fa 790 while(lo2 > 1){ //find last bit set to 1 (format len bit)
791 lo2=lo2 >> 1;
e0165dcf 792 idx3++;
793 }
e09f21fa 794 bitlen = idx3+19;
e0165dcf 795 fc =0;
796 cardnum=0;
e09f21fa 797 if(bitlen == 26){
e0165dcf 798 cardnum = (lo>>1)&0xFFFF;
799 fc = (lo>>17)&0xFF;
800 }
e09f21fa 801 if(bitlen == 37){
e0165dcf 802 cardnum = (lo>>1)&0x7FFFF;
803 fc = ((hi&0xF)<<12)|(lo>>20);
804 }
e09f21fa 805 if(bitlen == 34){
e0165dcf 806 cardnum = (lo>>1)&0xFFFF;
807 fc= ((hi&1)<<15)|(lo>>17);
808 }
e09f21fa 809 if(bitlen == 35){
e0165dcf 810 cardnum = (lo>>1)&0xFFFFF;
811 fc = ((hi&1)<<11)|(lo>>21);
812 }
813 }
814 else { //if bit 38 is not set then 37 bit format is used
815 bitlen= 37;
816 fc =0;
817 cardnum=0;
818 if(bitlen==37){
819 cardnum = (lo>>1)&0x7FFFF;
820 fc = ((hi&0xF)<<12)|(lo>>20);
821 }
822 }
823 //Dbprintf("TAG ID: %x%08x (%d)",
824 // (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
825 Dbprintf("TAG ID: %x%08x (%d) - Format Len: %dbit - FC: %d - Card: %d",
826 (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF,
827 (unsigned int) bitlen, (unsigned int) fc, (unsigned int) cardnum);
828 }
829 if (findone){
830 if (ledcontrol) LED_A_OFF();
831 *high = hi;
832 *low = lo;
833 return;
834 }
835 // reset
836 hi2 = hi = lo = 0;
837 }
838 WDT_HIT();
839 }
840 DbpString("Stopped");
841 if (ledcontrol) LED_A_OFF();
e09f21fa 842}
843
844void CmdEM410xdemod(int findone, int *high, int *low, int ledcontrol)
845{
e0165dcf 846 uint8_t *dest = BigBuf_get_addr();
847
848 size_t size=0, idx=0;
849 int clk=0, invert=0, errCnt=0, maxErr=20;
850 uint32_t hi=0;
851 uint64_t lo=0;
852 // Configure to go in 125Khz listen mode
853 LFSetupFPGAForADC(95, true);
854
855 while(!BUTTON_PRESS()) {
856
857 WDT_HIT();
858 if (ledcontrol) LED_A_ON();
859
860 DoAcquisition_default(-1,true);
861 size = BigBuf_max_traceLen();
862 //Dbprintf("DEBUG: Buffer got");
863 //askdemod and manchester decode
864 errCnt = askmandemod(dest, &size, &clk, &invert, maxErr);
865 //Dbprintf("DEBUG: ASK Got");
866 WDT_HIT();
867
868 if (errCnt>=0){
869 errCnt = Em410xDecode(dest, &size, &idx, &hi, &lo);
870 //Dbprintf("DEBUG: EM GOT");
871 if (errCnt){
872 if (size>64){
873 Dbprintf("EM XL TAG ID: %06x%08x%08x - (%05d_%03d_%08d)",
874 hi,
875 (uint32_t)(lo>>32),
876 (uint32_t)lo,
877 (uint32_t)(lo&0xFFFF),
878 (uint32_t)((lo>>16LL) & 0xFF),
879 (uint32_t)(lo & 0xFFFFFF));
880 } else {
881 Dbprintf("EM TAG ID: %02x%08x - (%05d_%03d_%08d)",
882 (uint32_t)(lo>>32),
883 (uint32_t)lo,
884 (uint32_t)(lo&0xFFFF),
885 (uint32_t)((lo>>16LL) & 0xFF),
886 (uint32_t)(lo & 0xFFFFFF));
887 }
888 }
889 if (findone){
890 if (ledcontrol) LED_A_OFF();
891 *high=lo>>32;
892 *low=lo & 0xFFFFFFFF;
893 return;
894 }
895 } else{
896 //Dbprintf("DEBUG: No Tag");
897 }
898 WDT_HIT();
899 hi = 0;
900 lo = 0;
901 clk=0;
902 invert=0;
903 errCnt=0;
904 size=0;
905 }
906 DbpString("Stopped");
907 if (ledcontrol) LED_A_OFF();
e09f21fa 908}
909
910void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
911{
e0165dcf 912 uint8_t *dest = BigBuf_get_addr();
913 int idx=0;
914 uint32_t code=0, code2=0;
915 uint8_t version=0;
916 uint8_t facilitycode=0;
917 uint16_t number=0;
918 // Configure to go in 125Khz listen mode
919 LFSetupFPGAForADC(95, true);
920
921 while(!BUTTON_PRESS()) {
922 WDT_HIT();
923 if (ledcontrol) LED_A_ON();
e09f21fa 924 DoAcquisition_default(-1,true);
925 //fskdemod and get start index
e0165dcf 926 WDT_HIT();
927 idx = IOdemodFSK(dest, BigBuf_max_traceLen());
928 if (idx>0){
929 //valid tag found
930
931 //Index map
932 //0 10 20 30 40 50 60
933 //| | | | | | |
934 //01234567 8 90123456 7 89012345 6 78901234 5 67890123 4 56789012 3 45678901 23
935 //-----------------------------------------------------------------------------
936 //00000000 0 11110000 1 facility 1 version* 1 code*one 1 code*two 1 ???????? 11
937 //
938 //XSF(version)facility:codeone+codetwo
939 //Handle the data
940 if(findone){ //only print binary if we are doing one
941 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx], dest[idx+1], dest[idx+2],dest[idx+3],dest[idx+4],dest[idx+5],dest[idx+6],dest[idx+7],dest[idx+8]);
942 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+9], dest[idx+10],dest[idx+11],dest[idx+12],dest[idx+13],dest[idx+14],dest[idx+15],dest[idx+16],dest[idx+17]);
943 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+18],dest[idx+19],dest[idx+20],dest[idx+21],dest[idx+22],dest[idx+23],dest[idx+24],dest[idx+25],dest[idx+26]);
944 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+27],dest[idx+28],dest[idx+29],dest[idx+30],dest[idx+31],dest[idx+32],dest[idx+33],dest[idx+34],dest[idx+35]);
945 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+36],dest[idx+37],dest[idx+38],dest[idx+39],dest[idx+40],dest[idx+41],dest[idx+42],dest[idx+43],dest[idx+44]);
946 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+45],dest[idx+46],dest[idx+47],dest[idx+48],dest[idx+49],dest[idx+50],dest[idx+51],dest[idx+52],dest[idx+53]);
947 Dbprintf("%d%d%d%d%d%d%d%d %d%d",dest[idx+54],dest[idx+55],dest[idx+56],dest[idx+57],dest[idx+58],dest[idx+59],dest[idx+60],dest[idx+61],dest[idx+62],dest[idx+63]);
948 }
949 code = bytebits_to_byte(dest+idx,32);
950 code2 = bytebits_to_byte(dest+idx+32,32);
951 version = bytebits_to_byte(dest+idx+27,8); //14,4
952 facilitycode = bytebits_to_byte(dest+idx+18,8) ;
953 number = (bytebits_to_byte(dest+idx+36,8)<<8)|(bytebits_to_byte(dest+idx+45,8)); //36,9
954
955 Dbprintf("XSF(%02d)%02x:%05d (%08x%08x)",version,facilitycode,number,code,code2);
956 // if we're only looking for one tag
957 if (findone){
958 if (ledcontrol) LED_A_OFF();
959 //LED_A_OFF();
960 *high=code;
961 *low=code2;
962 return;
963 }
964 code=code2=0;
965 version=facilitycode=0;
966 number=0;
967 idx=0;
968 }
969 WDT_HIT();
970 }
971 DbpString("Stopped");
972 if (ledcontrol) LED_A_OFF();
e09f21fa 973}
974
975/*------------------------------
976 * T5555/T5557/T5567 routines
977 *------------------------------
978 */
979
980/* T55x7 configuration register definitions */
981#define T55x7_POR_DELAY 0x00000001
982#define T55x7_ST_TERMINATOR 0x00000008
983#define T55x7_PWD 0x00000010
984#define T55x7_MAXBLOCK_SHIFT 5
985#define T55x7_AOR 0x00000200
986#define T55x7_PSKCF_RF_2 0
987#define T55x7_PSKCF_RF_4 0x00000400
988#define T55x7_PSKCF_RF_8 0x00000800
989#define T55x7_MODULATION_DIRECT 0
990#define T55x7_MODULATION_PSK1 0x00001000
991#define T55x7_MODULATION_PSK2 0x00002000
992#define T55x7_MODULATION_PSK3 0x00003000
993#define T55x7_MODULATION_FSK1 0x00004000
994#define T55x7_MODULATION_FSK2 0x00005000
995#define T55x7_MODULATION_FSK1a 0x00006000
996#define T55x7_MODULATION_FSK2a 0x00007000
997#define T55x7_MODULATION_MANCHESTER 0x00008000
998#define T55x7_MODULATION_BIPHASE 0x00010000
999#define T55x7_BITRATE_RF_8 0
1000#define T55x7_BITRATE_RF_16 0x00040000
1001#define T55x7_BITRATE_RF_32 0x00080000
1002#define T55x7_BITRATE_RF_40 0x000C0000
1003#define T55x7_BITRATE_RF_50 0x00100000
1004#define T55x7_BITRATE_RF_64 0x00140000
1005#define T55x7_BITRATE_RF_100 0x00180000
1006#define T55x7_BITRATE_RF_128 0x001C0000
1007
1008/* T5555 (Q5) configuration register definitions */
1009#define T5555_ST_TERMINATOR 0x00000001
1010#define T5555_MAXBLOCK_SHIFT 0x00000001
1011#define T5555_MODULATION_MANCHESTER 0
1012#define T5555_MODULATION_PSK1 0x00000010
1013#define T5555_MODULATION_PSK2 0x00000020
1014#define T5555_MODULATION_PSK3 0x00000030
1015#define T5555_MODULATION_FSK1 0x00000040
1016#define T5555_MODULATION_FSK2 0x00000050
1017#define T5555_MODULATION_BIPHASE 0x00000060
1018#define T5555_MODULATION_DIRECT 0x00000070
1019#define T5555_INVERT_OUTPUT 0x00000080
1020#define T5555_PSK_RF_2 0
1021#define T5555_PSK_RF_4 0x00000100
1022#define T5555_PSK_RF_8 0x00000200
1023#define T5555_USE_PWD 0x00000400
1024#define T5555_USE_AOR 0x00000800
1025#define T5555_BITRATE_SHIFT 12
1026#define T5555_FAST_WRITE 0x00004000
1027#define T5555_PAGE_SELECT 0x00008000
1028
1029/*
1030 * Relevant times in microsecond
1031 * To compensate antenna falling times shorten the write times
1032 * and enlarge the gap ones.
1033 */
13d77ef9 1034#define START_GAP 50*8 // 10 - 50fc 250
1035#define WRITE_GAP 20*8 // - 30fc 160
1036#define WRITE_0 24*8 // 16 - 63fc 54fc 144
1037#define WRITE_1 54*8 // 48 - 63fc 54fc 432 for T55x7; 448 for E5550 //400
1038
1039#define T55xx_SAMPLES_SIZE 12000 // 32 x 32 x 10 (32 bit times numofblock (7), times clock skip..)
e09f21fa 1040
1041// Write one bit to card
1042void T55xxWriteBit(int bit)
1043{
e0165dcf 1044 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1045 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1046 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1047 if (bit == 0)
1048 SpinDelayUs(WRITE_0);
1049 else
1050 SpinDelayUs(WRITE_1);
1051 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1052 SpinDelayUs(WRITE_GAP);
e09f21fa 1053}
1054
1055// Write one card block in page 0, no lock
1056void T55xxWriteBlock(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
1057{
e0165dcf 1058 uint32_t i = 0;
1059
1060 // Set up FPGA, 125kHz
1061 // Wait for config.. (192+8190xPOW)x8 == 67ms
1062 LFSetupFPGAForADC(0, true);
1063
1064 // Now start writting
1065 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1066 SpinDelayUs(START_GAP);
1067
1068 // Opcode
1069 T55xxWriteBit(1);
1070 T55xxWriteBit(0); //Page 0
1071 if (PwdMode == 1){
1072 // Pwd
1073 for (i = 0x80000000; i != 0; i >>= 1)
1074 T55xxWriteBit(Pwd & i);
1075 }
1076 // Lock bit
1077 T55xxWriteBit(0);
1078
1079 // Data
1080 for (i = 0x80000000; i != 0; i >>= 1)
1081 T55xxWriteBit(Data & i);
1082
1083 // Block
1084 for (i = 0x04; i != 0; i >>= 1)
1085 T55xxWriteBit(Block & i);
1086
1087 // Now perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550,
1088 // so wait a little more)
1089 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1090 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1091 SpinDelay(20);
1092 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
e09f21fa 1093}
1094
13d77ef9 1095void TurnReadLFOn(){
e0165dcf 1096 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1097 // Give it a bit of time for the resonant antenna to settle.
1098 SpinDelayUs(8*150);
13d77ef9 1099}
1100
1101
e09f21fa 1102// Read one card block in page 0
1103void T55xxReadBlock(uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
1104{
e0165dcf 1105 uint32_t i = 0;
1106 uint8_t *dest = BigBuf_get_addr();
1107 uint16_t bufferlength = BigBuf_max_traceLen();
1108 if ( bufferlength > T55xx_SAMPLES_SIZE )
1109 bufferlength = T55xx_SAMPLES_SIZE;
1110
1111 // Clear destination buffer before sending the command
1112 memset(dest, 0x80, bufferlength);
1113
1114 // Set up FPGA, 125kHz
1115 // Wait for config.. (192+8190xPOW)x8 == 67ms
1116 LFSetupFPGAForADC(0, true);
1117 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1118 SpinDelayUs(START_GAP);
1119
1120 // Opcode
1121 T55xxWriteBit(1);
1122 T55xxWriteBit(0); //Page 0
1123 if (PwdMode == 1){
1124 // Pwd
1125 for (i = 0x80000000; i != 0; i >>= 1)
1126 T55xxWriteBit(Pwd & i);
1127 }
1128 // Lock bit
1129 T55xxWriteBit(0);
1130 // Block
1131 for (i = 0x04; i != 0; i >>= 1)
1132 T55xxWriteBit(Block & i);
1133
1134 // Turn field on to read the response
1135 TurnReadLFOn();
1136 // Now do the acquisition
1137 i = 0;
1138 for(;;) {
1139 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1140 AT91C_BASE_SSC->SSC_THR = 0x43;
1141 LED_D_ON();
1142 }
1143 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1144 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1145 i++;
1146 LED_D_OFF();
1147 if (i >= bufferlength) break;
1148 }
1149 }
1150
1151 cmd_send(CMD_ACK,0,0,0,0,0);
1152 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1153 LED_D_OFF();
e09f21fa 1154}
1155
1156// Read card traceability data (page 1)
1157void T55xxReadTrace(void){
e0165dcf 1158
1159 uint32_t i = 0;
1160 uint8_t *dest = BigBuf_get_addr();
1161 uint16_t bufferlength = BigBuf_max_traceLen();
1162 if ( bufferlength > T55xx_SAMPLES_SIZE )
1163 bufferlength= T55xx_SAMPLES_SIZE;
1164
1165 // Clear destination buffer before sending the command
1166 memset(dest, 0x80, bufferlength);
1167
1168 LFSetupFPGAForADC(0, true);
1169 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1170 SpinDelayUs(START_GAP);
1171
1172 // Opcode
1173 T55xxWriteBit(1);
1174 T55xxWriteBit(1); //Page 1
1175
1176 // Turn field on to read the response
1177 TurnReadLFOn();
1178
1179 // Now do the acquisition
1180 for(;;) {
1181 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1182 AT91C_BASE_SSC->SSC_THR = 0x43;
1183 LED_D_ON();
1184 }
1185 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1186 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1187 i++;
1188 LED_D_OFF();
1189
1190 if (i >= bufferlength) break;
1191 }
1192 }
1193
1194 cmd_send(CMD_ACK,0,0,0,0,0);
1195 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1196 LED_D_OFF();
e09f21fa 1197}
1198
1199/*-------------- Cloning routines -----------*/
1200// Copy HID id to card and setup block 0 config
1201void CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT)
1202{
e0165dcf 1203 int data1=0, data2=0, data3=0, data4=0, data5=0, data6=0; //up to six blocks for long format
1204 int last_block = 0;
1205
1206 if (longFMT){
1207 // Ensure no more than 84 bits supplied
1208 if (hi2>0xFFFFF) {
1209 DbpString("Tags can only have 84 bits.");
1210 return;
1211 }
1212 // Build the 6 data blocks for supplied 84bit ID
1213 last_block = 6;
1214 data1 = 0x1D96A900; // load preamble (1D) & long format identifier (9E manchester encoded)
1215 for (int i=0;i<4;i++) {
1216 if (hi2 & (1<<(19-i)))
1217 data1 |= (1<<(((3-i)*2)+1)); // 1 -> 10
1218 else
1219 data1 |= (1<<((3-i)*2)); // 0 -> 01
1220 }
1221
1222 data2 = 0;
1223 for (int i=0;i<16;i++) {
1224 if (hi2 & (1<<(15-i)))
1225 data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1226 else
1227 data2 |= (1<<((15-i)*2)); // 0 -> 01
1228 }
1229
1230 data3 = 0;
1231 for (int i=0;i<16;i++) {
1232 if (hi & (1<<(31-i)))
1233 data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1234 else
1235 data3 |= (1<<((15-i)*2)); // 0 -> 01
1236 }
1237
1238 data4 = 0;
1239 for (int i=0;i<16;i++) {
1240 if (hi & (1<<(15-i)))
1241 data4 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1242 else
1243 data4 |= (1<<((15-i)*2)); // 0 -> 01
1244 }
1245
1246 data5 = 0;
1247 for (int i=0;i<16;i++) {
1248 if (lo & (1<<(31-i)))
1249 data5 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1250 else
1251 data5 |= (1<<((15-i)*2)); // 0 -> 01
1252 }
1253
1254 data6 = 0;
1255 for (int i=0;i<16;i++) {
1256 if (lo & (1<<(15-i)))
1257 data6 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1258 else
1259 data6 |= (1<<((15-i)*2)); // 0 -> 01
1260 }
1261 }
1262 else {
1263 // Ensure no more than 44 bits supplied
1264 if (hi>0xFFF) {
1265 DbpString("Tags can only have 44 bits.");
1266 return;
1267 }
1268
1269 // Build the 3 data blocks for supplied 44bit ID
1270 last_block = 3;
1271
1272 data1 = 0x1D000000; // load preamble
1273
1274 for (int i=0;i<12;i++) {
1275 if (hi & (1<<(11-i)))
1276 data1 |= (1<<(((11-i)*2)+1)); // 1 -> 10
1277 else
1278 data1 |= (1<<((11-i)*2)); // 0 -> 01
1279 }
1280
1281 data2 = 0;
1282 for (int i=0;i<16;i++) {
1283 if (lo & (1<<(31-i)))
1284 data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1285 else
1286 data2 |= (1<<((15-i)*2)); // 0 -> 01
1287 }
1288
1289 data3 = 0;
1290 for (int i=0;i<16;i++) {
1291 if (lo & (1<<(15-i)))
1292 data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1293 else
1294 data3 |= (1<<((15-i)*2)); // 0 -> 01
1295 }
1296 }
1297
1298 LED_D_ON();
1299 // Program the data blocks for supplied ID
1300 // and the block 0 for HID format
1301 T55xxWriteBlock(data1,1,0,0);
1302 T55xxWriteBlock(data2,2,0,0);
1303 T55xxWriteBlock(data3,3,0,0);
1304
1305 if (longFMT) { // if long format there are 6 blocks
1306 T55xxWriteBlock(data4,4,0,0);
1307 T55xxWriteBlock(data5,5,0,0);
1308 T55xxWriteBlock(data6,6,0,0);
1309 }
1310
1311 // Config for HID (RF/50, FSK2a, Maxblock=3 for short/6 for long)
1312 T55xxWriteBlock(T55x7_BITRATE_RF_50 |
1313 T55x7_MODULATION_FSK2a |
1314 last_block << T55x7_MAXBLOCK_SHIFT,
1315 0,0,0);
1316
1317 LED_D_OFF();
1318
1319 DbpString("DONE!");
e09f21fa 1320}
1321
1322void CopyIOtoT55x7(uint32_t hi, uint32_t lo, uint8_t longFMT)
1323{
e0165dcf 1324 int data1=0, data2=0; //up to six blocks for long format
e09f21fa 1325
e0165dcf 1326 data1 = hi; // load preamble
1327 data2 = lo;
e09f21fa 1328
e0165dcf 1329 LED_D_ON();
1330 // Program the data blocks for supplied ID
1331 // and the block 0 for HID format
1332 T55xxWriteBlock(data1,1,0,0);
1333 T55xxWriteBlock(data2,2,0,0);
e09f21fa 1334
e0165dcf 1335 //Config Block
1336 T55xxWriteBlock(0x00147040,0,0,0);
1337 LED_D_OFF();
e09f21fa 1338
e0165dcf 1339 DbpString("DONE!");
e09f21fa 1340}
1341
1342// Define 9bit header for EM410x tags
1343#define EM410X_HEADER 0x1FF
1344#define EM410X_ID_LENGTH 40
1345
1346void WriteEM410x(uint32_t card, uint32_t id_hi, uint32_t id_lo)
1347{
e0165dcf 1348 int i, id_bit;
1349 uint64_t id = EM410X_HEADER;
1350 uint64_t rev_id = 0; // reversed ID
1351 int c_parity[4]; // column parity
1352 int r_parity = 0; // row parity
1353 uint32_t clock = 0;
1354
1355 // Reverse ID bits given as parameter (for simpler operations)
1356 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1357 if (i < 32) {
1358 rev_id = (rev_id << 1) | (id_lo & 1);
1359 id_lo >>= 1;
1360 } else {
1361 rev_id = (rev_id << 1) | (id_hi & 1);
1362 id_hi >>= 1;
1363 }
1364 }
1365
1366 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1367 id_bit = rev_id & 1;
1368
1369 if (i % 4 == 0) {
1370 // Don't write row parity bit at start of parsing
1371 if (i)
1372 id = (id << 1) | r_parity;
1373 // Start counting parity for new row
1374 r_parity = id_bit;
1375 } else {
1376 // Count row parity
1377 r_parity ^= id_bit;
1378 }
1379
1380 // First elements in column?
1381 if (i < 4)
1382 // Fill out first elements
1383 c_parity[i] = id_bit;
1384 else
1385 // Count column parity
1386 c_parity[i % 4] ^= id_bit;
1387
1388 // Insert ID bit
1389 id = (id << 1) | id_bit;
1390 rev_id >>= 1;
1391 }
1392
1393 // Insert parity bit of last row
1394 id = (id << 1) | r_parity;
1395
1396 // Fill out column parity at the end of tag
1397 for (i = 0; i < 4; ++i)
1398 id = (id << 1) | c_parity[i];
1399
1400 // Add stop bit
1401 id <<= 1;
1402
1403 Dbprintf("Started writing %s tag ...", card ? "T55x7":"T5555");
1404 LED_D_ON();
1405
1406 // Write EM410x ID
1407 T55xxWriteBlock((uint32_t)(id >> 32), 1, 0, 0);
1408 T55xxWriteBlock((uint32_t)id, 2, 0, 0);
1409
1410 // Config for EM410x (RF/64, Manchester, Maxblock=2)
1411 if (card) {
1412 // Clock rate is stored in bits 8-15 of the card value
1413 clock = (card & 0xFF00) >> 8;
1414 Dbprintf("Clock rate: %d", clock);
1415 switch (clock)
1416 {
1417 case 32:
1418 clock = T55x7_BITRATE_RF_32;
1419 break;
1420 case 16:
1421 clock = T55x7_BITRATE_RF_16;
1422 break;
1423 case 0:
1424 // A value of 0 is assumed to be 64 for backwards-compatibility
1425 // Fall through...
1426 case 64:
1427 clock = T55x7_BITRATE_RF_64;
1428 break;
1429 default:
1430 Dbprintf("Invalid clock rate: %d", clock);
1431 return;
1432 }
1433
1434 // Writing configuration for T55x7 tag
1435 T55xxWriteBlock(clock |
1436 T55x7_MODULATION_MANCHESTER |
1437 2 << T55x7_MAXBLOCK_SHIFT,
1438 0, 0, 0);
1439 }
1440 else
1441 // Writing configuration for T5555(Q5) tag
1442 T55xxWriteBlock(0x1F << T5555_BITRATE_SHIFT |
1443 T5555_MODULATION_MANCHESTER |
1444 2 << T5555_MAXBLOCK_SHIFT,
1445 0, 0, 0);
1446
1447 LED_D_OFF();
1448 Dbprintf("Tag %s written with 0x%08x%08x\n", card ? "T55x7":"T5555",
1449 (uint32_t)(id >> 32), (uint32_t)id);
e09f21fa 1450}
1451
1452// Clone Indala 64-bit tag by UID to T55x7
1453void CopyIndala64toT55x7(int hi, int lo)
1454{
1455
e0165dcf 1456 //Program the 2 data blocks for supplied 64bit UID
1457 // and the block 0 for Indala64 format
1458 T55xxWriteBlock(hi,1,0,0);
1459 T55xxWriteBlock(lo,2,0,0);
1460 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=2)
1461 T55xxWriteBlock(T55x7_BITRATE_RF_32 |
1462 T55x7_MODULATION_PSK1 |
1463 2 << T55x7_MAXBLOCK_SHIFT,
1464 0, 0, 0);
1465 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=2;Inverse data)
1466 // T5567WriteBlock(0x603E1042,0);
e09f21fa 1467
e0165dcf 1468 DbpString("DONE!");
e09f21fa 1469
1470}
1471
1472void CopyIndala224toT55x7(int uid1, int uid2, int uid3, int uid4, int uid5, int uid6, int uid7)
1473{
1474
e0165dcf 1475 //Program the 7 data blocks for supplied 224bit UID
1476 // and the block 0 for Indala224 format
1477 T55xxWriteBlock(uid1,1,0,0);
1478 T55xxWriteBlock(uid2,2,0,0);
1479 T55xxWriteBlock(uid3,3,0,0);
1480 T55xxWriteBlock(uid4,4,0,0);
1481 T55xxWriteBlock(uid5,5,0,0);
1482 T55xxWriteBlock(uid6,6,0,0);
1483 T55xxWriteBlock(uid7,7,0,0);
1484 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=7)
1485 T55xxWriteBlock(T55x7_BITRATE_RF_32 |
1486 T55x7_MODULATION_PSK1 |
1487 7 << T55x7_MAXBLOCK_SHIFT,
1488 0,0,0);
1489 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=7;Inverse data)
1490 // T5567WriteBlock(0x603E10E2,0);
1491
1492 DbpString("DONE!");
e09f21fa 1493
1494}
1495
1496
1497#define abs(x) ( ((x)<0) ? -(x) : (x) )
1498#define max(x,y) ( x<y ? y:x)
1499
1500int DemodPCF7931(uint8_t **outBlocks) {
e0165dcf 1501 uint8_t BitStream[256];
1502 uint8_t Blocks[8][16];
1503 uint8_t *GraphBuffer = BigBuf_get_addr();
1504 int GraphTraceLen = BigBuf_max_traceLen();
1505 int i, j, lastval, bitidx, half_switch;
1506 int clock = 64;
1507 int tolerance = clock / 8;
1508 int pmc, block_done;
1509 int lc, warnings = 0;
1510 int num_blocks = 0;
1511 int lmin=128, lmax=128;
1512 uint8_t dir;
e09f21fa 1513
1514 LFSetupFPGAForADC(95, true);
1515 DoAcquisition_default(0, 0);
1516
1517
e0165dcf 1518 lmin = 64;
1519 lmax = 192;
1520
1521 i = 2;
1522
1523 /* Find first local max/min */
1524 if(GraphBuffer[1] > GraphBuffer[0]) {
1525 while(i < GraphTraceLen) {
1526 if( !(GraphBuffer[i] > GraphBuffer[i-1]) && GraphBuffer[i] > lmax)
1527 break;
1528 i++;
1529 }
1530 dir = 0;
1531 }
1532 else {
1533 while(i < GraphTraceLen) {
1534 if( !(GraphBuffer[i] < GraphBuffer[i-1]) && GraphBuffer[i] < lmin)
1535 break;
1536 i++;
1537 }
1538 dir = 1;
1539 }
1540
1541 lastval = i++;
1542 half_switch = 0;
1543 pmc = 0;
1544 block_done = 0;
1545
1546 for (bitidx = 0; i < GraphTraceLen; i++)
1547 {
1548 if ( (GraphBuffer[i-1] > GraphBuffer[i] && dir == 1 && GraphBuffer[i] > lmax) || (GraphBuffer[i-1] < GraphBuffer[i] && dir == 0 && GraphBuffer[i] < lmin))
1549 {
1550 lc = i - lastval;
1551 lastval = i;
1552
1553 // Switch depending on lc length:
1554 // Tolerance is 1/8 of clock rate (arbitrary)
1555 if (abs(lc-clock/4) < tolerance) {
1556 // 16T0
1557 if((i - pmc) == lc) { /* 16T0 was previous one */
1558 /* It's a PMC ! */
1559 i += (128+127+16+32+33+16)-1;
1560 lastval = i;
1561 pmc = 0;
1562 block_done = 1;
1563 }
1564 else {
1565 pmc = i;
1566 }
1567 } else if (abs(lc-clock/2) < tolerance) {
1568 // 32TO
1569 if((i - pmc) == lc) { /* 16T0 was previous one */
1570 /* It's a PMC ! */
1571 i += (128+127+16+32+33)-1;
1572 lastval = i;
1573 pmc = 0;
1574 block_done = 1;
1575 }
1576 else if(half_switch == 1) {
1577 BitStream[bitidx++] = 0;
1578 half_switch = 0;
1579 }
1580 else
1581 half_switch++;
1582 } else if (abs(lc-clock) < tolerance) {
1583 // 64TO
1584 BitStream[bitidx++] = 1;
1585 } else {
1586 // Error
1587 warnings++;
1588 if (warnings > 10)
1589 {
1590 Dbprintf("Error: too many detection errors, aborting.");
1591 return 0;
1592 }
1593 }
1594
1595 if(block_done == 1) {
1596 if(bitidx == 128) {
1597 for(j=0; j<16; j++) {
1598 Blocks[num_blocks][j] = 128*BitStream[j*8+7]+
1599 64*BitStream[j*8+6]+
1600 32*BitStream[j*8+5]+
1601 16*BitStream[j*8+4]+
1602 8*BitStream[j*8+3]+
1603 4*BitStream[j*8+2]+
1604 2*BitStream[j*8+1]+
1605 BitStream[j*8];
1606 }
1607 num_blocks++;
1608 }
1609 bitidx = 0;
1610 block_done = 0;
1611 half_switch = 0;
1612 }
1613 if(i < GraphTraceLen)
1614 {
1615 if (GraphBuffer[i-1] > GraphBuffer[i]) dir=0;
1616 else dir = 1;
1617 }
1618 }
1619 if(bitidx==255)
1620 bitidx=0;
1621 warnings = 0;
1622 if(num_blocks == 4) break;
1623 }
1624 memcpy(outBlocks, Blocks, 16*num_blocks);
1625 return num_blocks;
e09f21fa 1626}
1627
1628int IsBlock0PCF7931(uint8_t *Block) {
e0165dcf 1629 // Assume RFU means 0 :)
1630 if((memcmp(Block, "\x00\x00\x00\x00\x00\x00\x00\x01", 8) == 0) && memcmp(Block+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) // PAC enabled
1631 return 1;
1632 if((memcmp(Block+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) && Block[7] == 0) // PAC disabled, can it *really* happen ?
1633 return 1;
1634 return 0;
e09f21fa 1635}
1636
1637int IsBlock1PCF7931(uint8_t *Block) {
e0165dcf 1638 // Assume RFU means 0 :)
1639 if(Block[10] == 0 && Block[11] == 0 && Block[12] == 0 && Block[13] == 0)
1640 if((Block[14] & 0x7f) <= 9 && Block[15] <= 9)
1641 return 1;
e09f21fa 1642
e0165dcf 1643 return 0;
e09f21fa 1644}
1645
1646#define ALLOC 16
1647
1648void ReadPCF7931() {
e0165dcf 1649 uint8_t Blocks[8][17];
1650 uint8_t tmpBlocks[4][16];
1651 int i, j, ind, ind2, n;
1652 int num_blocks = 0;
1653 int max_blocks = 8;
1654 int ident = 0;
1655 int error = 0;
1656 int tries = 0;
1657
1658 memset(Blocks, 0, 8*17*sizeof(uint8_t));
1659
1660 do {
1661 memset(tmpBlocks, 0, 4*16*sizeof(uint8_t));
1662 n = DemodPCF7931((uint8_t**)tmpBlocks);
1663 if(!n)
1664 error++;
1665 if(error==10 && num_blocks == 0) {
1666 Dbprintf("Error, no tag or bad tag");
1667 return;
1668 }
1669 else if (tries==20 || error==10) {
1670 Dbprintf("Error reading the tag");
1671 Dbprintf("Here is the partial content");
1672 goto end;
1673 }
1674
1675 for(i=0; i<n; i++)
1676 Dbprintf("(dbg) %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
1677 tmpBlocks[i][0], tmpBlocks[i][1], tmpBlocks[i][2], tmpBlocks[i][3], tmpBlocks[i][4], tmpBlocks[i][5], tmpBlocks[i][6], tmpBlocks[i][7],
1678 tmpBlocks[i][8], tmpBlocks[i][9], tmpBlocks[i][10], tmpBlocks[i][11], tmpBlocks[i][12], tmpBlocks[i][13], tmpBlocks[i][14], tmpBlocks[i][15]);
1679 if(!ident) {
1680 for(i=0; i<n; i++) {
1681 if(IsBlock0PCF7931(tmpBlocks[i])) {
1682 // Found block 0 ?
1683 if(i < n-1 && IsBlock1PCF7931(tmpBlocks[i+1])) {
1684 // Found block 1!
1685 // \o/
1686 ident = 1;
1687 memcpy(Blocks[0], tmpBlocks[i], 16);
1688 Blocks[0][ALLOC] = 1;
1689 memcpy(Blocks[1], tmpBlocks[i+1], 16);
1690 Blocks[1][ALLOC] = 1;
1691 max_blocks = max((Blocks[1][14] & 0x7f), Blocks[1][15]) + 1;
1692 // Debug print
1693 Dbprintf("(dbg) Max blocks: %d", max_blocks);
1694 num_blocks = 2;
1695 // Handle following blocks
1696 for(j=i+2, ind2=2; j!=i; j++, ind2++, num_blocks++) {
1697 if(j==n) j=0;
1698 if(j==i) break;
1699 memcpy(Blocks[ind2], tmpBlocks[j], 16);
1700 Blocks[ind2][ALLOC] = 1;
1701 }
1702 break;
1703 }
1704 }
1705 }
1706 }
1707 else {
1708 for(i=0; i<n; i++) { // Look for identical block in known blocks
1709 if(memcmp(tmpBlocks[i], "\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00", 16)) { // Block is not full of 00
1710 for(j=0; j<max_blocks; j++) {
1711 if(Blocks[j][ALLOC] == 1 && !memcmp(tmpBlocks[i], Blocks[j], 16)) {
1712 // Found an identical block
1713 for(ind=i-1,ind2=j-1; ind >= 0; ind--,ind2--) {
1714 if(ind2 < 0)
1715 ind2 = max_blocks;
1716 if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found
1717 // Dbprintf("Tmp %d -> Block %d", ind, ind2);
1718 memcpy(Blocks[ind2], tmpBlocks[ind], 16);
1719 Blocks[ind2][ALLOC] = 1;
1720 num_blocks++;
1721 if(num_blocks == max_blocks) goto end;
1722 }
1723 }
1724 for(ind=i+1,ind2=j+1; ind < n; ind++,ind2++) {
1725 if(ind2 > max_blocks)
1726 ind2 = 0;
1727 if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found
1728 // Dbprintf("Tmp %d -> Block %d", ind, ind2);
1729 memcpy(Blocks[ind2], tmpBlocks[ind], 16);
1730 Blocks[ind2][ALLOC] = 1;
1731 num_blocks++;
1732 if(num_blocks == max_blocks) goto end;
1733 }
1734 }
1735 }
1736 }
1737 }
1738 }
1739 }
1740 tries++;
1741 if (BUTTON_PRESS()) return;
1742 } while (num_blocks != max_blocks);
e09f21fa 1743 end:
e0165dcf 1744 Dbprintf("-----------------------------------------");
1745 Dbprintf("Memory content:");
1746 Dbprintf("-----------------------------------------");
1747 for(i=0; i<max_blocks; i++) {
1748 if(Blocks[i][ALLOC]==1)
1749 Dbprintf("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
1750 Blocks[i][0], Blocks[i][1], Blocks[i][2], Blocks[i][3], Blocks[i][4], Blocks[i][5], Blocks[i][6], Blocks[i][7],
1751 Blocks[i][8], Blocks[i][9], Blocks[i][10], Blocks[i][11], Blocks[i][12], Blocks[i][13], Blocks[i][14], Blocks[i][15]);
1752 else
1753 Dbprintf("<missing block %d>", i);
1754 }
1755 Dbprintf("-----------------------------------------");
1756
1757 return ;
e09f21fa 1758}
1759
1760
1761//-----------------------------------
1762// EM4469 / EM4305 routines
1763//-----------------------------------
1764#define FWD_CMD_LOGIN 0xC //including the even parity, binary mirrored
1765#define FWD_CMD_WRITE 0xA
1766#define FWD_CMD_READ 0x9
1767#define FWD_CMD_DISABLE 0x5
1768
1769
1770uint8_t forwardLink_data[64]; //array of forwarded bits
1771uint8_t * forward_ptr; //ptr for forward message preparation
1772uint8_t fwd_bit_sz; //forwardlink bit counter
1773uint8_t * fwd_write_ptr; //forwardlink bit pointer
1774
1775//====================================================================
1776// prepares command bits
1777// see EM4469 spec
1778//====================================================================
1779//--------------------------------------------------------------------
1780uint8_t Prepare_Cmd( uint8_t cmd ) {
e0165dcf 1781 //--------------------------------------------------------------------
e09f21fa 1782
e0165dcf 1783 *forward_ptr++ = 0; //start bit
1784 *forward_ptr++ = 0; //second pause for 4050 code
e09f21fa 1785
e0165dcf 1786 *forward_ptr++ = cmd;
1787 cmd >>= 1;
1788 *forward_ptr++ = cmd;
1789 cmd >>= 1;
1790 *forward_ptr++ = cmd;
1791 cmd >>= 1;
1792 *forward_ptr++ = cmd;
e09f21fa 1793
e0165dcf 1794 return 6; //return number of emited bits
e09f21fa 1795}
1796
1797//====================================================================
1798// prepares address bits
1799// see EM4469 spec
1800//====================================================================
1801
1802//--------------------------------------------------------------------
1803uint8_t Prepare_Addr( uint8_t addr ) {
e0165dcf 1804 //--------------------------------------------------------------------
e09f21fa 1805
e0165dcf 1806 register uint8_t line_parity;
e09f21fa 1807
e0165dcf 1808 uint8_t i;
1809 line_parity = 0;
1810 for(i=0;i<6;i++) {
1811 *forward_ptr++ = addr;
1812 line_parity ^= addr;
1813 addr >>= 1;
1814 }
e09f21fa 1815
e0165dcf 1816 *forward_ptr++ = (line_parity & 1);
e09f21fa 1817
e0165dcf 1818 return 7; //return number of emited bits
e09f21fa 1819}
1820
1821//====================================================================
1822// prepares data bits intreleaved with parity bits
1823// see EM4469 spec
1824//====================================================================
1825
1826//--------------------------------------------------------------------
1827uint8_t Prepare_Data( uint16_t data_low, uint16_t data_hi) {
e0165dcf 1828 //--------------------------------------------------------------------
1829
1830 register uint8_t line_parity;
1831 register uint8_t column_parity;
1832 register uint8_t i, j;
1833 register uint16_t data;
1834
1835 data = data_low;
1836 column_parity = 0;
1837
1838 for(i=0; i<4; i++) {
1839 line_parity = 0;
1840 for(j=0; j<8; j++) {
1841 line_parity ^= data;
1842 column_parity ^= (data & 1) << j;
1843 *forward_ptr++ = data;
1844 data >>= 1;
1845 }
1846 *forward_ptr++ = line_parity;
1847 if(i == 1)
1848 data = data_hi;
1849 }
1850
1851 for(j=0; j<8; j++) {
1852 *forward_ptr++ = column_parity;
1853 column_parity >>= 1;
1854 }
1855 *forward_ptr = 0;
1856
1857 return 45; //return number of emited bits
e09f21fa 1858}
1859
1860//====================================================================
1861// Forward Link send function
1862// Requires: forwarLink_data filled with valid bits (1 bit per byte)
1863// fwd_bit_count set with number of bits to be sent
1864//====================================================================
1865void SendForward(uint8_t fwd_bit_count) {
1866
e0165dcf 1867 fwd_write_ptr = forwardLink_data;
1868 fwd_bit_sz = fwd_bit_count;
1869
1870 LED_D_ON();
1871
1872 //Field on
1873 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1874 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1875 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1876
1877 // Give it a bit of time for the resonant antenna to settle.
1878 // And for the tag to fully power up
1879 SpinDelay(150);
1880
1881 // force 1st mod pulse (start gap must be longer for 4305)
1882 fwd_bit_sz--; //prepare next bit modulation
1883 fwd_write_ptr++;
1884 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1885 SpinDelayUs(55*8); //55 cycles off (8us each)for 4305
1886 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1887 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1888 SpinDelayUs(16*8); //16 cycles on (8us each)
1889
1890 // now start writting
1891 while(fwd_bit_sz-- > 0) { //prepare next bit modulation
1892 if(((*fwd_write_ptr++) & 1) == 1)
1893 SpinDelayUs(32*8); //32 cycles at 125Khz (8us each)
1894 else {
1895 //These timings work for 4469/4269/4305 (with the 55*8 above)
1896 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1897 SpinDelayUs(23*8); //16-4 cycles off (8us each)
1898 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1899 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1900 SpinDelayUs(9*8); //16 cycles on (8us each)
1901 }
1902 }
e09f21fa 1903}
1904
1905void EM4xLogin(uint32_t Password) {
1906
e0165dcf 1907 uint8_t fwd_bit_count;
e09f21fa 1908
e0165dcf 1909 forward_ptr = forwardLink_data;
1910 fwd_bit_count = Prepare_Cmd( FWD_CMD_LOGIN );
1911 fwd_bit_count += Prepare_Data( Password&0xFFFF, Password>>16 );
e09f21fa 1912
e0165dcf 1913 SendForward(fwd_bit_count);
e09f21fa 1914
e0165dcf 1915 //Wait for command to complete
1916 SpinDelay(20);
e09f21fa 1917
1918}
1919
1920void EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1921
e0165dcf 1922 uint8_t fwd_bit_count;
1923 uint8_t *dest = BigBuf_get_addr();
1924 int m=0, i=0;
1925
1926 //If password mode do login
1927 if (PwdMode == 1) EM4xLogin(Pwd);
1928
1929 forward_ptr = forwardLink_data;
1930 fwd_bit_count = Prepare_Cmd( FWD_CMD_READ );
1931 fwd_bit_count += Prepare_Addr( Address );
1932
1933 m = BigBuf_max_traceLen();
1934 // Clear destination buffer before sending the command
1935 memset(dest, 128, m);
1936 // Connect the A/D to the peak-detected low-frequency path.
1937 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1938 // Now set up the SSC to get the ADC samples that are now streaming at us.
1939 FpgaSetupSsc();
1940
1941 SendForward(fwd_bit_count);
1942
1943 // Now do the acquisition
1944 i = 0;
1945 for(;;) {
1946 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1947 AT91C_BASE_SSC->SSC_THR = 0x43;
1948 }
1949 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1950 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1951 i++;
1952 if (i >= m) break;
1953 }
1954 }
1955 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1956 LED_D_OFF();
e09f21fa 1957}
1958
1959void EM4xWriteWord(uint32_t Data, uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1960
e0165dcf 1961 uint8_t fwd_bit_count;
e09f21fa 1962
e0165dcf 1963 //If password mode do login
1964 if (PwdMode == 1) EM4xLogin(Pwd);
e09f21fa 1965
e0165dcf 1966 forward_ptr = forwardLink_data;
1967 fwd_bit_count = Prepare_Cmd( FWD_CMD_WRITE );
1968 fwd_bit_count += Prepare_Addr( Address );
1969 fwd_bit_count += Prepare_Data( Data&0xFFFF, Data>>16 );
e09f21fa 1970
e0165dcf 1971 SendForward(fwd_bit_count);
e09f21fa 1972
e0165dcf 1973 //Wait for write to complete
1974 SpinDelay(20);
1975 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1976 LED_D_OFF();
e09f21fa 1977}
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