Update fpgaloader.c
[proxmark3-svn] / armsrc / fpgaloader.c
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15c4dc5a 1//-----------------------------------------------------------------------------
bd20f8f4 2// Jonathan Westhues, April 2006
62638f87 3// iZsh <izsh at fail0verflow.com>, 2014
bd20f8f4 4//
5// This code is licensed to you under the terms of the GNU GPL, version 2 or,
6// at your option, any later version. See the LICENSE.txt file for the text of
7// the license.
8//-----------------------------------------------------------------------------
15c4dc5a 9// Routines to load the FPGA image, and then to configure the FPGA's major
10// mode once it is configured.
15c4dc5a 11//-----------------------------------------------------------------------------
add4d470 12
13#include <stdint.h>
14#include <stddef.h>
15#include <stdbool.h>
16#include "fpgaloader.h"
e30c654b 17#include "proxmark3.h"
f7e3ed82 18#include "util.h"
9ab7a6c7 19#include "string.h"
add4d470 20#include "BigBuf.h"
21#include "zlib.h"
22
23extern void Dbprintf(const char *fmt, ...);
15c4dc5a 24
e6153040 25// remember which version of the bitstream we have already downloaded to the FPGA
26static int downloaded_bitstream = FPGA_BITSTREAM_ERR;
27
28// this is where the bitstreams are located in memory:
fb228974 29extern uint8_t _binary_obj_fpga_all_bit_z_start, _binary_obj_fpga_all_bit_z_end;
30
e6153040 31static uint8_t *fpga_image_ptr = NULL;
fb228974 32static uint32_t uncompressed_bytes_cnt;
e6153040 33
34static const uint8_t _bitparse_fixed_header[] = {0x00, 0x09, 0x0f, 0xf0, 0x0f, 0xf0, 0x0f, 0xf0, 0x0f, 0xf0, 0x00, 0x00, 0x01};
e6153040 35#define FPGA_BITSTREAM_FIXED_HEADER_SIZE sizeof(_bitparse_fixed_header)
fb228974 36#define OUTPUT_BUFFER_LEN 80
37#define FPGA_INTERLEAVE_SIZE 288
e6153040 38
15c4dc5a 39//-----------------------------------------------------------------------------
40// Set up the Serial Peripheral Interface as master
41// Used to write the FPGA config word
42// May also be used to write to other SPI attached devices like an LCD
43//-----------------------------------------------------------------------------
44void SetupSpi(int mode)
45{
46 // PA10 -> SPI_NCS2 chip select (LCD)
47 // PA11 -> SPI_NCS0 chip select (FPGA)
48 // PA12 -> SPI_MISO Master-In Slave-Out
49 // PA13 -> SPI_MOSI Master-Out Slave-In
50 // PA14 -> SPI_SPCK Serial Clock
51
52 // Disable PIO control of the following pins, allows use by the SPI peripheral
53 AT91C_BASE_PIOA->PIO_PDR =
54 GPIO_NCS0 |
55 GPIO_NCS2 |
56 GPIO_MISO |
57 GPIO_MOSI |
58 GPIO_SPCK;
59
60 AT91C_BASE_PIOA->PIO_ASR =
61 GPIO_NCS0 |
62 GPIO_MISO |
63 GPIO_MOSI |
64 GPIO_SPCK;
65
66 AT91C_BASE_PIOA->PIO_BSR = GPIO_NCS2;
67
68 //enable the SPI Peripheral clock
69 AT91C_BASE_PMC->PMC_PCER = (1<<AT91C_ID_SPI);
70 // Enable SPI
71 AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SPIEN;
72
73 switch (mode) {
74 case SPI_FPGA_MODE:
75 AT91C_BASE_SPI->SPI_MR =
76 ( 0 << 24) | // Delay between chip selects (take default: 6 MCK periods)
77 (14 << 16) | // Peripheral Chip Select (selects FPGA SPI_NCS0 or PA11)
78 ( 0 << 7) | // Local Loopback Disabled
79 ( 1 << 4) | // Mode Fault Detection disabled
80 ( 0 << 2) | // Chip selects connected directly to peripheral
81 ( 0 << 1) | // Fixed Peripheral Select
82 ( 1 << 0); // Master Mode
83 AT91C_BASE_SPI->SPI_CSR[0] =
84 ( 1 << 24) | // Delay between Consecutive Transfers (32 MCK periods)
85 ( 1 << 16) | // Delay Before SPCK (1 MCK period)
86 ( 6 << 8) | // Serial Clock Baud Rate (baudrate = MCK/6 = 24Mhz/6 = 4M baud
87 ( 8 << 4) | // Bits per Transfer (16 bits)
88 ( 0 << 3) | // Chip Select inactive after transfer
89 ( 1 << 1) | // Clock Phase data captured on leading edge, changes on following edge
90 ( 0 << 0); // Clock Polarity inactive state is logic 0
91 break;
92 case SPI_LCD_MODE:
93 AT91C_BASE_SPI->SPI_MR =
94 ( 0 << 24) | // Delay between chip selects (take default: 6 MCK periods)
95 (11 << 16) | // Peripheral Chip Select (selects LCD SPI_NCS2 or PA10)
96 ( 0 << 7) | // Local Loopback Disabled
97 ( 1 << 4) | // Mode Fault Detection disabled
98 ( 0 << 2) | // Chip selects connected directly to peripheral
99 ( 0 << 1) | // Fixed Peripheral Select
100 ( 1 << 0); // Master Mode
101 AT91C_BASE_SPI->SPI_CSR[2] =
102 ( 1 << 24) | // Delay between Consecutive Transfers (32 MCK periods)
103 ( 1 << 16) | // Delay Before SPCK (1 MCK period)
104 ( 6 << 8) | // Serial Clock Baud Rate (baudrate = MCK/6 = 24Mhz/6 = 4M baud
105 ( 1 << 4) | // Bits per Transfer (9 bits)
106 ( 0 << 3) | // Chip Select inactive after transfer
107 ( 1 << 1) | // Clock Phase data captured on leading edge, changes on following edge
108 ( 0 << 0); // Clock Polarity inactive state is logic 0
109 break;
110 default: // Disable SPI
111 AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SPIDIS;
112 break;
113 }
114}
115
116//-----------------------------------------------------------------------------
117// Set up the synchronous serial port, with the one set of options that we
118// always use when we are talking to the FPGA. Both RX and TX are enabled.
119//-----------------------------------------------------------------------------
120void FpgaSetupSsc(void)
121{
122 // First configure the GPIOs, and get ourselves a clock.
123 AT91C_BASE_PIOA->PIO_ASR =
124 GPIO_SSC_FRAME |
125 GPIO_SSC_DIN |
126 GPIO_SSC_DOUT |
127 GPIO_SSC_CLK;
128 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT;
129
130 AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_SSC);
131
132 // Now set up the SSC proper, starting from a known state.
133 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST;
134
135 // RX clock comes from TX clock, RX starts when TX starts, data changes
136 // on RX clock rising edge, sampled on falling edge
137 AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(1) | SSC_CLOCK_MODE_START(1);
138
139 // 8 bits per transfer, no loopback, MSB first, 1 transfer per sync
d714d3ef 140 // pulse, no output sync
902cb3c0 141 AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(8) | AT91C_SSC_MSBF | SSC_FRAME_MODE_WORDS_PER_TRANSFER(0);
15c4dc5a 142
143 // clock comes from TK pin, no clock output, outputs change on falling
d714d3ef 144 // edge of TK, sample on rising edge of TK, start on positive-going edge of sync
902cb3c0 145 AT91C_BASE_SSC->SSC_TCMR = SSC_CLOCK_MODE_SELECT(2) | SSC_CLOCK_MODE_START(5);
15c4dc5a 146
147 // tx framing is the same as the rx framing
148 AT91C_BASE_SSC->SSC_TFMR = AT91C_BASE_SSC->SSC_RFMR;
149
150 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_RXEN | AT91C_SSC_TXEN;
151}
152
153//-----------------------------------------------------------------------------
154// Set up DMA to receive samples from the FPGA. We will use the PDC, with
155// a single buffer as a circular buffer (so that we just chain back to
156// ourselves, not to another buffer). The stuff to manipulate those buffers
157// is in apps.h, because it should be inlined, for speed.
158//-----------------------------------------------------------------------------
d19929cb 159bool FpgaSetupSscDma(uint8_t *buf, int len)
15c4dc5a 160{
e702439e 161 if (buf == NULL) return false;
d19929cb 162
7bc95e2e 163 AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTDIS; // Disable DMA Transfer
164 AT91C_BASE_PDC_SSC->PDC_RPR = (uint32_t) buf; // transfer to this memory address
165 AT91C_BASE_PDC_SSC->PDC_RCR = len; // transfer this many bytes
166 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) buf; // next transfer to same memory address
167 AT91C_BASE_PDC_SSC->PDC_RNCR = len; // ... with same number of bytes
168 AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTEN; // go!
e702439e
I
169
170 return true;
15c4dc5a 171}
172
e6153040 173
8e074056 174//----------------------------------------------------------------------------
175// Uncompress (inflate) the FPGA data. Returns one decompressed byte with
176// each call.
177//----------------------------------------------------------------------------
fb228974 178static int get_from_fpga_combined_stream(z_streamp compressed_fpga_stream, uint8_t *output_buffer)
e6153040 179{
add4d470 180 if (fpga_image_ptr == compressed_fpga_stream->next_out) { // need more data
181 compressed_fpga_stream->next_out = output_buffer;
182 compressed_fpga_stream->avail_out = OUTPUT_BUFFER_LEN;
183 fpga_image_ptr = output_buffer;
184 int res = inflate(compressed_fpga_stream, Z_SYNC_FLUSH);
e702439e 185 if (res != Z_OK)
add4d470 186 Dbprintf("inflate returned: %d, %s", res, compressed_fpga_stream->msg);
e702439e
I
187
188 if (res < 0)
25056d8b 189 return res;
add4d470 190 }
191
fb228974 192 uncompressed_bytes_cnt++;
193
add4d470 194 return *fpga_image_ptr++;
e6153040 195}
196
8e074056 197//----------------------------------------------------------------------------
198// Undo the interleaving of several FPGA config files. FPGA config files
199// are combined into one big file:
200// 288 bytes from FPGA file 1, followed by 288 bytes from FGPA file 2, etc.
201//----------------------------------------------------------------------------
fb228974 202static int get_from_fpga_stream(int bitstream_version, z_streamp compressed_fpga_stream, uint8_t *output_buffer)
203{
204 while((uncompressed_bytes_cnt / FPGA_INTERLEAVE_SIZE) % FPGA_BITSTREAM_MAX != (bitstream_version - 1)) {
205 // skip undesired data belonging to other bitstream_versions
206 get_from_fpga_combined_stream(compressed_fpga_stream, output_buffer);
207 }
208
209 return get_from_fpga_combined_stream(compressed_fpga_stream, output_buffer);
210
211}
212
213
add4d470 214static voidpf fpga_inflate_malloc(voidpf opaque, uInt items, uInt size)
e6153040 215{
add4d470 216 return BigBuf_malloc(items*size);
217}
218
219
220static void fpga_inflate_free(voidpf opaque, voidpf address)
221{
e702439e 222 BigBuf_free(); BigBuf_Clear_ext(false);
add4d470 223}
224
225
8e074056 226//----------------------------------------------------------------------------
227// Initialize decompression of the respective (HF or LF) FPGA stream
228//----------------------------------------------------------------------------
25056d8b 229static bool reset_fpga_stream(int bitstream_version, z_streamp compressed_fpga_stream, uint8_t *output_buffer)
add4d470 230{
231 uint8_t header[FPGA_BITSTREAM_FIXED_HEADER_SIZE];
add4d470 232
fb228974 233 uncompressed_bytes_cnt = 0;
234
25056d8b 235 // initialize z_stream structure for inflate:
fb228974 236 compressed_fpga_stream->next_in = &_binary_obj_fpga_all_bit_z_start;
237 compressed_fpga_stream->avail_in = &_binary_obj_fpga_all_bit_z_start - &_binary_obj_fpga_all_bit_z_end;
25056d8b 238 compressed_fpga_stream->next_out = output_buffer;
239 compressed_fpga_stream->avail_out = OUTPUT_BUFFER_LEN;
240 compressed_fpga_stream->zalloc = &fpga_inflate_malloc;
241 compressed_fpga_stream->zfree = &fpga_inflate_free;
242
8e074056 243 inflateInit2(compressed_fpga_stream, 0);
25056d8b 244
245 fpga_image_ptr = output_buffer;
add4d470 246
247 for (uint16_t i = 0; i < FPGA_BITSTREAM_FIXED_HEADER_SIZE; i++) {
fb228974 248 header[i] = get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer);
add4d470 249 }
250
251 // Check for a valid .bit file (starts with _bitparse_fixed_header)
252 if(memcmp(_bitparse_fixed_header, header, FPGA_BITSTREAM_FIXED_HEADER_SIZE) == 0) {
253 return true;
254 } else {
255 return false;
256 }
e6153040 257}
258
259
15c4dc5a 260static void DownloadFPGA_byte(unsigned char w)
261{
262#define SEND_BIT(x) { if(w & (1<<x) ) HIGH(GPIO_FPGA_DIN); else LOW(GPIO_FPGA_DIN); HIGH(GPIO_FPGA_CCLK); LOW(GPIO_FPGA_CCLK); }
263 SEND_BIT(7);
264 SEND_BIT(6);
265 SEND_BIT(5);
266 SEND_BIT(4);
267 SEND_BIT(3);
268 SEND_BIT(2);
269 SEND_BIT(1);
270 SEND_BIT(0);
271}
272
e6153040 273// Download the fpga image starting at current stream position with length FpgaImageLen bytes
fb228974 274static void DownloadFPGA(int bitstream_version, int FpgaImageLen, z_streamp compressed_fpga_stream, uint8_t *output_buffer)
15c4dc5a 275{
add4d470 276
e702439e 277 //Dbprintf("DownloadFPGA(len: %d)", FpgaImageLen);
25056d8b 278
15c4dc5a 279 int i=0;
280
281 AT91C_BASE_PIOA->PIO_OER = GPIO_FPGA_ON;
282 AT91C_BASE_PIOA->PIO_PER = GPIO_FPGA_ON;
283 HIGH(GPIO_FPGA_ON); // ensure everything is powered on
284
285 SpinDelay(50);
286
287 LED_D_ON();
288
289 // These pins are inputs
290 AT91C_BASE_PIOA->PIO_ODR =
291 GPIO_FPGA_NINIT |
292 GPIO_FPGA_DONE;
293 // PIO controls the following pins
294 AT91C_BASE_PIOA->PIO_PER =
295 GPIO_FPGA_NINIT |
296 GPIO_FPGA_DONE;
297 // Enable pull-ups
298 AT91C_BASE_PIOA->PIO_PPUER =
299 GPIO_FPGA_NINIT |
300 GPIO_FPGA_DONE;
301
302 // setup initial logic state
303 HIGH(GPIO_FPGA_NPROGRAM);
304 LOW(GPIO_FPGA_CCLK);
305 LOW(GPIO_FPGA_DIN);
306 // These pins are outputs
307 AT91C_BASE_PIOA->PIO_OER =
308 GPIO_FPGA_NPROGRAM |
309 GPIO_FPGA_CCLK |
310 GPIO_FPGA_DIN;
311
312 // enter FPGA configuration mode
313 LOW(GPIO_FPGA_NPROGRAM);
314 SpinDelay(50);
315 HIGH(GPIO_FPGA_NPROGRAM);
316
317 i=100000;
318 // wait for FPGA ready to accept data signal
319 while ((i) && ( !(AT91C_BASE_PIOA->PIO_PDSR & GPIO_FPGA_NINIT ) ) ) {
320 i--;
321 }
322
323 // crude error indicator, leave both red LEDs on and return
324 if (i==0){
325 LED_C_ON();
326 LED_D_ON();
327 return;
328 }
329
25056d8b 330 for(i = 0; i < FpgaImageLen; i++) {
fb228974 331 int b = get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer);
25056d8b 332 if (b < 0) {
333 Dbprintf("Error %d during FpgaDownload", b);
334 break;
335 }
336 DownloadFPGA_byte(b);
15c4dc5a 337 }
25056d8b 338
15c4dc5a 339 // continue to clock FPGA until ready signal goes high
340 i=100000;
341 while ( (i--) && ( !(AT91C_BASE_PIOA->PIO_PDSR & GPIO_FPGA_DONE ) ) ) {
342 HIGH(GPIO_FPGA_CCLK);
343 LOW(GPIO_FPGA_CCLK);
344 }
345 // crude error indicator, leave both red LEDs on and return
346 if (i==0){
347 LED_C_ON();
348 LED_D_ON();
349 return;
350 }
351 LED_D_OFF();
352}
353
e6153040 354
15c4dc5a 355/* Simple Xilinx .bit parser. The file starts with the fixed opaque byte sequence
356 * 00 09 0f f0 0f f0 0f f0 0f f0 00 00 01
357 * After that the format is 1 byte section type (ASCII character), 2 byte length
358 * (big endian), <length> bytes content. Except for section 'e' which has 4 bytes
359 * length.
360 */
fb228974 361static int bitparse_find_section(int bitstream_version, char section_name, unsigned int *section_length, z_streamp compressed_fpga_stream, uint8_t *output_buffer)
15c4dc5a 362{
15c4dc5a 363 int result = 0;
e6153040 364 #define MAX_FPGA_BIT_STREAM_HEADER_SEARCH 100 // maximum number of bytes to search for the requested section
365 uint16_t numbytes = 0;
366 while(numbytes < MAX_FPGA_BIT_STREAM_HEADER_SEARCH) {
fb228974 367 char current_name = get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer);
e6153040 368 numbytes++;
15c4dc5a 369 unsigned int current_length = 0;
370 if(current_name < 'a' || current_name > 'e') {
371 /* Strange section name, abort */
372 break;
373 }
374 current_length = 0;
375 switch(current_name) {
376 case 'e':
377 /* Four byte length field */
fb228974 378 current_length += get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer) << 24;
379 current_length += get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer) << 16;
e6153040 380 numbytes += 2;
15c4dc5a 381 default: /* Fall through, two byte length field */
fb228974 382 current_length += get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer) << 8;
383 current_length += get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer) << 0;
e6153040 384 numbytes += 2;
15c4dc5a 385 }
e30c654b 386
15c4dc5a 387 if(current_name != 'e' && current_length > 255) {
388 /* Maybe a parse error */
389 break;
390 }
e30c654b 391
15c4dc5a 392 if(current_name == section_name) {
393 /* Found it */
15c4dc5a 394 *section_length = current_length;
395 result = 1;
396 break;
397 }
e30c654b 398
e6153040 399 for (uint16_t i = 0; i < current_length && numbytes < MAX_FPGA_BIT_STREAM_HEADER_SEARCH; i++) {
fb228974 400 get_from_fpga_stream(bitstream_version, compressed_fpga_stream, output_buffer);
e6153040 401 numbytes++;
402 }
15c4dc5a 403 }
e30c654b 404
15c4dc5a 405 return result;
406}
407
e6153040 408
8e074056 409//----------------------------------------------------------------------------
410// Check which FPGA image is currently loaded (if any). If necessary
411// decompress and load the correct (HF or LF) image to the FPGA
412//----------------------------------------------------------------------------
7cc204bf 413void FpgaDownloadAndGo(int bitstream_version)
15c4dc5a 414{
add4d470 415 z_stream compressed_fpga_stream;
e702439e 416 uint8_t output_buffer[OUTPUT_BUFFER_LEN] = {0x00};
e6153040 417
7cc204bf 418 // check whether or not the bitstream is already loaded
e6153040 419 if (downloaded_bitstream == bitstream_version)
7cc204bf 420 return;
421
8e074056 422 // make sure that we have enough memory to decompress
e702439e 423 BigBuf_free(); BigBuf_Clear_ext(false);
8e074056 424
add4d470 425 if (!reset_fpga_stream(bitstream_version, &compressed_fpga_stream, output_buffer)) {
7cc204bf 426 return;
e6153040 427 }
25056d8b 428
add4d470 429 unsigned int bitstream_length;
fb228974 430 if(bitparse_find_section(bitstream_version, 'e', &bitstream_length, &compressed_fpga_stream, output_buffer)) {
431 DownloadFPGA(bitstream_version, bitstream_length, &compressed_fpga_stream, output_buffer);
add4d470 432 downloaded_bitstream = bitstream_version;
15c4dc5a 433 }
25056d8b 434
435 inflateEnd(&compressed_fpga_stream);
e702439e
I
436
437 // free eventually allocated BigBuf memory
438 BigBuf_free(); BigBuf_Clear_ext(false);
e6153040 439}
15c4dc5a 440
7cc204bf 441
8e074056 442//-----------------------------------------------------------------------------
443// Gather version information from FPGA image. Needs to decompress the begin
444// of the respective (HF or LF) image.
445// Note: decompression makes use of (i.e. overwrites) BigBuf[]. It is therefore
446// advisable to call this only once and store the results for later use.
447//-----------------------------------------------------------------------------
e6153040 448void FpgaGatherVersion(int bitstream_version, char *dst, int len)
15c4dc5a 449{
15c4dc5a 450 unsigned int fpga_info_len;
e702439e 451 char tempstr[40] = {0x00};
add4d470 452 z_stream compressed_fpga_stream;
e702439e 453 uint8_t output_buffer[OUTPUT_BUFFER_LEN] = {0x00};
e6153040 454
455 dst[0] = '\0';
25056d8b 456
8e074056 457 // ensure that we can allocate enough memory for decompression:
e702439e 458 BigBuf_free(); BigBuf_Clear_ext(false);
8e074056 459
e702439e 460 if (!reset_fpga_stream(bitstream_version, &compressed_fpga_stream, output_buffer))
e6153040 461 return;
e6153040 462
fb228974 463 if(bitparse_find_section(bitstream_version, 'a', &fpga_info_len, &compressed_fpga_stream, output_buffer)) {
e6153040 464 for (uint16_t i = 0; i < fpga_info_len; i++) {
fb228974 465 char c = (char)get_from_fpga_stream(bitstream_version, &compressed_fpga_stream, output_buffer);
e6153040 466 if (i < sizeof(tempstr)) {
467 tempstr[i] = c;
468 }
15c4dc5a 469 }
e6153040 470 if (!memcmp("fpga_lf", tempstr, 7))
471 strncat(dst, "LF ", len-1);
472 else if (!memcmp("fpga_hf", tempstr, 7))
473 strncat(dst, "HF ", len-1);
474 }
475 strncat(dst, "FPGA image built", len-1);
fb228974 476 if(bitparse_find_section(bitstream_version, 'b', &fpga_info_len, &compressed_fpga_stream, output_buffer)) {
e6153040 477 strncat(dst, " for ", len-1);
478 for (uint16_t i = 0; i < fpga_info_len; i++) {
fb228974 479 char c = (char)get_from_fpga_stream(bitstream_version, &compressed_fpga_stream, output_buffer);
e6153040 480 if (i < sizeof(tempstr)) {
481 tempstr[i] = c;
482 }
15c4dc5a 483 }
e6153040 484 strncat(dst, tempstr, len-1);
485 }
fb228974 486 if(bitparse_find_section(bitstream_version, 'c', &fpga_info_len, &compressed_fpga_stream, output_buffer)) {
e6153040 487 strncat(dst, " on ", len-1);
488 for (uint16_t i = 0; i < fpga_info_len; i++) {
fb228974 489 char c = (char)get_from_fpga_stream(bitstream_version, &compressed_fpga_stream, output_buffer);
e6153040 490 if (i < sizeof(tempstr)) {
491 tempstr[i] = c;
492 }
15c4dc5a 493 }
e6153040 494 strncat(dst, tempstr, len-1);
495 }
fb228974 496 if(bitparse_find_section(bitstream_version, 'd', &fpga_info_len, &compressed_fpga_stream, output_buffer)) {
e6153040 497 strncat(dst, " at ", len-1);
498 for (uint16_t i = 0; i < fpga_info_len; i++) {
fb228974 499 char c = (char)get_from_fpga_stream(bitstream_version, &compressed_fpga_stream, output_buffer);
e6153040 500 if (i < sizeof(tempstr)) {
501 tempstr[i] = c;
502 }
15c4dc5a 503 }
e6153040 504 strncat(dst, tempstr, len-1);
15c4dc5a 505 }
25056d8b 506
8e074056 507 strncat(dst, "\n", len-1);
25056d8b 508
8e074056 509 inflateEnd(&compressed_fpga_stream);
15c4dc5a 510}
511
add4d470 512
15c4dc5a 513//-----------------------------------------------------------------------------
514// Send a 16 bit command/data pair to the FPGA.
515// The bit format is: C3 C2 C1 C0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
516// where C is the 4 bit command and D is the 12 bit data
517//-----------------------------------------------------------------------------
f7e3ed82 518void FpgaSendCommand(uint16_t cmd, uint16_t v)
15c4dc5a 519{
520 SetupSpi(SPI_FPGA_MODE);
521 while ((AT91C_BASE_SPI->SPI_SR & AT91C_SPI_TXEMPTY) == 0); // wait for the transfer to complete
522 AT91C_BASE_SPI->SPI_TDR = AT91C_SPI_LASTXFER | cmd | v; // send the data
523}
524//-----------------------------------------------------------------------------
525// Write the FPGA setup word (that determines what mode the logic is in, read
526// vs. clone vs. etc.). This is now a special case of FpgaSendCommand() to
527// avoid changing this function's occurence everywhere in the source code.
528//-----------------------------------------------------------------------------
f7e3ed82 529void FpgaWriteConfWord(uint8_t v)
15c4dc5a 530{
531 FpgaSendCommand(FPGA_CMD_SET_CONFREG, v);
532}
533
534//-----------------------------------------------------------------------------
535// Set up the CMOS switches that mux the ADC: four switches, independently
536// closable, but should only close one at a time. Not an FPGA thing, but
537// the samples from the ADC always flow through the FPGA.
538//-----------------------------------------------------------------------------
f7e3ed82 539void SetAdcMuxFor(uint32_t whichGpio)
15c4dc5a 540{
541 AT91C_BASE_PIOA->PIO_OER =
542 GPIO_MUXSEL_HIPKD |
543 GPIO_MUXSEL_LOPKD |
544 GPIO_MUXSEL_LORAW |
545 GPIO_MUXSEL_HIRAW;
546
547 AT91C_BASE_PIOA->PIO_PER =
548 GPIO_MUXSEL_HIPKD |
549 GPIO_MUXSEL_LOPKD |
550 GPIO_MUXSEL_LORAW |
551 GPIO_MUXSEL_HIRAW;
552
553 LOW(GPIO_MUXSEL_HIPKD);
554 LOW(GPIO_MUXSEL_HIRAW);
555 LOW(GPIO_MUXSEL_LORAW);
556 LOW(GPIO_MUXSEL_LOPKD);
557
558 HIGH(whichGpio);
559}
e2012d1b 560
e702439e 561void Fpga_print_status(void) {
e2012d1b 562 Dbprintf("Fgpa");
e702439e
I
563 switch(downloaded_bitstream) {
564 case FPGA_BITSTREAM_HF: Dbprintf(" mode....................HF"); break;
565 case FPGA_BITSTREAM_LF: Dbprintf(" mode....................LF"); break;
566 default: Dbprintf(" mode....................%d", downloaded_bitstream); break;
567 }
e2012d1b 568}
fdcfbdcc
RAB
569
570int FpgaGetCurrent() {
571 return downloaded_bitstream;
572}
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