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(implementing suggestion #94)
[proxmark3-svn] / fpga / lo_read.v
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ba06a4b6 1//-----------------------------------------------------------------------------
2// The way that we connect things in low-frequency read mode. In this case
3// we are generating the unmodulated low frequency carrier.
4// The A/D samples at that same rate and the result is serialized.
5//
6// Jonathan Westhues, April 2006
fa57f6e1 7// iZsh <izsh at fail0verflow.com>, June 2014
ba06a4b6 8//-----------------------------------------------------------------------------
9
10module lo_read(
7cc204bf 11 input pck0, input [7:0] pck_cnt, input pck_divclk,
12 output pwr_lo, output pwr_hi,
13 output pwr_oe1, output pwr_oe2, output pwr_oe3, output pwr_oe4,
14 input [7:0] adc_d, output adc_clk,
15 output ssp_frame, output ssp_din, output ssp_clk,
b014c96d 16 output dbg,
17 input lf_field
ba06a4b6 18);
ba06a4b6 19
20reg [7:0] to_arm_shiftreg;
ba06a4b6 21
22// this task also runs at pck0 frequency (24Mhz) and is used to serialize
23// the ADC output which is then clocked into the ARM SSP.
24
7cc204bf 25// because pck_divclk always transitions when pck_cnt = 0 we use the
26// pck_div counter to sync our other signals off it
27// we read the ADC value when pck_cnt=7 and shift it out on counts 8..15
ba06a4b6 28always @(posedge pck0)
29begin
7cc204bf 30 if((pck_cnt == 8'd7) && !pck_divclk)
31 to_arm_shiftreg <= adc_d;
32 else begin
33 to_arm_shiftreg[7:1] <= to_arm_shiftreg[6:0];
ba06a4b6 34 // simulation showed a glitch occuring due to the LSB of the shifter
35 // not being set as we shift bits out
36 // this ensures the ssp_din remains low after a transfer and suppresses
37 // the glitch that would occur when the last data shifted out ended in
38 // a 1 bit and the next data shifted out started with a 0 bit
7cc204bf 39 to_arm_shiftreg[0] <= 1'b0;
ba06a4b6 40 end
41end
42
43// ADC samples on falling edge of adc_clk, data available on the rising edge
44
45// example of ssp transfer of binary value 1100101
46// start of transfer is indicated by the rise of the ssp_frame signal
47// ssp_din changes on the rising edge of the ssp_clk clock and is clocked into
48// the ARM by the falling edge of ssp_clk
49// _______________________________
50// ssp_frame__| |__
51// _______ ___ ___
52// ssp_din __| |_______| |___| |______
53// _ _ _ _ _ _ _ _ _ _
54// ssp_clk |_| |_| |_| |_| |_| |_| |_| |_| |_| |_
55
56// serialized SSP data is gated by ant_lo to suppress unwanted signal
7cc204bf 57assign ssp_din = to_arm_shiftreg[7] && !pck_divclk;
ba06a4b6 58// SSP clock always runs at 24Mhz
59assign ssp_clk = pck0;
60// SSP frame is gated by ant_lo and goes high when pck_divider=8..15
7cc204bf 61assign ssp_frame = (pck_cnt[7:3] == 5'd1) && !pck_divclk;
ba06a4b6 62// unused signals tied low
63assign pwr_hi = 1'b0;
64assign pwr_oe1 = 1'b0;
65assign pwr_oe2 = 1'b0;
66assign pwr_oe3 = 1'b0;
67assign pwr_oe4 = 1'b0;
68// this is the antenna driver signal
b014c96d 69assign pwr_lo = lf_field & pck_divclk;
ba06a4b6 70// ADC clock out of phase with antenna driver
7cc204bf 71assign adc_clk = ~pck_divclk;
ba06a4b6 72// ADC clock also routed to debug pin
73assign dbg = adc_clk;
74endmodule
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