]> git.zerfleddert.de Git - proxmark3-svn/blame - fpga/lo_edge_detect.v
fix: AVX512 detection
[proxmark3-svn] / fpga / lo_edge_detect.v
CommitLineData
d19929cb 1//-----------------------------------------------------------------------------
3b2fee43 2// Copyright (C) 2014 iZsh <izsh at fail0verflow.com>
d19929cb 3//
3b2fee43 4// This code is licensed to you under the terms of the GNU GPL, version 2 or,
5// at your option, any later version. See the LICENSE.txt file for the text of
6// the license.
d19929cb 7//-----------------------------------------------------------------------------
3b2fee43 8//
9// There are two modes:
10// - lf_ed_toggle_mode == 0: the output is set low (resp. high) when a low
11// (resp. high) edge/peak is detected, with hysteresis
12// - lf_ed_toggle_mode == 1: the output is toggling whenever an edge/peak
13// is detected.
14// That way you can detect two consecutive edges/peaks at the same level (L/H)
15//
16// Output:
17// - ssp_frame (wired to TIOA1 on the arm) for the edge detection/state
18// - ssp_clk: cross_lo
19`include "lp20khz_1MSa_iir_filter.v"
20`include "lf_edge_detect.v"
d19929cb 21
22module lo_edge_detect(
3b2fee43 23 input pck0, input pck_divclk,
24 output pwr_lo, output pwr_hi,
25 output pwr_oe1, output pwr_oe2, output pwr_oe3, output pwr_oe4,
26 input [7:0] adc_d, output adc_clk,
27 output ssp_frame, input ssp_dout, output ssp_clk,
28 input cross_lo,
29 output dbg,
30 input lf_field,
31 input lf_ed_toggle_mode, input [7:0] lf_ed_threshold
d19929cb 32);
d19929cb 33
7cc204bf 34wire tag_modulation = ssp_dout & !lf_field;
35wire reader_modulation = !ssp_dout & lf_field & pck_divclk;
d19929cb 36
37// No logic, straight through.
7843130a 38assign pwr_oe1 = 1'b0; // not used in LF mode
39assign pwr_oe3 = 1'b0; // base antenna load = 33 Ohms
40// when modulating, add another 33 Ohms and 10k Ohms in parallel:
d19929cb 41assign pwr_oe2 = tag_modulation;
7843130a 42assign pwr_oe4 = tag_modulation;
43
d19929cb 44assign ssp_clk = cross_lo;
45assign pwr_lo = reader_modulation;
46assign pwr_hi = 1'b0;
3b2fee43 47
48// filter the ADC values
49wire data_rdy;
50wire [7:0] adc_filtered;
51assign adc_clk = pck0;
52lp20khz_1MSa_iir_filter adc_filter(pck0, adc_d, data_rdy, adc_filtered);
53
54// detect edges
55wire [7:0] high_threshold, highz_threshold, lowz_threshold, low_threshold;
56wire [7:0] max, min;
57wire edge_state, edge_toggle;
58lf_edge_detect lf_ed(pck0, adc_filtered, lf_ed_threshold,
59 max, min,
60 high_threshold, highz_threshold, lowz_threshold, low_threshold,
61 edge_state, edge_toggle);
62
63assign dbg = lf_ed_toggle_mode ? edge_toggle : edge_state;
64
65assign ssp_frame = lf_ed_toggle_mode ? edge_toggle : edge_state;
d19929cb 66
67endmodule
68
Impressum, Datenschutz