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CHG: removed leftover debugging statements proxmark3.c
[proxmark3-svn] / fpga / hi_read_rx_xcorr.v
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1//-----------------------------------------------------------------------------
2//
3// Jonathan Westhues, April 2006
4//-----------------------------------------------------------------------------
5
6module hi_read_rx_xcorr(
7 pck0, ck_1356meg, ck_1356megb,
8 pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
9 adc_d, adc_clk,
10 ssp_frame, ssp_din, ssp_dout, ssp_clk,
11 cross_hi, cross_lo,
12 dbg,
13 xcorr_is_848, snoop, xcorr_quarter_freq
14);
15 input pck0, ck_1356meg, ck_1356megb;
16 output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
17 input [7:0] adc_d;
18 output adc_clk;
19 input ssp_dout;
20 output ssp_frame, ssp_din, ssp_clk;
21 input cross_hi, cross_lo;
22 output dbg;
23 input xcorr_is_848, snoop, xcorr_quarter_freq;
24
25// Carrier is steady on through this, unless we're snooping.
26assign pwr_hi = ck_1356megb & (~snoop);
27assign pwr_oe1 = 1'b0;
28assign pwr_oe2 = 1'b0;
29assign pwr_oe3 = 1'b0;
30assign pwr_oe4 = 1'b0;
31
32reg ssp_clk;
33reg ssp_frame;
34
35reg fc_div_2;
36always @(posedge ck_1356meg)
37 fc_div_2 = ~fc_div_2;
38
39reg fc_div_4;
40always @(posedge fc_div_2)
41 fc_div_4 = ~fc_div_4;
42
43reg fc_div_8;
44always @(posedge fc_div_4)
45 fc_div_8 = ~fc_div_8;
46
47reg adc_clk;
48
49always @(xcorr_is_848 or xcorr_quarter_freq or ck_1356meg)
50 if(~xcorr_quarter_freq)
51 begin
52 if(xcorr_is_848)
53 // The subcarrier frequency is fc/16; we will sample at fc, so that
54 // means the subcarrier is 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 ...
55 adc_clk <= ck_1356meg;
56 else
57 // The subcarrier frequency is fc/32; we will sample at fc/2, and
58 // the subcarrier will look identical.
59 adc_clk <= fc_div_2;
60 end
61 else
62 begin
63 if(xcorr_is_848)
64 // The subcarrier frequency is fc/64
65 adc_clk <= fc_div_4;
66 else
67 // The subcarrier frequency is fc/128
68 adc_clk <= fc_div_8;
69 end
70
71// When we're a reader, we just need to do the BPSK demod; but when we're an
72// eavesdropper, we also need to pick out the commands sent by the reader,
73// using AM. Do this the same way that we do it for the simulated tag.
74reg after_hysteresis, after_hysteresis_prev;
75reg [11:0] has_been_low_for;
76always @(negedge adc_clk)
77begin
78 if(& adc_d[7:0]) after_hysteresis <= 1'b1;
79 else if(~(| adc_d[7:0])) after_hysteresis <= 1'b0;
80
81 if(after_hysteresis)
82 begin
83 has_been_low_for <= 7'b0;
84 end
85 else
86 begin
87 if(has_been_low_for == 12'd4095)
88 begin
89 has_been_low_for <= 12'd0;
90 after_hysteresis <= 1'b1;
91 end
92 else
93 has_been_low_for <= has_been_low_for + 1;
94 end
95end
96
97// Let us report a correlation every 4 subcarrier cycles, or 4*16 samples,
98// so we need a 6-bit counter.
99reg [5:0] corr_i_cnt;
100reg [5:0] corr_q_cnt;
101// And a couple of registers in which to accumulate the correlations.
102reg signed [15:0] corr_i_accum;
103reg signed [15:0] corr_q_accum;
104reg signed [7:0] corr_i_out;
105reg signed [7:0] corr_q_out;
106
107// ADC data appears on the rising edge, so sample it on the falling edge
108always @(negedge adc_clk)
109begin
110 // These are the correlators: we correlate against in-phase and quadrature
111 // versions of our reference signal, and keep the (signed) result to
112 // send out later over the SSP.
113 if(corr_i_cnt == 7'd63)
114 begin
115 if(snoop)
116 begin
117 corr_i_out <= {corr_i_accum[12:6], after_hysteresis_prev};
118 corr_q_out <= {corr_q_accum[12:6], after_hysteresis};
119 end
120 else
121 begin
122 // Only correlations need to be delivered.
123 corr_i_out <= corr_i_accum[13:6];
124 corr_q_out <= corr_q_accum[13:6];
125 end
126
127 corr_i_accum <= adc_d;
128 corr_q_accum <= adc_d;
129 corr_q_cnt <= 4;
130 corr_i_cnt <= 0;
131 end
132 else
133 begin
134 if(corr_i_cnt[3])
135 corr_i_accum <= corr_i_accum - adc_d;
136 else
137 corr_i_accum <= corr_i_accum + adc_d;
138
139 if(corr_q_cnt[3])
140 corr_q_accum <= corr_q_accum - adc_d;
141 else
142 corr_q_accum <= corr_q_accum + adc_d;
143
144 corr_i_cnt <= corr_i_cnt + 1;
145 corr_q_cnt <= corr_q_cnt + 1;
146 end
147
148 // The logic in hi_simulate.v reports 4 samples per bit. We report two
149 // (I, Q) pairs per bit, so we should do 2 samples per pair.
150 if(corr_i_cnt == 6'd31)
151 after_hysteresis_prev <= after_hysteresis;
152
153 // Then the result from last time is serialized and send out to the ARM.
154 // We get one report each cycle, and each report is 16 bits, so the
155 // ssp_clk should be the adc_clk divided by 64/16 = 4.
156
157 if(corr_i_cnt[1:0] == 2'b10)
158 ssp_clk <= 1'b0;
159
160 if(corr_i_cnt[1:0] == 2'b00)
161 begin
162 ssp_clk <= 1'b1;
163 // Don't shift if we just loaded new data, obviously.
164 if(corr_i_cnt != 7'd0)
165 begin
166 corr_i_out[7:0] <= {corr_i_out[6:0], corr_q_out[7]};
167 corr_q_out[7:1] <= corr_q_out[6:0];
168 end
169 end
170
171 if(corr_i_cnt[5:2] == 4'b000 || corr_i_cnt[5:2] == 4'b1000)
172 ssp_frame = 1'b1;
173 else
174 ssp_frame = 1'b0;
175
176end
177
178assign ssp_din = corr_i_out[7];
179
180assign dbg = corr_i_cnt[3];
181
182// Unused.
183assign pwr_lo = 1'b0;
184
185endmodule
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