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1 | //----------------------------------------------------------------------------- | |
2 | // The way that we connect things in low-frequency read mode. In this case | |
3 | // we are generating the unmodulated low frequency carrier. | |
4 | // The A/D samples at that same rate and the result is serialized. | |
5 | // | |
6 | // Jonathan Westhues, April 2006 | |
7 | //----------------------------------------------------------------------------- | |
8 | ||
9 | module lo_read( | |
10 | pck0, ck_1356meg, ck_1356megb, | |
11 | pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4, | |
12 | adc_d, adc_clk, | |
13 | ssp_frame, ssp_din, ssp_dout, ssp_clk, | |
14 | cross_hi, cross_lo, | |
15 | dbg, | |
16 | lo_is_125khz, divisor | |
17 | ); | |
18 | input pck0, ck_1356meg, ck_1356megb; | |
19 | output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4; | |
20 | input [7:0] adc_d; | |
21 | output adc_clk; | |
22 | input ssp_dout; | |
23 | output ssp_frame, ssp_din, ssp_clk; | |
24 | input cross_hi, cross_lo; | |
25 | output dbg; | |
26 | input lo_is_125khz; // redundant signal, no longer used anywhere | |
27 | input [7:0] divisor; | |
28 | ||
29 | reg [7:0] to_arm_shiftreg; | |
30 | reg [7:0] pck_divider; | |
31 | reg ant_lo; | |
32 | ||
33 | // this task runs on the rising egde of pck0 clock (24Mhz) and creates ant_lo | |
34 | // which is high for (divisor+1) pck0 cycles and low for the same duration | |
35 | // ant_lo is therefore a 50% duty cycle clock signal with a frequency of | |
36 | // 12Mhz/(divisor+1) which drives the antenna as well as the ADC clock adc_clk | |
37 | always @(posedge pck0) | |
38 | begin | |
39 | if(pck_divider == divisor[7:0]) | |
40 | begin | |
41 | pck_divider <= 8'd0; | |
42 | ant_lo = !ant_lo; | |
43 | end | |
44 | else | |
45 | begin | |
46 | pck_divider <= pck_divider + 1; | |
47 | end | |
48 | end | |
49 | ||
50 | // this task also runs at pck0 frequency (24Mhz) and is used to serialize | |
51 | // the ADC output which is then clocked into the ARM SSP. | |
52 | ||
53 | // because ant_lo always transitions when pck_divider = 0 we use the | |
54 | // pck_divider counter to sync our other signals off it | |
55 | // we read the ADC value when pck_divider=7 and shift it out on counts 8..15 | |
56 | always @(posedge pck0) | |
57 | begin | |
58 | if((pck_divider == 8'd7) && !ant_lo) | |
59 | to_arm_shiftreg <= adc_d; | |
60 | else | |
61 | begin | |
62 | to_arm_shiftreg[7:1] <= to_arm_shiftreg[6:0]; | |
63 | // simulation showed a glitch occuring due to the LSB of the shifter | |
64 | // not being set as we shift bits out | |
65 | // this ensures the ssp_din remains low after a transfer and suppresses | |
66 | // the glitch that would occur when the last data shifted out ended in | |
67 | // a 1 bit and the next data shifted out started with a 0 bit | |
68 | to_arm_shiftreg[0] <= 1'b0; | |
69 | end | |
70 | end | |
71 | ||
72 | // ADC samples on falling edge of adc_clk, data available on the rising edge | |
73 | ||
74 | // example of ssp transfer of binary value 1100101 | |
75 | // start of transfer is indicated by the rise of the ssp_frame signal | |
76 | // ssp_din changes on the rising edge of the ssp_clk clock and is clocked into | |
77 | // the ARM by the falling edge of ssp_clk | |
78 | // _______________________________ | |
79 | // ssp_frame__| |__ | |
80 | // _______ ___ ___ | |
81 | // ssp_din __| |_______| |___| |______ | |
82 | // _ _ _ _ _ _ _ _ _ _ | |
83 | // ssp_clk |_| |_| |_| |_| |_| |_| |_| |_| |_| |_ | |
84 | ||
85 | // serialized SSP data is gated by ant_lo to suppress unwanted signal | |
86 | assign ssp_din = to_arm_shiftreg[7] && !ant_lo; | |
87 | // SSP clock always runs at 24Mhz | |
88 | assign ssp_clk = pck0; | |
89 | // SSP frame is gated by ant_lo and goes high when pck_divider=8..15 | |
90 | assign ssp_frame = (pck_divider[7:3] == 5'd1) && !ant_lo; | |
91 | // unused signals tied low | |
92 | assign pwr_hi = 1'b0; | |
93 | assign pwr_oe1 = 1'b0; | |
94 | assign pwr_oe2 = 1'b0; | |
95 | assign pwr_oe3 = 1'b0; | |
96 | assign pwr_oe4 = 1'b0; | |
97 | // this is the antenna driver signal | |
98 | assign pwr_lo = ant_lo; | |
99 | // ADC clock out of phase with antenna driver | |
100 | assign adc_clk = ~ant_lo; | |
101 | // ADC clock also routed to debug pin | |
102 | assign dbg = adc_clk; | |
103 | endmodule |