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Initial commit for the firmware. Used the 20090306_ela version as baseline.
[proxmark3-svn] / fpga / hi_read_rx_xcorr.v
... / ...
CommitLineData
1//-----------------------------------------------------------------------------\r
2//\r
3// Jonathan Westhues, April 2006\r
4//-----------------------------------------------------------------------------\r
5\r
6module hi_read_rx_xcorr(\r
7 pck0, ck_1356meg, ck_1356megb,\r
8 pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,\r
9 adc_d, adc_clk,\r
10 ssp_frame, ssp_din, ssp_dout, ssp_clk,\r
11 cross_hi, cross_lo,\r
12 dbg,\r
13 xcorr_is_848, snoop\r
14);\r
15 input pck0, ck_1356meg, ck_1356megb;\r
16 output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;\r
17 input [7:0] adc_d;\r
18 output adc_clk;\r
19 input ssp_dout;\r
20 output ssp_frame, ssp_din, ssp_clk;\r
21 input cross_hi, cross_lo;\r
22 output dbg;\r
23 input xcorr_is_848, snoop;\r
24\r
25// Carrier is steady on through this, unless we're snooping.\r
26assign pwr_hi = ck_1356megb & (~snoop);\r
27assign pwr_oe1 = 1'b0;\r
28assign pwr_oe2 = 1'b0;\r
29assign pwr_oe3 = 1'b0;\r
30assign pwr_oe4 = 1'b0;\r
31\r
32reg ssp_clk;\r
33reg ssp_frame;\r
34\r
35reg fc_div_2;\r
36always @(posedge ck_1356meg)\r
37 fc_div_2 = ~fc_div_2;\r
38\r
39reg adc_clk;\r
40\r
41always @(xcorr_is_848 or fc_div_2 or ck_1356meg)\r
42 if(xcorr_is_848)\r
43 // The subcarrier frequency is fc/16; we will sample at fc, so that \r
44 // means the subcarrier is 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 ...\r
45 adc_clk <= ck_1356meg;\r
46 else\r
47 // The subcarrier frequency is fc/32; we will sample at fc/2, and\r
48 // the subcarrier will look identical.\r
49 adc_clk <= fc_div_2;\r
50\r
51// When we're a reader, we just need to do the BPSK demod; but when we're an\r
52// eavesdropper, we also need to pick out the commands sent by the reader,\r
53// using AM. Do this the same way that we do it for the simulated tag.\r
54reg after_hysteresis, after_hysteresis_prev;\r
55reg [11:0] has_been_low_for;\r
56always @(negedge adc_clk)\r
57begin\r
58 if(& adc_d[7:0]) after_hysteresis <= 1'b1;\r
59 else if(~(| adc_d[7:0])) after_hysteresis <= 1'b0;\r
60\r
61 if(after_hysteresis)\r
62 begin\r
63 has_been_low_for <= 7'b0;\r
64 end\r
65 else\r
66 begin\r
67 if(has_been_low_for == 12'd4095)\r
68 begin\r
69 has_been_low_for <= 12'd0;\r
70 after_hysteresis <= 1'b1;\r
71 end\r
72 else\r
73 has_been_low_for <= has_been_low_for + 1;\r
74 end\r
75end\r
76\r
77// Let us report a correlation every 4 subcarrier cycles, or 4*16 samples,\r
78// so we need a 6-bit counter.\r
79reg [5:0] corr_i_cnt;\r
80reg [5:0] corr_q_cnt;\r
81// And a couple of registers in which to accumulate the correlations.\r
82reg signed [15:0] corr_i_accum;\r
83reg signed [15:0] corr_q_accum;\r
84reg signed [7:0] corr_i_out;\r
85reg signed [7:0] corr_q_out;\r
86\r
87// ADC data appears on the rising edge, so sample it on the falling edge\r
88always @(negedge adc_clk)\r
89begin\r
90 // These are the correlators: we correlate against in-phase and quadrature\r
91 // versions of our reference signal, and keep the (signed) result to\r
92 // send out later over the SSP.\r
93 if(corr_i_cnt == 7'd63)\r
94 begin\r
95 if(snoop)\r
96 begin\r
97 corr_i_out <= {corr_i_accum[12:6], after_hysteresis_prev};\r
98 corr_q_out <= {corr_q_accum[12:6], after_hysteresis};\r
99 end\r
100 else\r
101 begin\r
102 // Only correlations need to be delivered.\r
103 corr_i_out <= corr_i_accum[13:6];\r
104 corr_q_out <= corr_q_accum[13:6];\r
105 end\r
106\r
107 corr_i_accum <= adc_d;\r
108 corr_q_accum <= adc_d;\r
109 corr_q_cnt <= 4;\r
110 corr_i_cnt <= 0;\r
111 end\r
112 else\r
113 begin\r
114 if(corr_i_cnt[3])\r
115 corr_i_accum <= corr_i_accum - adc_d;\r
116 else\r
117 corr_i_accum <= corr_i_accum + adc_d;\r
118\r
119 if(corr_q_cnt[3])\r
120 corr_q_accum <= corr_q_accum - adc_d;\r
121 else\r
122 corr_q_accum <= corr_q_accum + adc_d;\r
123\r
124 corr_i_cnt <= corr_i_cnt + 1;\r
125 corr_q_cnt <= corr_q_cnt + 1;\r
126 end\r
127\r
128 // The logic in hi_simulate.v reports 4 samples per bit. We report two\r
129 // (I, Q) pairs per bit, so we should do 2 samples per pair.\r
130 if(corr_i_cnt == 6'd31)\r
131 after_hysteresis_prev <= after_hysteresis;\r
132\r
133 // Then the result from last time is serialized and send out to the ARM.\r
134 // We get one report each cycle, and each report is 16 bits, so the\r
135 // ssp_clk should be the adc_clk divided by 64/16 = 4.\r
136\r
137 if(corr_i_cnt[1:0] == 2'b10)\r
138 ssp_clk <= 1'b0;\r
139\r
140 if(corr_i_cnt[1:0] == 2'b00)\r
141 begin\r
142 ssp_clk <= 1'b1;\r
143 // Don't shift if we just loaded new data, obviously.\r
144 if(corr_i_cnt != 7'd0)\r
145 begin\r
146 corr_i_out[7:0] <= {corr_i_out[6:0], corr_q_out[7]};\r
147 corr_q_out[7:1] <= corr_q_out[6:0];\r
148 end\r
149 end\r
150\r
151 if(corr_i_cnt[5:2] == 4'b000 || corr_i_cnt[5:2] == 4'b1000)\r
152 ssp_frame = 1'b1;\r
153 else\r
154 ssp_frame = 1'b0;\r
155\r
156end\r
157\r
158assign ssp_din = corr_i_out[7];\r
159\r
160assign dbg = corr_i_cnt[3];\r
161\r
162// Unused.\r
163assign pwr_lo = 1'b0;\r
164\r
165endmodule\r
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