]>
Commit | Line | Data |
---|---|---|
1 | //----------------------------------------------------------------------------- | |
2 | // Pretend to be an ISO 14443 tag. We will do this by alternately short- | |
3 | // circuiting and open-circuiting the antenna coil, with the tri-state | |
4 | // pins. | |
5 | // | |
6 | // We communicate over the SSP, as a bitstream (i.e., might as well be | |
7 | // unframed, though we still generate the word sync signal). The output | |
8 | // (ARM -> FPGA) tells us whether to modulate or not. The input (FPGA | |
9 | // -> ARM) is us using the A/D as a fancy comparator; this is with | |
10 | // (software-added) hysteresis, to undo the high-pass filter. | |
11 | // | |
12 | // At this point only Type A is implemented. This means that we are using a | |
13 | // bit rate of 106 kbit/s, or fc/128. Oversample by 4, which ought to make | |
14 | // things practical for the ARM (fc/32, 423.8 kbits/s, ~50 kbytes/s) | |
15 | // | |
16 | // Jonathan Westhues, October 2006 | |
17 | //----------------------------------------------------------------------------- | |
18 | ||
19 | module hi_simulate( | |
20 | pck0, ck_1356meg, ck_1356megb, | |
21 | pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4, | |
22 | adc_d, adc_clk, | |
23 | ssp_frame, ssp_din, ssp_dout, ssp_clk, | |
24 | cross_hi, cross_lo, | |
25 | dbg, | |
26 | mod_type | |
27 | ); | |
28 | input pck0, ck_1356meg, ck_1356megb; | |
29 | output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4; | |
30 | input [7:0] adc_d; | |
31 | output adc_clk; | |
32 | input ssp_dout; | |
33 | output ssp_frame, ssp_din, ssp_clk; | |
34 | input cross_hi, cross_lo; | |
35 | output dbg; | |
36 | input [2:0] mod_type; | |
37 | ||
38 | // Power amp goes between LOW and tri-state, so pwr_hi (and pwr_lo) can | |
39 | // always be low. | |
40 | assign pwr_hi = 1'b0; | |
41 | assign pwr_lo = 1'b0; | |
42 | ||
43 | // The comparator with hysteresis on the output from the peak detector. | |
44 | reg after_hysteresis; | |
45 | assign adc_clk = ck_1356meg; | |
46 | ||
47 | always @(negedge adc_clk) | |
48 | begin | |
49 | if(& adc_d[7:5]) after_hysteresis = 1'b1; | |
50 | else if(~(| adc_d[7:5])) after_hysteresis = 1'b0; | |
51 | end | |
52 | ||
53 | ||
54 | // Divide 13.56 MHz by 32 to produce the SSP_CLK | |
55 | // The register is bigger to allow higher division factors of up to /128 | |
56 | reg [10:0] ssp_clk_divider; | |
57 | ||
58 | always @(posedge adc_clk) | |
59 | ssp_clk_divider <= (ssp_clk_divider + 1); | |
60 | ||
61 | reg ssp_clk; | |
62 | reg ssp_frame; | |
63 | always @(negedge adc_clk) | |
64 | begin | |
65 | //If we're in 101, we only need a new bit every 8th carrier bit (53Hz). Otherwise, get next bit at 424Khz | |
66 | if(mod_type == 3'b101) | |
67 | begin | |
68 | if(ssp_clk_divider[7:0] == 8'b00000000) | |
69 | ssp_clk <= 1'b0; | |
70 | if(ssp_clk_divider[7:0] == 8'b10000000) | |
71 | ssp_clk <= 1'b1; | |
72 | ||
73 | end | |
74 | else | |
75 | begin | |
76 | if(ssp_clk_divider[4:0] == 5'd0)//[4:0] == 5'b00000) | |
77 | ssp_clk <= 1'b1; | |
78 | if(ssp_clk_divider[4:0] == 5'd16) //[4:0] == 5'b10000) | |
79 | ssp_clk <= 1'b0; | |
80 | end | |
81 | end | |
82 | ||
83 | ||
84 | //assign ssp_clk = ssp_clk_divider[4]; | |
85 | ||
86 | // Divide SSP_CLK by 8 to produce the byte framing signal; the phase of | |
87 | // this is arbitrary, because it's just a bitstream. | |
88 | // One nasty issue, though: I can't make it work with both rx and tx at | |
89 | // once. The phase wrt ssp_clk must be changed. TODO to find out why | |
90 | // that is and make a better fix. | |
91 | reg [2:0] ssp_frame_divider_to_arm; | |
92 | always @(posedge ssp_clk) | |
93 | ssp_frame_divider_to_arm <= (ssp_frame_divider_to_arm + 1); | |
94 | reg [2:0] ssp_frame_divider_from_arm; | |
95 | always @(negedge ssp_clk) | |
96 | ssp_frame_divider_from_arm <= (ssp_frame_divider_from_arm + 1); | |
97 | ||
98 | ||
99 | ||
100 | always @(ssp_frame_divider_to_arm or ssp_frame_divider_from_arm or mod_type) | |
101 | if(mod_type == 3'b000) // not modulating, so listening, to ARM | |
102 | ssp_frame = (ssp_frame_divider_to_arm == 3'b000); | |
103 | else | |
104 | ssp_frame = (ssp_frame_divider_from_arm == 3'b000); | |
105 | ||
106 | // Synchronize up the after-hysteresis signal, to produce DIN. | |
107 | reg ssp_din; | |
108 | always @(posedge ssp_clk) | |
109 | ssp_din = after_hysteresis; | |
110 | ||
111 | // Modulating carrier frequency is fc/16, reuse ssp_clk divider for that | |
112 | reg modulating_carrier; | |
113 | always @(mod_type or ssp_clk or ssp_dout) | |
114 | if(mod_type == 3'b000) | |
115 | modulating_carrier <= 1'b0; // no modulation | |
116 | else if(mod_type == 3'b001) | |
117 | modulating_carrier <= ssp_dout ^ ssp_clk_divider[3]; // XOR means BPSK | |
118 | else if(mod_type == 3'b010) | |
119 | modulating_carrier <= ssp_dout & ssp_clk_divider[5]; // switch 212kHz subcarrier on/off | |
120 | else if(mod_type == 3'b100 || mod_type == 3'b101) | |
121 | modulating_carrier <= ssp_dout & ssp_clk_divider[4]; // switch 424kHz modulation on/off | |
122 | else | |
123 | modulating_carrier <= 1'b0; // yet unused | |
124 | ||
125 | // This one is all LF, so doesn't matter | |
126 | assign pwr_oe2 = modulating_carrier; | |
127 | ||
128 | // Toggle only one of these, since we are already producing much deeper | |
129 | // modulation than a real tag would. | |
130 | assign pwr_oe1 = modulating_carrier; | |
131 | assign pwr_oe4 = modulating_carrier; | |
132 | ||
133 | // This one is always on, so that we can watch the carrier. | |
134 | assign pwr_oe3 = 1'b0; | |
135 | ||
136 | assign dbg = modulating_carrier; | |
137 | //reg dbg; | |
138 | //always @(ssp_dout) | |
139 | // dbg <= ssp_dout; | |
140 | ||
141 | endmodule |