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iso14443a cleanup, cascade2 level working again
[proxmark3-svn] / fpga / hi_read_rx_xcorr.v
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1//-----------------------------------------------------------------------------\r
2//\r
3// Jonathan Westhues, April 2006\r
4//-----------------------------------------------------------------------------\r
5\r
6module hi_read_rx_xcorr(\r
7 pck0, ck_1356meg, ck_1356megb,\r
8 pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,\r
9 adc_d, adc_clk,\r
10 ssp_frame, ssp_din, ssp_dout, ssp_clk,\r
11 cross_hi, cross_lo,\r
12 dbg,\r
13 xcorr_is_848, snoop, xcorr_quarter_freq\r
14);\r
15 input pck0, ck_1356meg, ck_1356megb;\r
16 output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;\r
17 input [7:0] adc_d;\r
18 output adc_clk;\r
19 input ssp_dout;\r
20 output ssp_frame, ssp_din, ssp_clk;\r
21 input cross_hi, cross_lo;\r
22 output dbg;\r
23 input xcorr_is_848, snoop, xcorr_quarter_freq;\r
24\r
25// Carrier is steady on through this, unless we're snooping.\r
26assign pwr_hi = ck_1356megb & (~snoop);\r
27assign pwr_oe1 = 1'b0;\r
28assign pwr_oe2 = 1'b0;\r
29assign pwr_oe3 = 1'b0;\r
30assign pwr_oe4 = 1'b0;\r
31\r
32reg ssp_clk;\r
33reg ssp_frame;\r
34\r
35reg fc_div_2;\r
36always @(posedge ck_1356meg)\r
37 fc_div_2 = ~fc_div_2;\r
38\r
39reg fc_div_4;\r
40always @(posedge fc_div_2)\r
41 fc_div_4 = ~fc_div_4;\r
42\r
43reg fc_div_8;\r
44always @(posedge fc_div_4)\r
45 fc_div_8 = ~fc_div_8;\r
46\r
47reg adc_clk;\r
48\r
49always @(xcorr_is_848 or xcorr_quarter_freq or ck_1356meg)\r
50 if(~xcorr_quarter_freq)\r
51 begin\r
52 if(xcorr_is_848)\r
53 // The subcarrier frequency is fc/16; we will sample at fc, so that \r
54 // means the subcarrier is 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 ...\r
55 adc_clk <= ck_1356meg;\r
56 else\r
57 // The subcarrier frequency is fc/32; we will sample at fc/2, and\r
58 // the subcarrier will look identical.\r
59 adc_clk <= fc_div_2;\r
60 end\r
61 else\r
62 begin\r
63 if(xcorr_is_848)\r
64 // The subcarrier frequency is fc/64\r
65 adc_clk <= fc_div_4;\r
66 else\r
67 // The subcarrier frequency is fc/128\r
68 adc_clk <= fc_div_8;\r
69 end\r
70\r
71// When we're a reader, we just need to do the BPSK demod; but when we're an\r
72// eavesdropper, we also need to pick out the commands sent by the reader,\r
73// using AM. Do this the same way that we do it for the simulated tag.\r
74reg after_hysteresis, after_hysteresis_prev;\r
75reg [11:0] has_been_low_for;\r
76always @(negedge adc_clk)\r
77begin\r
78 if(& adc_d[7:0]) after_hysteresis <= 1'b1;\r
79 else if(~(| adc_d[7:0])) after_hysteresis <= 1'b0;\r
80\r
81 if(after_hysteresis)\r
82 begin\r
83 has_been_low_for <= 7'b0;\r
84 end\r
85 else\r
86 begin\r
87 if(has_been_low_for == 12'd4095)\r
88 begin\r
89 has_been_low_for <= 12'd0;\r
90 after_hysteresis <= 1'b1;\r
91 end\r
92 else\r
93 has_been_low_for <= has_been_low_for + 1;\r
94 end\r
95end\r
96\r
97// Let us report a correlation every 4 subcarrier cycles, or 4*16 samples,\r
98// so we need a 6-bit counter.\r
99reg [5:0] corr_i_cnt;\r
100reg [5:0] corr_q_cnt;\r
101// And a couple of registers in which to accumulate the correlations.\r
102reg signed [15:0] corr_i_accum;\r
103reg signed [15:0] corr_q_accum;\r
104reg signed [7:0] corr_i_out;\r
105reg signed [7:0] corr_q_out;\r
106\r
107// ADC data appears on the rising edge, so sample it on the falling edge\r
108always @(negedge adc_clk)\r
109begin\r
110 // These are the correlators: we correlate against in-phase and quadrature\r
111 // versions of our reference signal, and keep the (signed) result to\r
112 // send out later over the SSP.\r
113 if(corr_i_cnt == 7'd63)\r
114 begin\r
115 if(snoop)\r
116 begin\r
117 corr_i_out <= {corr_i_accum[12:6], after_hysteresis_prev};\r
118 corr_q_out <= {corr_q_accum[12:6], after_hysteresis};\r
119 end\r
120 else\r
121 begin\r
122 // Only correlations need to be delivered.\r
123 corr_i_out <= corr_i_accum[13:6];\r
124 corr_q_out <= corr_q_accum[13:6];\r
125 end\r
126\r
127 corr_i_accum <= adc_d;\r
128 corr_q_accum <= adc_d;\r
129 corr_q_cnt <= 4;\r
130 corr_i_cnt <= 0;\r
131 end\r
132 else\r
133 begin\r
134 if(corr_i_cnt[3])\r
135 corr_i_accum <= corr_i_accum - adc_d;\r
136 else\r
137 corr_i_accum <= corr_i_accum + adc_d;\r
138\r
139 if(corr_q_cnt[3])\r
140 corr_q_accum <= corr_q_accum - adc_d;\r
141 else\r
142 corr_q_accum <= corr_q_accum + adc_d;\r
143\r
144 corr_i_cnt <= corr_i_cnt + 1;\r
145 corr_q_cnt <= corr_q_cnt + 1;\r
146 end\r
147\r
148 // The logic in hi_simulate.v reports 4 samples per bit. We report two\r
149 // (I, Q) pairs per bit, so we should do 2 samples per pair.\r
150 if(corr_i_cnt == 6'd31)\r
151 after_hysteresis_prev <= after_hysteresis;\r
152\r
153 // Then the result from last time is serialized and send out to the ARM.\r
154 // We get one report each cycle, and each report is 16 bits, so the\r
155 // ssp_clk should be the adc_clk divided by 64/16 = 4.\r
156\r
157 if(corr_i_cnt[1:0] == 2'b10)\r
158 ssp_clk <= 1'b0;\r
159\r
160 if(corr_i_cnt[1:0] == 2'b00)\r
161 begin\r
162 ssp_clk <= 1'b1;\r
163 // Don't shift if we just loaded new data, obviously.\r
164 if(corr_i_cnt != 7'd0)\r
165 begin\r
166 corr_i_out[7:0] <= {corr_i_out[6:0], corr_q_out[7]};\r
167 corr_q_out[7:1] <= corr_q_out[6:0];\r
168 end\r
169 end\r
170\r
171 if(corr_i_cnt[5:2] == 4'b000 || corr_i_cnt[5:2] == 4'b1000)\r
172 ssp_frame = 1'b1;\r
173 else\r
174 ssp_frame = 1'b0;\r
175\r
176end\r
177\r
178assign ssp_din = corr_i_out[7];\r
179\r
180assign dbg = corr_i_cnt[3];\r
181\r
182// Unused.\r
183assign pwr_lo = 1'b0;\r
184\r
185endmodule\r
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