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1 | `include "fpga.v" | |
2 | ||
3 | module testbed_fpga; | |
4 | reg spck, mosi, ncs; | |
5 | wire miso; | |
6 | reg pck0i, ck_1356meg, ck_1356megb; | |
7 | wire pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4; | |
8 | reg [7:0] adc_d; | |
9 | wire adc_clk, adc_noe; | |
10 | reg ssp_dout; | |
11 | wire ssp_frame, ssp_din, ssp_clk; | |
12 | ||
13 | fpga dut( | |
14 | spck, miso, mosi, ncs, | |
15 | pck0i, ck_1356meg, ck_1356megb, | |
16 | pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4, | |
17 | adc_d, adc_clk, adc_noe, | |
18 | ssp_frame, ssp_din, ssp_dout, ssp_clk | |
19 | ); | |
20 | ||
21 | integer i; | |
22 | ||
23 | initial begin | |
24 | ||
25 | // init inputs | |
26 | #5 ncs=1; | |
27 | #5 spck = 1; | |
28 | #5 mosi = 1; | |
29 | ||
30 | #50 ncs=0; | |
31 | for (i = 0 ; i < 8 ; i = i + 1) begin | |
32 | #5 mosi = $random; | |
33 | #5 spck = 0; | |
34 | #5 spck = 1; | |
35 | end | |
36 | #5 ncs=1; | |
37 | ||
38 | #50 ncs=0; | |
39 | for (i = 0 ; i < 8 ; i = i + 1) begin | |
40 | #5 mosi = $random; | |
41 | #5 spck = 0; | |
42 | #5 spck = 1; | |
43 | end | |
44 | #5 ncs=1; | |
45 | ||
46 | #50 mosi=1; | |
47 | $finish; | |
48 | end | |
49 | ||
50 | endmodule // main |