fix hf iclass sim
[proxmark3-svn] / armsrc / iclass.c
1 //-----------------------------------------------------------------------------
2 // Gerhard de Koning Gans - May 2008
3 // Hagen Fritsch - June 2010
4 // Gerhard de Koning Gans - May 2011
5 // Gerhard de Koning Gans - June 2012 - Added iClass card and reader emulation
6 //
7 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
8 // at your option, any later version. See the LICENSE.txt file for the text of
9 // the license.
10 //-----------------------------------------------------------------------------
11 // Routines to support iClass.
12 //-----------------------------------------------------------------------------
13 // Based on ISO14443a implementation. Still in experimental phase.
14 // Contribution made during a security research at Radboud University Nijmegen
15 //
16 // Please feel free to contribute and extend iClass support!!
17 //-----------------------------------------------------------------------------
18 //
19 // FIX:
20 // ====
21 // We still have sometimes a demodulation error when snooping iClass communication.
22 // The resulting trace of a read-block-03 command may look something like this:
23 //
24 // + 22279: : 0c 03 e8 01
25 //
26 // ...with an incorrect answer...
27 //
28 // + 85: 0: TAG ff! ff! ff! ff! ff! ff! ff! ff! bb 33 bb 00 01! 0e! 04! bb !crc
29 //
30 // We still left the error signalling bytes in the traces like 0xbb
31 //
32 // A correct trace should look like this:
33 //
34 // + 21112: : 0c 03 e8 01
35 // + 85: 0: TAG ff ff ff ff ff ff ff ff ea f5
36 //
37 //-----------------------------------------------------------------------------
38
39 #include "iclass.h"
40
41 #include "proxmark3.h"
42 #include "apps.h"
43 #include "util.h"
44 #include "string.h"
45 #include "common.h"
46 #include "cmd.h"
47 #include "iso14443a.h"
48 // Needed for CRC in emulation mode;
49 // same construction as in ISO 14443;
50 // different initial value (CRC_ICLASS)
51 #include "iso14443crc.h"
52 #include "iso15693tools.h"
53 #include "protocols.h"
54 #include "optimized_cipher.h"
55 #include "usb_cdc.h" // for usb_poll_validate_length
56 #include "fpgaloader.h"
57
58 static int timeout = 4096;
59
60 //-----------------------------------------------------------------------------
61 // The software UART that receives commands from the reader, and its state
62 // variables.
63 //-----------------------------------------------------------------------------
64 static struct {
65 enum {
66 STATE_UNSYNCD,
67 STATE_START_OF_COMMUNICATION,
68 STATE_RECEIVING
69 } state;
70 uint16_t shiftReg;
71 int bitCnt;
72 int byteCnt;
73 int byteCntMax;
74 int posCnt;
75 int nOutOfCnt;
76 int OutOfCnt;
77 int syncBit;
78 int samples;
79 int highCnt;
80 int swapper;
81 int counter;
82 int bitBuffer;
83 int dropPosition;
84 uint8_t *output;
85 } Uart;
86
87 static RAMFUNC int OutOfNDecoding(int bit) {
88 //int error = 0;
89 int bitright;
90
91 if (!Uart.bitBuffer) {
92 Uart.bitBuffer = bit ^ 0xFF0;
93 return false;
94 } else {
95 Uart.bitBuffer <<= 4;
96 Uart.bitBuffer ^= bit;
97 }
98
99 /*if (Uart.swapper) {
100 Uart.output[Uart.byteCnt] = Uart.bitBuffer & 0xFF;
101 Uart.byteCnt++;
102 Uart.swapper = 0;
103 if (Uart.byteCnt > 15) { return true; }
104 }
105 else {
106 Uart.swapper = 1;
107 }*/
108
109 if (Uart.state != STATE_UNSYNCD) {
110 Uart.posCnt++;
111
112 if ((Uart.bitBuffer & Uart.syncBit) ^ Uart.syncBit) {
113 bit = 0x00;
114 } else {
115 bit = 0x01;
116 }
117 if (((Uart.bitBuffer << 1) & Uart.syncBit) ^ Uart.syncBit) {
118 bitright = 0x00;
119 } else {
120 bitright = 0x01;
121 }
122 if (bit != bitright) {
123 bit = bitright;
124 }
125
126
127 // So, now we only have to deal with *bit*, lets see...
128 if (Uart.posCnt == 1) {
129 // measurement first half bitperiod
130 if (!bit) {
131 // Drop in first half means that we are either seeing
132 // an SOF or an EOF.
133
134 if (Uart.nOutOfCnt == 1) {
135 // End of Communication
136 Uart.state = STATE_UNSYNCD;
137 Uart.highCnt = 0;
138 if (Uart.byteCnt == 0) {
139 // Its not straightforward to show single EOFs
140 // So just leave it and do not return true
141 Uart.output[0] = 0xf0;
142 Uart.byteCnt++;
143 } else {
144 return true;
145 }
146 } else if (Uart.state != STATE_START_OF_COMMUNICATION) {
147 // When not part of SOF or EOF, it is an error
148 Uart.state = STATE_UNSYNCD;
149 Uart.highCnt = 0;
150 //error = 4;
151 }
152 }
153 } else {
154 // measurement second half bitperiod
155 // Count the bitslot we are in... (ISO 15693)
156 Uart.nOutOfCnt++;
157
158 if (!bit) {
159 if (Uart.dropPosition) {
160 if (Uart.state == STATE_START_OF_COMMUNICATION) {
161 //error = 1;
162 } else {
163 //error = 7;
164 }
165 // It is an error if we already have seen a drop in current frame
166 Uart.state = STATE_UNSYNCD;
167 Uart.highCnt = 0;
168 } else {
169 Uart.dropPosition = Uart.nOutOfCnt;
170 }
171 }
172
173 Uart.posCnt = 0;
174
175
176 if (Uart.nOutOfCnt == Uart.OutOfCnt && Uart.OutOfCnt == 4) {
177 Uart.nOutOfCnt = 0;
178
179 if (Uart.state == STATE_START_OF_COMMUNICATION) {
180 if (Uart.dropPosition == 4) {
181 Uart.state = STATE_RECEIVING;
182 Uart.OutOfCnt = 256;
183 } else if (Uart.dropPosition == 3) {
184 Uart.state = STATE_RECEIVING;
185 Uart.OutOfCnt = 4;
186 //Uart.output[Uart.byteCnt] = 0xdd;
187 //Uart.byteCnt++;
188 } else {
189 Uart.state = STATE_UNSYNCD;
190 Uart.highCnt = 0;
191 }
192 Uart.dropPosition = 0;
193 } else {
194 // RECEIVING DATA
195 // 1 out of 4
196 if (!Uart.dropPosition) {
197 Uart.state = STATE_UNSYNCD;
198 Uart.highCnt = 0;
199 //error = 9;
200 } else {
201 Uart.shiftReg >>= 2;
202
203 // Swap bit order
204 Uart.dropPosition--;
205 //if (Uart.dropPosition == 1) { Uart.dropPosition = 2; }
206 //else if (Uart.dropPosition == 2) { Uart.dropPosition = 1; }
207
208 Uart.shiftReg ^= ((Uart.dropPosition & 0x03) << 6);
209 Uart.bitCnt += 2;
210 Uart.dropPosition = 0;
211
212 if (Uart.bitCnt == 8) {
213 Uart.output[Uart.byteCnt] = (Uart.shiftReg & 0xff);
214 Uart.byteCnt++;
215 Uart.bitCnt = 0;
216 Uart.shiftReg = 0;
217 }
218 }
219 }
220 } else if (Uart.nOutOfCnt == Uart.OutOfCnt) {
221 // RECEIVING DATA
222 // 1 out of 256
223 if (!Uart.dropPosition) {
224 Uart.state = STATE_UNSYNCD;
225 Uart.highCnt = 0;
226 //error = 3;
227 } else {
228 Uart.dropPosition--;
229 Uart.output[Uart.byteCnt] = (Uart.dropPosition & 0xff);
230 Uart.byteCnt++;
231 Uart.bitCnt = 0;
232 Uart.shiftReg = 0;
233 Uart.nOutOfCnt = 0;
234 Uart.dropPosition = 0;
235 }
236 }
237
238 /*if (error) {
239 Uart.output[Uart.byteCnt] = 0xAA;
240 Uart.byteCnt++;
241 Uart.output[Uart.byteCnt] = error & 0xFF;
242 Uart.byteCnt++;
243 Uart.output[Uart.byteCnt] = 0xAA;
244 Uart.byteCnt++;
245 Uart.output[Uart.byteCnt] = (Uart.bitBuffer >> 8) & 0xFF;
246 Uart.byteCnt++;
247 Uart.output[Uart.byteCnt] = Uart.bitBuffer & 0xFF;
248 Uart.byteCnt++;
249 Uart.output[Uart.byteCnt] = (Uart.syncBit >> 3) & 0xFF;
250 Uart.byteCnt++;
251 Uart.output[Uart.byteCnt] = 0xAA;
252 Uart.byteCnt++;
253 return true;
254 }*/
255 }
256
257 } else {
258 bit = Uart.bitBuffer & 0xf0;
259 bit >>= 4;
260 bit ^= 0x0F; // drops become 1s ;-)
261 if (bit) {
262 // should have been high or at least (4 * 128) / fc
263 // according to ISO this should be at least (9 * 128 + 20) / fc
264 if (Uart.highCnt == 8) {
265 // we went low, so this could be start of communication
266 // it turns out to be safer to choose a less significant
267 // syncbit... so we check whether the neighbour also represents the drop
268 Uart.posCnt = 1; // apparently we are busy with our first half bit period
269 Uart.syncBit = bit & 8;
270 Uart.samples = 3;
271 if (!Uart.syncBit) { Uart.syncBit = bit & 4; Uart.samples = 2; }
272 else if (bit & 4) { Uart.syncBit = bit & 4; Uart.samples = 2; bit <<= 2; }
273 if (!Uart.syncBit) { Uart.syncBit = bit & 2; Uart.samples = 1; }
274 else if (bit & 2) { Uart.syncBit = bit & 2; Uart.samples = 1; bit <<= 1; }
275 if (!Uart.syncBit) { Uart.syncBit = bit & 1; Uart.samples = 0;
276 if (Uart.syncBit && (Uart.bitBuffer & 8)) {
277 Uart.syncBit = 8;
278
279 // the first half bit period is expected in next sample
280 Uart.posCnt = 0;
281 Uart.samples = 3;
282 }
283 } else if (bit & 1) { Uart.syncBit = bit & 1; Uart.samples = 0; }
284
285 Uart.syncBit <<= 4;
286 Uart.state = STATE_START_OF_COMMUNICATION;
287 Uart.bitCnt = 0;
288 Uart.byteCnt = 0;
289 Uart.nOutOfCnt = 0;
290 Uart.OutOfCnt = 4; // Start at 1/4, could switch to 1/256
291 Uart.dropPosition = 0;
292 Uart.shiftReg = 0;
293 //error = 0;
294 } else {
295 Uart.highCnt = 0;
296 }
297 } else if (Uart.highCnt < 8) {
298 Uart.highCnt++;
299 }
300 }
301
302 return false;
303 }
304
305
306 //=============================================================================
307 // Manchester
308 //=============================================================================
309
310 static struct {
311 enum {
312 DEMOD_UNSYNCD,
313 DEMOD_START_OF_COMMUNICATION,
314 DEMOD_START_OF_COMMUNICATION2,
315 DEMOD_START_OF_COMMUNICATION3,
316 DEMOD_SOF_COMPLETE,
317 DEMOD_MANCHESTER_D,
318 DEMOD_MANCHESTER_E,
319 DEMOD_END_OF_COMMUNICATION,
320 DEMOD_END_OF_COMMUNICATION2,
321 DEMOD_MANCHESTER_F,
322 DEMOD_ERROR_WAIT
323 } state;
324 int bitCount;
325 int posCount;
326 int syncBit;
327 uint16_t shiftReg;
328 int buffer;
329 int buffer2;
330 int buffer3;
331 int buff;
332 int samples;
333 int len;
334 enum {
335 SUB_NONE,
336 SUB_FIRST_HALF,
337 SUB_SECOND_HALF,
338 SUB_BOTH
339 } sub;
340 uint8_t *output;
341 } Demod;
342
343 static RAMFUNC int ManchesterDecoding(int v) {
344 int bit;
345 int modulation;
346 int error = 0;
347
348 bit = Demod.buffer;
349 Demod.buffer = Demod.buffer2;
350 Demod.buffer2 = Demod.buffer3;
351 Demod.buffer3 = v;
352
353 if (Demod.buff < 3) {
354 Demod.buff++;
355 return false;
356 }
357
358 if (Demod.state==DEMOD_UNSYNCD) {
359 Demod.output[Demod.len] = 0xfa;
360 Demod.syncBit = 0;
361 //Demod.samples = 0;
362 Demod.posCount = 1; // This is the first half bit period, so after syncing handle the second part
363
364 if (bit & 0x08) {
365 Demod.syncBit = 0x08;
366 }
367
368 if (bit & 0x04) {
369 if (Demod.syncBit) {
370 bit <<= 4;
371 }
372 Demod.syncBit = 0x04;
373 }
374
375 if (bit & 0x02) {
376 if (Demod.syncBit) {
377 bit <<= 2;
378 }
379 Demod.syncBit = 0x02;
380 }
381
382 if (bit & 0x01 && Demod.syncBit) {
383 Demod.syncBit = 0x01;
384 }
385
386 if (Demod.syncBit) {
387 Demod.len = 0;
388 Demod.state = DEMOD_START_OF_COMMUNICATION;
389 Demod.sub = SUB_FIRST_HALF;
390 Demod.bitCount = 0;
391 Demod.shiftReg = 0;
392 Demod.samples = 0;
393 if (Demod.posCount) {
394 switch (Demod.syncBit) {
395 case 0x08: Demod.samples = 3; break;
396 case 0x04: Demod.samples = 2; break;
397 case 0x02: Demod.samples = 1; break;
398 case 0x01: Demod.samples = 0; break;
399 }
400 // SOF must be long burst... otherwise stay unsynced!!!
401 if (!(Demod.buffer & Demod.syncBit) || !(Demod.buffer2 & Demod.syncBit)) {
402 Demod.state = DEMOD_UNSYNCD;
403 }
404 } else {
405 // SOF must be long burst... otherwise stay unsynced!!!
406 if (!(Demod.buffer2 & Demod.syncBit) || !(Demod.buffer3 & Demod.syncBit)) {
407 Demod.state = DEMOD_UNSYNCD;
408 error = 0x88;
409 }
410
411 }
412 error = 0;
413
414 }
415 } else {
416 // state is DEMOD is in SYNC from here on.
417 modulation = bit & Demod.syncBit;
418 modulation |= ((bit << 1) ^ ((Demod.buffer & 0x08) >> 3)) & Demod.syncBit;
419
420 Demod.samples += 4;
421
422 if (Demod.posCount == 0) {
423 Demod.posCount = 1;
424 if (modulation) {
425 Demod.sub = SUB_FIRST_HALF;
426 } else {
427 Demod.sub = SUB_NONE;
428 }
429 } else {
430 Demod.posCount = 0;
431 if (modulation) {
432 if (Demod.sub == SUB_FIRST_HALF) {
433 Demod.sub = SUB_BOTH;
434 } else {
435 Demod.sub = SUB_SECOND_HALF;
436 }
437 } else if (Demod.sub == SUB_NONE) {
438 if (Demod.state == DEMOD_SOF_COMPLETE) {
439 Demod.output[Demod.len] = 0x0f;
440 Demod.len++;
441 Demod.state = DEMOD_UNSYNCD;
442 return true;
443 } else {
444 Demod.state = DEMOD_ERROR_WAIT;
445 error = 0x33;
446 }
447 }
448
449 switch(Demod.state) {
450 case DEMOD_START_OF_COMMUNICATION:
451 if (Demod.sub == SUB_BOTH) {
452 Demod.state = DEMOD_START_OF_COMMUNICATION2;
453 Demod.posCount = 1;
454 Demod.sub = SUB_NONE;
455 } else {
456 Demod.output[Demod.len] = 0xab;
457 Demod.state = DEMOD_ERROR_WAIT;
458 error = 0xd2;
459 }
460 break;
461 case DEMOD_START_OF_COMMUNICATION2:
462 if (Demod.sub == SUB_SECOND_HALF) {
463 Demod.state = DEMOD_START_OF_COMMUNICATION3;
464 } else {
465 Demod.output[Demod.len] = 0xab;
466 Demod.state = DEMOD_ERROR_WAIT;
467 error = 0xd3;
468 }
469 break;
470 case DEMOD_START_OF_COMMUNICATION3:
471 if (Demod.sub == SUB_SECOND_HALF) {
472 Demod.state = DEMOD_SOF_COMPLETE;
473 } else {
474 Demod.output[Demod.len] = 0xab;
475 Demod.state = DEMOD_ERROR_WAIT;
476 error = 0xd4;
477 }
478 break;
479 case DEMOD_SOF_COMPLETE:
480 case DEMOD_MANCHESTER_D:
481 case DEMOD_MANCHESTER_E:
482 // OPPOSITE FROM ISO14443 - 11110000 = 0 (1 in 14443)
483 // 00001111 = 1 (0 in 14443)
484 if (Demod.sub == SUB_SECOND_HALF) { // SUB_FIRST_HALF
485 Demod.bitCount++;
486 Demod.shiftReg = (Demod.shiftReg >> 1) ^ 0x100;
487 Demod.state = DEMOD_MANCHESTER_D;
488 } else if (Demod.sub == SUB_FIRST_HALF) { // SUB_SECOND_HALF
489 Demod.bitCount++;
490 Demod.shiftReg >>= 1;
491 Demod.state = DEMOD_MANCHESTER_E;
492 } else if (Demod.sub == SUB_BOTH) {
493 Demod.state = DEMOD_MANCHESTER_F;
494 } else {
495 Demod.state = DEMOD_ERROR_WAIT;
496 error = 0x55;
497 }
498 break;
499
500 case DEMOD_MANCHESTER_F:
501 // Tag response does not need to be a complete byte!
502 if (Demod.len > 0 || Demod.bitCount > 0) {
503 if (Demod.bitCount > 1) { // was > 0, do not interpret last closing bit, is part of EOF
504 Demod.shiftReg >>= (9 - Demod.bitCount); // right align data
505 Demod.output[Demod.len] = Demod.shiftReg & 0xff;
506 Demod.len++;
507 }
508
509 Demod.state = DEMOD_UNSYNCD;
510 return true;
511 } else {
512 Demod.output[Demod.len] = 0xad;
513 Demod.state = DEMOD_ERROR_WAIT;
514 error = 0x03;
515 }
516 break;
517
518 case DEMOD_ERROR_WAIT:
519 Demod.state = DEMOD_UNSYNCD;
520 break;
521
522 default:
523 Demod.output[Demod.len] = 0xdd;
524 Demod.state = DEMOD_UNSYNCD;
525 break;
526 }
527
528 if (Demod.bitCount >= 8) {
529 Demod.shiftReg >>= 1;
530 Demod.output[Demod.len] = (Demod.shiftReg & 0xff);
531 Demod.len++;
532 Demod.bitCount = 0;
533 Demod.shiftReg = 0;
534 }
535
536 if (error) {
537 Demod.output[Demod.len] = 0xBB;
538 Demod.len++;
539 Demod.output[Demod.len] = error & 0xFF;
540 Demod.len++;
541 Demod.output[Demod.len] = 0xBB;
542 Demod.len++;
543 Demod.output[Demod.len] = bit & 0xFF;
544 Demod.len++;
545 Demod.output[Demod.len] = Demod.buffer & 0xFF;
546 Demod.len++;
547 // Look harder ;-)
548 Demod.output[Demod.len] = Demod.buffer2 & 0xFF;
549 Demod.len++;
550 Demod.output[Demod.len] = Demod.syncBit & 0xFF;
551 Demod.len++;
552 Demod.output[Demod.len] = 0xBB;
553 Demod.len++;
554 return true;
555 }
556
557 }
558
559 } // end (state != UNSYNCED)
560
561 return false;
562 }
563
564 //=============================================================================
565 // Finally, a `sniffer' for iClass communication
566 // Both sides of communication!
567 //=============================================================================
568
569 //-----------------------------------------------------------------------------
570 // Record the sequence of commands sent by the reader to the tag, with
571 // triggering so that we start recording at the point that the tag is moved
572 // near the reader.
573 //-----------------------------------------------------------------------------
574 void RAMFUNC SnoopIClass(void) {
575
576 // We won't start recording the frames that we acquire until we trigger;
577 // a good trigger condition to get started is probably when we see a
578 // response from the tag.
579 //int triggered = false; // false to wait first for card
580
581 // The command (reader -> tag) that we're receiving.
582 // The length of a received command will in most cases be no more than 18 bytes.
583 // So 32 should be enough!
584 #define ICLASS_BUFFER_SIZE 32
585 uint8_t readerToTagCmd[ICLASS_BUFFER_SIZE];
586 // The response (tag -> reader) that we're receiving.
587 uint8_t tagToReaderResponse[ICLASS_BUFFER_SIZE];
588
589 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
590
591 // free all BigBuf memory
592 BigBuf_free();
593 // The DMA buffer, used to stream samples from the FPGA
594 uint8_t *dmaBuf = BigBuf_malloc(DMA_BUFFER_SIZE);
595
596 set_tracing(true);
597 clear_trace();
598 iso14a_set_trigger(false);
599
600 int lastRxCounter;
601 uint8_t *upTo;
602 int smpl;
603 int maxBehindBy = 0;
604
605 // Count of samples received so far, so that we can include timing
606 // information in the trace buffer.
607 int samples = 0;
608 rsamples = 0;
609
610 // Set up the demodulator for tag -> reader responses.
611 Demod.output = tagToReaderResponse;
612 Demod.len = 0;
613 Demod.state = DEMOD_UNSYNCD;
614
615 // Setup for the DMA.
616 FpgaSetupSsc(FPGA_MAJOR_MODE_HF_ISO14443A);
617 upTo = dmaBuf;
618 lastRxCounter = DMA_BUFFER_SIZE;
619 FpgaSetupSscDma((uint8_t *)dmaBuf, DMA_BUFFER_SIZE);
620
621 // And the reader -> tag commands
622 memset(&Uart, 0, sizeof(Uart));
623 Uart.output = readerToTagCmd;
624 Uart.byteCntMax = 32; // was 100 (greg)////////////////////////////////////////////////////////////////////////
625 Uart.state = STATE_UNSYNCD;
626
627 // And put the FPGA in the appropriate mode
628 // Signal field is off with the appropriate LED
629 LED_D_OFF();
630 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_SNIFFER);
631 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
632
633 uint32_t time_0 = GetCountSspClk();
634 uint32_t time_start = 0;
635 uint32_t time_stop = 0;
636
637 int div = 0;
638 //int div2 = 0;
639 int decbyte = 0;
640 int decbyter = 0;
641
642 // And now we loop, receiving samples.
643 for (;;) {
644 LED_A_ON();
645 WDT_HIT();
646 int behindBy = (lastRxCounter - AT91C_BASE_PDC_SSC->PDC_RCR) & (DMA_BUFFER_SIZE-1);
647 if (behindBy > maxBehindBy) {
648 maxBehindBy = behindBy;
649 if (behindBy > (9 * DMA_BUFFER_SIZE / 10)) {
650 Dbprintf("blew circular buffer! behindBy=0x%x", behindBy);
651 goto done;
652 }
653 }
654 if (behindBy < 1) continue;
655
656 LED_A_OFF();
657 smpl = upTo[0];
658 upTo++;
659 lastRxCounter -= 1;
660 if (upTo - dmaBuf > DMA_BUFFER_SIZE) {
661 upTo -= DMA_BUFFER_SIZE;
662 lastRxCounter += DMA_BUFFER_SIZE;
663 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) upTo;
664 AT91C_BASE_PDC_SSC->PDC_RNCR = DMA_BUFFER_SIZE;
665 }
666
667 //samples += 4;
668 samples += 1;
669
670 if (smpl & 0xF) {
671 decbyte ^= (1 << (3 - div));
672 }
673
674 // FOR READER SIDE COMMUMICATION...
675
676 decbyter <<= 2;
677 decbyter ^= (smpl & 0x30);
678
679 div++;
680
681 if ((div + 1) % 2 == 0) {
682 smpl = decbyter;
683 if (OutOfNDecoding((smpl & 0xF0) >> 4)) {
684 rsamples = samples - Uart.samples;
685 time_stop = (GetCountSspClk()-time_0) << 4;
686 LED_C_ON();
687
688 //if (!LogTrace(Uart.output, Uart.byteCnt, rsamples, Uart.parityBits,true)) break;
689 //if (!LogTrace(NULL, 0, Uart.endTime*16 - DELAY_READER_AIR2ARM_AS_SNIFFER, 0, true)) break;
690 uint8_t parity[MAX_PARITY_SIZE];
691 GetParity(Uart.output, Uart.byteCnt, parity);
692 LogTrace(Uart.output, Uart.byteCnt, time_start, time_stop, parity, true);
693
694 /* And ready to receive another command. */
695 Uart.state = STATE_UNSYNCD;
696 /* And also reset the demod code, which might have been */
697 /* false-triggered by the commands from the reader. */
698 Demod.state = DEMOD_UNSYNCD;
699 LED_B_OFF();
700 Uart.byteCnt = 0;
701 } else {
702 time_start = (GetCountSspClk()-time_0) << 4;
703 }
704 decbyter = 0;
705 }
706
707 if (div > 3) {
708 smpl = decbyte;
709 if (ManchesterDecoding(smpl & 0x0F)) {
710 time_stop = (GetCountSspClk()-time_0) << 4;
711
712 rsamples = samples - Demod.samples;
713 LED_B_ON();
714
715 uint8_t parity[MAX_PARITY_SIZE];
716 GetParity(Demod.output, Demod.len, parity);
717 LogTrace(Demod.output, Demod.len, time_start, time_stop, parity, false);
718
719 // And ready to receive another response.
720 memset(&Demod, 0, sizeof(Demod));
721 Demod.output = tagToReaderResponse;
722 Demod.state = DEMOD_UNSYNCD;
723 LED_C_OFF();
724 } else {
725 time_start = (GetCountSspClk()-time_0) << 4;
726 }
727
728 div = 0;
729 decbyte = 0x00;
730 }
731
732 if (BUTTON_PRESS()) {
733 DbpString("cancelled_a");
734 goto done;
735 }
736 }
737
738 DbpString("COMMAND FINISHED");
739
740 Dbprintf("%x %x %x", maxBehindBy, Uart.state, Uart.byteCnt);
741 Dbprintf("%x %x %x", Uart.byteCntMax, BigBuf_get_traceLen(), (int)Uart.output[0]);
742
743 done:
744 AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTDIS;
745 Dbprintf("%x %x %x", maxBehindBy, Uart.state, Uart.byteCnt);
746 Dbprintf("%x %x %x", Uart.byteCntMax, BigBuf_get_traceLen(), (int)Uart.output[0]);
747 LEDsoff();
748 }
749
750 void rotateCSN(uint8_t* originalCSN, uint8_t* rotatedCSN) {
751 int i;
752 for (i = 0; i < 8; i++) {
753 rotatedCSN[i] = (originalCSN[i] >> 3) | (originalCSN[(i+1)%8] << 5);
754 }
755 }
756
757 //-----------------------------------------------------------------------------
758 // Wait for commands from reader
759 // Stop when button is pressed
760 // Or return true when command is captured
761 //-----------------------------------------------------------------------------
762 static int GetIClassCommandFromReader(uint8_t *received, int *len, int maxLen) {
763 // Set FPGA mode to "simulated ISO 14443 tag", no modulation (listen
764 // only, since we are receiving, not transmitting).
765 // Signal field is off with the appropriate LED
766 LED_D_OFF();
767 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_LISTEN);
768
769 // Now run a `software UART' on the stream of incoming samples.
770 Uart.output = received;
771 Uart.byteCntMax = maxLen;
772 Uart.state = STATE_UNSYNCD;
773
774 for (;;) {
775 WDT_HIT();
776
777 if (BUTTON_PRESS()) return false;
778
779 if (AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
780 AT91C_BASE_SSC->SSC_THR = 0x00;
781 }
782 if (AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
783 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
784
785 if (OutOfNDecoding(b & 0x0f)) {
786 *len = Uart.byteCnt;
787 return true;
788 }
789 }
790 }
791 }
792
793 static uint8_t encode4Bits(const uint8_t b) {
794 uint8_t c = b & 0xF;
795 // OTA, the least significant bits first
796 // The columns are
797 // 1 - Bit value to send
798 // 2 - Reversed (big-endian)
799 // 3 - Manchester Encoded
800 // 4 - Hex values
801
802 switch(c){
803 // 1 2 3 4
804 case 15: return 0x55; // 1111 -> 1111 -> 01010101 -> 0x55
805 case 14: return 0x95; // 1110 -> 0111 -> 10010101 -> 0x95
806 case 13: return 0x65; // 1101 -> 1011 -> 01100101 -> 0x65
807 case 12: return 0xa5; // 1100 -> 0011 -> 10100101 -> 0xa5
808 case 11: return 0x59; // 1011 -> 1101 -> 01011001 -> 0x59
809 case 10: return 0x99; // 1010 -> 0101 -> 10011001 -> 0x99
810 case 9: return 0x69; // 1001 -> 1001 -> 01101001 -> 0x69
811 case 8: return 0xa9; // 1000 -> 0001 -> 10101001 -> 0xa9
812 case 7: return 0x56; // 0111 -> 1110 -> 01010110 -> 0x56
813 case 6: return 0x96; // 0110 -> 0110 -> 10010110 -> 0x96
814 case 5: return 0x66; // 0101 -> 1010 -> 01100110 -> 0x66
815 case 4: return 0xa6; // 0100 -> 0010 -> 10100110 -> 0xa6
816 case 3: return 0x5a; // 0011 -> 1100 -> 01011010 -> 0x5a
817 case 2: return 0x9a; // 0010 -> 0100 -> 10011010 -> 0x9a
818 case 1: return 0x6a; // 0001 -> 1000 -> 01101010 -> 0x6a
819 default: return 0xaa; // 0000 -> 0000 -> 10101010 -> 0xaa
820
821 }
822 }
823
824 //-----------------------------------------------------------------------------
825 // Prepare tag messages
826 //-----------------------------------------------------------------------------
827 static void CodeIClassTagAnswer(const uint8_t *cmd, int len) {
828
829 /*
830 * SOF comprises 3 parts;
831 * * An unmodulated time of 56.64 us
832 * * 24 pulses of 423.75 kHz (fc/32)
833 * * A logic 1, which starts with an unmodulated time of 18.88us
834 * followed by 8 pulses of 423.75kHz (fc/32)
835 *
836 *
837 * EOF comprises 3 parts:
838 * - A logic 0 (which starts with 8 pulses of fc/32 followed by an unmodulated
839 * time of 18.88us.
840 * - 24 pulses of fc/32
841 * - An unmodulated time of 56.64 us
842 *
843 *
844 * A logic 0 starts with 8 pulses of fc/32
845 * followed by an unmodulated time of 256/fc (~18,88us).
846 *
847 * A logic 0 starts with unmodulated time of 256/fc (~18,88us) followed by
848 * 8 pulses of fc/32 (also 18.88us)
849 *
850 * The mode FPGA_HF_SIMULATOR_MODULATE_424K_8BIT which we use to simulate tag,
851 * works like this.
852 * - A 1-bit input to the FPGA becomes 8 pulses on 423.5kHz (fc/32) (18.88us).
853 * - A 0-bit input to the FPGA becomes an unmodulated time of 18.88us
854 *
855 * In this mode the SOF can be written as 00011101 = 0x1D
856 * The EOF can be written as 10111000 = 0xb8
857 * A logic 1 is 01
858 * A logic 0 is 10
859 *
860 * */
861
862 int i;
863
864 ToSendReset();
865
866 // Send SOF
867 ToSend[++ToSendMax] = 0x1D;
868
869 for (i = 0; i < len; i++) {
870 uint8_t b = cmd[i];
871 ToSend[++ToSendMax] = encode4Bits(b & 0xF); // Least significant half
872 ToSend[++ToSendMax] = encode4Bits((b >>4) & 0xF); // Most significant half
873 }
874
875 // Send EOF
876 ToSend[++ToSendMax] = 0xB8;
877 //lastProxToAirDuration = 8*ToSendMax - 3*8 - 3*8;//Not counting zeroes in the beginning or end
878 // Convert from last byte pos to length
879 ToSendMax++;
880 }
881
882 // Only SOF
883 static void CodeIClassTagSOF() {
884 //So far a dummy implementation, not used
885 //int lastProxToAirDuration =0;
886
887 ToSendReset();
888 // Send SOF
889 ToSend[++ToSendMax] = 0x1D;
890 // lastProxToAirDuration = 8*ToSendMax - 3*8;//Not counting zeroes in the beginning
891
892 // Convert from last byte pos to length
893 ToSendMax++;
894 }
895
896 static void AppendCrc(uint8_t *data, int len) {
897 ComputeCrc14443(CRC_ICLASS, data, len, data+len, data+len+1);
898 }
899
900 static int SendIClassAnswer(uint8_t *resp, int respLen, int delay) {
901 int i = 0, d = 0;//, u = 0, d = 0;
902 uint8_t b = 0;
903
904 //FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_SIMULATOR|FPGA_HF_SIMULATOR_MODULATE_424K);
905 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_SIMULATOR | FPGA_HF_SIMULATOR_MODULATE_424K_8BIT);
906
907 AT91C_BASE_SSC->SSC_THR = 0x00;
908 FpgaSetupSsc(FPGA_MAJOR_MODE_HF_SIMULATOR);
909 while (true) {
910 if ((AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY)){
911 b = AT91C_BASE_SSC->SSC_RHR;
912 (void) b;
913 }
914 if (AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)){
915 b = 0x00;
916 if (d < delay) {
917 // send 0x00 byte (causing a 2048/13,56MHz = 151us delay)
918 d++;
919 } else {
920 if (i < respLen) {
921 b = resp[i];
922 }
923 i++;
924 }
925 AT91C_BASE_SSC->SSC_THR = b;
926 }
927
928 // if (i > respLen +4) break;
929 if (i > respLen + 1) break;
930 // send 2 more 0x00 bytes (causing a 302us delay)
931 }
932
933 return 0;
934 }
935
936
937
938 /**
939 * @brief Does the actual simulation
940 * @param csn - csn to use
941 * @param breakAfterMacReceived if true, returns after reader MAC has been received.
942 */
943 int doIClassSimulation(int simulationMode, uint8_t *reader_mac_buf) {
944
945 // free eventually allocated BigBuf memory
946 BigBuf_free_keep_EM();
947
948 State cipher_state;
949
950 uint8_t *emulator = BigBuf_get_EM_addr();
951 uint8_t *csn = emulator;
952 uint8_t sof_data[] = { 0x0F } ;
953
954 // CSN followed by two CRC bytes
955 uint8_t anticoll_data[10] = { 0 };
956 uint8_t csn_data[10] = { 0 };
957 memcpy(csn_data, csn, sizeof(csn_data));
958 Dbprintf("Simulating CSN %02x%02x%02x%02x%02x%02x%02x%02x", csn[0], csn[1], csn[2], csn[3], csn[4], csn[5], csn[6], csn[7]);
959
960 // Construct anticollision-CSN
961 rotateCSN(csn_data, anticoll_data);
962
963 // Compute CRC on both CSNs
964 AppendCrc(anticoll_data, 8);
965 AppendCrc(csn_data, 8);
966
967 uint8_t diversified_key[8] = { 0 };
968 // e-Purse
969 uint8_t card_challenge_data[8] = { 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
970 //uint8_t card_challenge_data[8] = { 0 };
971 if (simulationMode == ICLASS_SIM_MODE_FULL) {
972 // The diversified key should be stored on block 3
973 // Get the diversified key from emulator memory
974 memcpy(diversified_key, emulator + (8 * 3), 8);
975 // Card challenge, a.k.a e-purse is on block 2
976 memcpy(card_challenge_data, emulator + (8 * 2), 8);
977 // Precalculate the cipher state, feeding it the CC
978 cipher_state = opt_doTagMAC_1(card_challenge_data, diversified_key);
979 }
980 // save card challenge for sim2,4 attack
981 if (reader_mac_buf != NULL) {
982 memcpy(reader_mac_buf, card_challenge_data, 8);
983 }
984
985 int exitLoop = 0;
986 // Reader 0a
987 // Tag 0f
988 // Reader 0c
989 // Tag anticoll. CSN
990 // Reader 81 anticoll. CSN
991 // Tag CSN
992
993 uint8_t *modulated_response;
994 int modulated_response_size = 0;
995 uint8_t *trace_data = NULL;
996 int trace_data_size = 0;
997
998 // Respond SOF -- takes 1 bytes
999 uint8_t *resp_sof = BigBuf_malloc(2);
1000 int resp_sof_Len;
1001
1002 // Anticollision CSN (rotated CSN)
1003 // 22: Takes 2 bytes for SOF/EOF and 10 * 2 = 20 bytes (2 bytes/byte)
1004 uint8_t *resp_anticoll = BigBuf_malloc(22);
1005 int resp_anticoll_len;
1006
1007 // CSN (block 0)
1008 // 22: Takes 2 bytes for SOF/EOF and 10 * 2 = 20 bytes (2 bytes/byte)
1009 uint8_t *resp_csn = BigBuf_malloc(22);
1010 int resp_csn_len;
1011
1012 // configuration (block 1) picopass 2ks
1013 uint8_t *resp_conf = BigBuf_malloc(22);
1014 int resp_conf_len;
1015 uint8_t conf_data[10] = {0x12, 0xFF, 0xFF, 0xFF, 0x7F, 0x1F, 0xFF, 0x3C, 0x00, 0x00};
1016 AppendCrc(conf_data, 8);
1017
1018 // e-Purse (block 2)
1019 // 18: Takes 2 bytes for SOF/EOF and 8 * 2 = 16 bytes (2 bytes/bit)
1020 uint8_t *resp_cc = BigBuf_malloc(18);
1021 int resp_cc_len;
1022
1023 // Application Issuer Area (block 5)
1024 uint8_t *resp_aia = BigBuf_malloc(22);
1025 int resp_aia_len;
1026 uint8_t aia_data[10] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00};
1027 AppendCrc(aia_data, 8);
1028
1029 uint8_t *receivedCmd = BigBuf_malloc(MAX_FRAME_SIZE);
1030 int len;
1031
1032 // Prepare card messages
1033 ToSendMax = 0;
1034
1035 // First card answer: SOF
1036 CodeIClassTagSOF();
1037 memcpy(resp_sof, ToSend, ToSendMax);
1038 resp_sof_Len = ToSendMax;
1039
1040 // Anticollision CSN
1041 CodeIClassTagAnswer(anticoll_data, sizeof(anticoll_data));
1042 memcpy(resp_anticoll, ToSend, ToSendMax);
1043 resp_anticoll_len = ToSendMax;
1044
1045 // CSN (block 0)
1046 CodeIClassTagAnswer(csn_data, sizeof(csn_data));
1047 memcpy(resp_csn, ToSend, ToSendMax);
1048 resp_csn_len = ToSendMax;
1049
1050 // Configuration (block 1)
1051 CodeIClassTagAnswer(conf_data, sizeof(conf_data));
1052 memcpy(resp_conf, ToSend, ToSendMax);
1053 resp_conf_len = ToSendMax;
1054
1055 // e-Purse (block 2)
1056 CodeIClassTagAnswer(card_challenge_data, sizeof(card_challenge_data));
1057 memcpy(resp_cc, ToSend, ToSendMax);
1058 resp_cc_len = ToSendMax;
1059
1060 // Application Issuer Area (block 5)
1061 CodeIClassTagAnswer(aia_data, sizeof(aia_data));
1062 memcpy(resp_aia, ToSend, ToSendMax);
1063 resp_aia_len = ToSendMax;
1064
1065 //This is used for responding to READ-block commands or other data which is dynamically generated
1066 uint8_t *data_generic_trace = BigBuf_malloc(8 + 2); // 8 bytes data + 2byte CRC is max tag answer
1067 uint8_t *data_response = BigBuf_malloc( (8 + 2) * 2 + 2);
1068
1069 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_LISTEN);
1070 SpinDelay(100);
1071 StartCountSspClk();
1072 // We need to listen to the high-frequency, peak-detected path.
1073 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
1074 FpgaSetupSsc(FPGA_MAJOR_MODE_HF_ISO14443A);
1075
1076 uint32_t time_0 = GetCountSspClk();
1077 uint32_t t2r_time =0;
1078 uint32_t r2t_time =0;
1079
1080 LED_A_ON();
1081 bool buttonPressed = false;
1082 uint8_t response_delay = 1;
1083 while (!exitLoop) {
1084 WDT_HIT();
1085 response_delay = 1;
1086 LED_B_OFF();
1087 //Signal tracer
1088 // Can be used to get a trigger for an oscilloscope..
1089 LED_C_OFF();
1090
1091 if (!GetIClassCommandFromReader(receivedCmd, &len, 100)) {
1092 buttonPressed = true;
1093 break;
1094 }
1095 r2t_time = GetCountSspClk();
1096 //Signal tracer
1097 LED_C_ON();
1098
1099 // Now look at the reader command and provide appropriate responses
1100 // default is no response:
1101 modulated_response = NULL;
1102 modulated_response_size = 0;
1103 trace_data = NULL;
1104 trace_data_size = 0;
1105 if (receivedCmd[0] == ICLASS_CMD_ACTALL) {
1106 // Reader in anticollission phase
1107 modulated_response = resp_sof;
1108 modulated_response_size = resp_sof_Len;
1109 trace_data = sof_data;
1110 trace_data_size = sizeof(sof_data);
1111
1112 } else if (receivedCmd[0] == ICLASS_CMD_READ_OR_IDENTIFY && len == 1) { // identify
1113 // Reader asks for anticollission CSN
1114 modulated_response = resp_anticoll;
1115 modulated_response_size = resp_anticoll_len;
1116 trace_data = anticoll_data;
1117 trace_data_size = sizeof(anticoll_data);
1118 //DbpString("Reader requests anticollission CSN:");
1119
1120 } else if (receivedCmd[0] == ICLASS_CMD_READ_OR_IDENTIFY && len == 4) { // read block
1121 uint16_t blockNo = receivedCmd[1];
1122 if (simulationMode != ICLASS_SIM_MODE_FULL) {
1123 // provide defaults for blocks 0, 1, 2, 5
1124 switch (blockNo) {
1125 case 0: // csn (block 00)
1126 modulated_response = resp_csn;
1127 modulated_response_size = resp_csn_len;
1128 trace_data = csn_data;
1129 trace_data_size = sizeof(csn_data);
1130 break;
1131 case 1: // configuration (block 01)
1132 modulated_response = resp_conf;
1133 modulated_response_size = resp_conf_len;
1134 trace_data = conf_data;
1135 trace_data_size = sizeof(conf_data);
1136 break;
1137 case 2: // e-purse (block 02)
1138 modulated_response = resp_cc;
1139 modulated_response_size = resp_cc_len;
1140 trace_data = card_challenge_data;
1141 trace_data_size = sizeof(card_challenge_data);
1142 // set epurse of sim2,4 attack
1143 if (reader_mac_buf != NULL) {
1144 memcpy(reader_mac_buf, card_challenge_data, 8);
1145 }
1146 break;
1147 case 5: // Application Issuer Area (block 05)
1148 modulated_response = resp_aia;
1149 modulated_response_size = resp_aia_len;
1150 trace_data = aia_data;
1151 trace_data_size = sizeof(aia_data);
1152 break;
1153 // default: don't respond
1154 }
1155 } else { // use data from emulator memory
1156 memcpy(data_generic_trace, emulator + (receivedCmd[1] << 3), 8);
1157 AppendCrc(data_generic_trace, 8);
1158 trace_data = data_generic_trace;
1159 trace_data_size = 10;
1160 CodeIClassTagAnswer(trace_data, trace_data_size);
1161 memcpy(data_response, ToSend, ToSendMax);
1162 modulated_response = data_response;
1163 modulated_response_size = ToSendMax;
1164 }
1165
1166 } else if (receivedCmd[0] == ICLASS_CMD_SELECT) {
1167 // Reader selects anticollission CSN.
1168 // Tag sends the corresponding real CSN
1169 modulated_response = resp_csn;
1170 modulated_response_size = resp_csn_len;
1171 trace_data = csn_data;
1172 trace_data_size = sizeof(csn_data);
1173
1174 } else if (receivedCmd[0] == ICLASS_CMD_READCHECK_KD
1175 || receivedCmd[0] == ICLASS_CMD_READCHECK_KC) {
1176 // Read e-purse (88 02 || 18 02)
1177 modulated_response = resp_cc;
1178 modulated_response_size = resp_cc_len;
1179 trace_data = card_challenge_data;
1180 trace_data_size = sizeof(card_challenge_data);
1181 LED_B_ON();
1182
1183 } else if (receivedCmd[0] == ICLASS_CMD_CHECK) {
1184 // Reader random and reader MAC!!!
1185 if (simulationMode == ICLASS_SIM_MODE_FULL) {
1186 //NR, from reader, is in receivedCmd +1
1187 opt_doTagMAC_2(cipher_state, receivedCmd+1, data_generic_trace, diversified_key);
1188 trace_data = data_generic_trace;
1189 trace_data_size = 4;
1190 CodeIClassTagAnswer(trace_data, trace_data_size);
1191 memcpy(data_response, ToSend, ToSendMax);
1192 modulated_response = data_response;
1193 modulated_response_size = ToSendMax;
1194 response_delay = 0; //We need to hurry here... (but maybe not too much... ??)
1195 //exitLoop = true;
1196 } else { // Not fullsim, we don't respond
1197 // We do not know what to answer, so lets keep quiet
1198 if (simulationMode == ICLASS_SIM_MODE_EXIT_AFTER_MAC) {
1199 // dbprintf:ing ...
1200 Dbprintf("CSN: %02x %02x %02x %02x %02x %02x %02x %02x"
1201 ,csn[0],csn[1],csn[2],csn[3],csn[4],csn[5],csn[6],csn[7]);
1202 Dbprintf("RDR: (len=%02d): %02x %02x %02x %02x %02x %02x %02x %02x %02x",len,
1203 receivedCmd[0], receivedCmd[1], receivedCmd[2],
1204 receivedCmd[3], receivedCmd[4], receivedCmd[5],
1205 receivedCmd[6], receivedCmd[7], receivedCmd[8]);
1206 if (reader_mac_buf != NULL) {
1207 // save NR and MAC for sim 2,4
1208 memcpy(reader_mac_buf + 8, receivedCmd + 1, 8);
1209 }
1210 exitLoop = true;
1211 }
1212 }
1213
1214 } else if (receivedCmd[0] == ICLASS_CMD_HALT && len == 1) {
1215 // Reader ends the session
1216 modulated_response = resp_sof;
1217 modulated_response_size = 0;
1218 trace_data = NULL;
1219 trace_data_size = 0;
1220
1221 } else if (receivedCmd[0] == ICLASS_CMD_UPDATE && simulationMode == ICLASS_SIM_MODE_FULL) {
1222 // Probably the reader wants to update the nonce. Let's just ignore that for now.
1223 // OBS! If this is implemented, don't forget to regenerate the cipher_state
1224 // We're expected to respond with the data+crc, exactly what's already in the receivedCmd
1225 // receivedCmd is now UPDATE 1b | ADDRESS 1b | DATA 8b | Signature 4b or CRC 2b
1226
1227 //Take the data...
1228 memcpy(data_generic_trace, receivedCmd + 2, 8);
1229 //Add crc
1230 AppendCrc(data_generic_trace, 8);
1231 trace_data = data_generic_trace;
1232 trace_data_size = 10;
1233 CodeIClassTagAnswer(trace_data, trace_data_size);
1234 memcpy(data_response, ToSend, ToSendMax);
1235 modulated_response = data_response;
1236 modulated_response_size = ToSendMax;
1237
1238 } else if (receivedCmd[0] == ICLASS_CMD_PAGESEL) {
1239 // Pagesel
1240 // Pagesel enables to select a page in the selected chip memory and return its configuration block
1241 // Chips with a single page will not answer to this command
1242 // It appears we're fine ignoring this.
1243 // Otherwise, we should answer 8bytes (block) + 2bytes CRC
1244
1245 } else {
1246 //#db# Unknown command received from reader (len=5): 26 1 0 f6 a 44 44 44 44
1247 // Never seen this command before
1248 print_result("Unhandled command received from reader ", receivedCmd, len);
1249 // Do not respond
1250 }
1251
1252 /**
1253 A legit tag has about 330us delay between reader EOT and tag SOF.
1254 **/
1255 if (modulated_response_size > 0) {
1256 SendIClassAnswer(modulated_response, modulated_response_size, response_delay);
1257 t2r_time = GetCountSspClk();
1258 }
1259
1260 uint8_t parity[MAX_PARITY_SIZE];
1261 GetParity(receivedCmd, len, parity);
1262 LogTrace(receivedCmd, len, (r2t_time-time_0) << 4, (r2t_time-time_0) << 4, parity, true);
1263
1264 if (trace_data != NULL) {
1265 GetParity(trace_data, trace_data_size, parity);
1266 LogTrace(trace_data, trace_data_size, (t2r_time-time_0) << 4, (t2r_time-time_0) << 4, parity, false);
1267 }
1268 if (!get_tracing()) {
1269 DbpString("Trace full");
1270 //break;
1271 }
1272 }
1273
1274 LED_A_OFF();
1275 LED_B_OFF();
1276 LED_C_OFF();
1277
1278 if (buttonPressed)
1279 {
1280 DbpString("Button pressed");
1281 }
1282 return buttonPressed;
1283 }
1284
1285 /**
1286 * @brief SimulateIClass simulates an iClass card.
1287 * @param arg0 type of simulation
1288 * - 0 uses the first 8 bytes in usb data as CSN
1289 * - 2 "dismantling iclass"-attack. This mode iterates through all CSN's specified
1290 * in the usb data. This mode collects MAC from the reader, in order to do an offline
1291 * attack on the keys. For more info, see "dismantling iclass" and proxclone.com.
1292 * - Other : Uses the default CSN (031fec8af7ff12e0)
1293 * @param arg1 - number of CSN's contained in datain (applicable for mode 2 only)
1294 * @param arg2
1295 * @param datain
1296 */
1297 void SimulateIClass(uint32_t arg0, uint32_t arg1, uint32_t arg2, uint8_t *datain) {
1298 uint32_t simType = arg0;
1299 uint32_t numberOfCSNS = arg1;
1300
1301 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
1302
1303 // Enable and clear the trace
1304 set_tracing(true);
1305 clear_trace();
1306 //Use the emulator memory for SIM
1307 uint8_t *emulator = BigBuf_get_EM_addr();
1308
1309 if (simType == ICLASS_SIM_MODE_CSN) {
1310 // Use the CSN from commandline
1311 memcpy(emulator, datain, 8);
1312 doIClassSimulation(ICLASS_SIM_MODE_CSN, NULL);
1313 } else if (simType == ICLASS_SIM_MODE_CSN_DEFAULT) {
1314 //Default CSN
1315 uint8_t csn_crc[] = { 0x03, 0x1f, 0xec, 0x8a, 0xf7, 0xff, 0x12, 0xe0, 0x00, 0x00 };
1316 // Use the CSN from commandline
1317 memcpy(emulator, csn_crc, 8);
1318 doIClassSimulation(ICLASS_SIM_MODE_CSN, NULL);
1319 } else if (simType == ICLASS_SIM_MODE_READER_ATTACK) {
1320 uint8_t mac_responses[USB_CMD_DATA_SIZE] = { 0 };
1321 Dbprintf("Going into attack mode, %d CSNS sent", numberOfCSNS);
1322 // In this mode, a number of csns are within datain. We'll simulate each one, one at a time
1323 // in order to collect MAC's from the reader. This can later be used in an offline-attack
1324 // in order to obtain the keys, as in the "dismantling iclass"-paper.
1325 int i;
1326 for (i = 0; i < numberOfCSNS && i*16+16 <= USB_CMD_DATA_SIZE; i++) {
1327 // The usb data is 512 bytes, fitting 32 responses (8 byte CC + 4 Byte NR + 4 Byte MAC = 16 Byte response).
1328 memcpy(emulator, datain+(i*8), 8);
1329 if (doIClassSimulation(ICLASS_SIM_MODE_EXIT_AFTER_MAC, mac_responses+i*16)) {
1330 // Button pressed
1331 break;
1332 }
1333 }
1334 cmd_send(CMD_ACK, CMD_SIMULATE_TAG_ICLASS, i, 0, mac_responses, i*16);
1335 } else if (simType == ICLASS_SIM_MODE_FULL) {
1336 //This is 'full sim' mode, where we use the emulator storage for data.
1337 doIClassSimulation(ICLASS_SIM_MODE_FULL, NULL);
1338 } else {
1339 // We may want a mode here where we hardcode the csns to use (from proxclone).
1340 // That will speed things up a little, but not required just yet.
1341 Dbprintf("The mode is not implemented, reserved for future use");
1342 }
1343 Dbprintf("Done...");
1344
1345 }
1346
1347
1348 /// THE READER CODE
1349
1350 //-----------------------------------------------------------------------------
1351 // Transmit the command (to the tag) that was placed in ToSend[].
1352 //-----------------------------------------------------------------------------
1353 static void TransmitIClassCommand(const uint8_t *cmd, int len, int *samples, int *wait) {
1354 int c;
1355 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_MOD);
1356 AT91C_BASE_SSC->SSC_THR = 0x00;
1357 FpgaSetupSsc(FPGA_MAJOR_MODE_HF_ISO14443A);
1358
1359 if (wait) {
1360 if (*wait < 10) *wait = 10;
1361
1362 for (c = 0; c < *wait;) {
1363 if (AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1364 AT91C_BASE_SSC->SSC_THR = 0x00; // For exact timing!
1365 c++;
1366 }
1367 if (AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
1368 volatile uint32_t r = AT91C_BASE_SSC->SSC_RHR;
1369 (void)r;
1370 }
1371 WDT_HIT();
1372 }
1373 }
1374
1375 uint8_t sendbyte;
1376 bool firstpart = true;
1377 c = 0;
1378 for (;;) {
1379 if (AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1380
1381 // DOUBLE THE SAMPLES!
1382 if (firstpart) {
1383 sendbyte = (cmd[c] & 0xf0) | (cmd[c] >> 4);
1384 } else {
1385 sendbyte = (cmd[c] & 0x0f) | (cmd[c] << 4);
1386 c++;
1387 }
1388 if (sendbyte == 0xff) {
1389 sendbyte = 0xfe;
1390 }
1391 AT91C_BASE_SSC->SSC_THR = sendbyte;
1392 firstpart = !firstpart;
1393
1394 if (c >= len) {
1395 break;
1396 }
1397 }
1398 if (AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
1399 volatile uint32_t r = AT91C_BASE_SSC->SSC_RHR;
1400 (void)r;
1401 }
1402 WDT_HIT();
1403 }
1404 if (samples && wait) *samples = (c + *wait) << 3;
1405 }
1406
1407
1408 //-----------------------------------------------------------------------------
1409 // Prepare iClass reader command to send to FPGA
1410 //-----------------------------------------------------------------------------
1411 void CodeIClassCommand(const uint8_t *cmd, int len) {
1412 int i, j, k;
1413
1414 ToSendReset();
1415
1416 // Start of Communication: 1 out of 4
1417 ToSend[++ToSendMax] = 0xf0;
1418 ToSend[++ToSendMax] = 0x00;
1419 ToSend[++ToSendMax] = 0x0f;
1420 ToSend[++ToSendMax] = 0x00;
1421
1422 // Modulate the bytes
1423 for (i = 0; i < len; i++) {
1424 uint8_t b = cmd[i];
1425 for (j = 0; j < 4; j++) {
1426 for (k = 0; k < 4; k++) {
1427 if (k == (b & 3)) {
1428 ToSend[++ToSendMax] = 0xf0;
1429 } else {
1430 ToSend[++ToSendMax] = 0x00;
1431 }
1432 }
1433 b >>= 2;
1434 }
1435 }
1436
1437 // End of Communication
1438 ToSend[++ToSendMax] = 0x00;
1439 ToSend[++ToSendMax] = 0x00;
1440 ToSend[++ToSendMax] = 0xf0;
1441 ToSend[++ToSendMax] = 0x00;
1442
1443 // Convert from last character reference to length
1444 ToSendMax++;
1445 }
1446
1447 static void ReaderTransmitIClass(uint8_t *frame, int len) {
1448 int wait = 0;
1449 int samples = 0;
1450
1451 // This is tied to other size changes
1452 CodeIClassCommand(frame, len);
1453
1454 // Select the card
1455 TransmitIClassCommand(ToSend, ToSendMax, &samples, &wait);
1456 if (trigger)
1457 LED_A_ON();
1458
1459 // Store reader command in buffer
1460 uint8_t par[MAX_PARITY_SIZE];
1461 GetParity(frame, len, par);
1462 LogTrace(frame, len, rsamples, rsamples, par, true);
1463 }
1464
1465 //-----------------------------------------------------------------------------
1466 // Wait a certain time for tag response
1467 // If a response is captured return true
1468 // If it takes too long return false
1469 //-----------------------------------------------------------------------------
1470 static int GetIClassAnswer(uint8_t *receivedResponse, int maxLen, int *samples, int *elapsed) {
1471 //uint8_t *buffer
1472 // buffer needs to be 512 bytes
1473 int c;
1474
1475 // Set FPGA mode to "reader listen mode", no modulation (listen
1476 // only, since we are receiving, not transmitting).
1477 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_LISTEN);
1478
1479 // Now get the answer from the card
1480 Demod.output = receivedResponse;
1481 Demod.len = 0;
1482 Demod.state = DEMOD_UNSYNCD;
1483
1484 uint8_t b;
1485 if (elapsed) *elapsed = 0;
1486
1487 bool skip = false;
1488
1489 c = 0;
1490 for (;;) {
1491 WDT_HIT();
1492
1493 if (BUTTON_PRESS()) return false;
1494
1495 if (AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1496 AT91C_BASE_SSC->SSC_THR = 0x00; // To make use of exact timing of next command from reader!!
1497 if (elapsed) (*elapsed)++;
1498 }
1499 if (AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
1500 if (c < timeout) {
1501 c++;
1502 } else {
1503 return false;
1504 }
1505 b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1506 skip = !skip;
1507 if (skip) continue;
1508
1509 if (ManchesterDecoding(b & 0x0f)) {
1510 *samples = c << 3;
1511 return true;
1512 }
1513 }
1514 }
1515 }
1516
1517 static int ReaderReceiveIClass(uint8_t *receivedAnswer) {
1518 int samples = 0;
1519 if (!GetIClassAnswer(receivedAnswer, 160, &samples, 0)) {
1520 return false;
1521 }
1522 rsamples += samples;
1523 uint8_t parity[MAX_PARITY_SIZE];
1524 GetParity(receivedAnswer, Demod.len, parity);
1525 LogTrace(receivedAnswer, Demod.len, rsamples, rsamples, parity, false);
1526 if (samples == 0) return false;
1527 return Demod.len;
1528 }
1529
1530 static void setupIclassReader() {
1531 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
1532 // Reset trace buffer
1533 set_tracing(true);
1534 clear_trace();
1535
1536 // Setup SSC
1537 FpgaSetupSsc(FPGA_MAJOR_MODE_HF_ISO14443A);
1538 // Start from off (no field generated)
1539 // Signal field is off with the appropriate LED
1540 LED_D_OFF();
1541 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1542 SpinDelay(200);
1543
1544 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
1545
1546 // Now give it time to spin up.
1547 // Signal field is on with the appropriate LED
1548 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_MOD);
1549 SpinDelay(200);
1550 LED_A_ON();
1551
1552 }
1553
1554 static bool sendCmdGetResponseWithRetries(uint8_t* command, size_t cmdsize, uint8_t* resp, uint8_t expected_size, uint8_t retries) {
1555 while (retries-- > 0) {
1556 ReaderTransmitIClass(command, cmdsize);
1557 if (expected_size == ReaderReceiveIClass(resp)) {
1558 return true;
1559 }
1560 }
1561 return false;//Error
1562 }
1563
1564 /**
1565 * @brief Talks to an iclass tag, sends the commands to get CSN and CC.
1566 * @param card_data where the CSN and CC are stored for return
1567 * @return 0 = fail
1568 * 1 = Got CSN
1569 * 2 = Got CSN and CC
1570 */
1571 static uint8_t handshakeIclassTag_ext(uint8_t *card_data, bool use_credit_key) {
1572 static uint8_t act_all[] = { 0x0a };
1573 //static uint8_t identify[] = { 0x0c };
1574 static uint8_t identify[] = { 0x0c, 0x00, 0x73, 0x33 };
1575 static uint8_t select[] = { 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
1576 static uint8_t readcheck_cc[]= { 0x88, 0x02 };
1577 if (use_credit_key)
1578 readcheck_cc[0] = 0x18;
1579 else
1580 readcheck_cc[0] = 0x88;
1581
1582 uint8_t resp[ICLASS_BUFFER_SIZE];
1583
1584 uint8_t read_status = 0;
1585
1586 // Send act_all
1587 ReaderTransmitIClass(act_all, 1);
1588 // Card present?
1589 if (!ReaderReceiveIClass(resp)) return read_status;//Fail
1590 //Send Identify
1591 ReaderTransmitIClass(identify, 1);
1592 //We expect a 10-byte response here, 8 byte anticollision-CSN and 2 byte CRC
1593 uint8_t len = ReaderReceiveIClass(resp);
1594 if (len != 10) return read_status;//Fail
1595
1596 //Copy the Anti-collision CSN to our select-packet
1597 memcpy(&select[1], resp, 8);
1598 //Select the card
1599 ReaderTransmitIClass(select, sizeof(select));
1600 //We expect a 10-byte response here, 8 byte CSN and 2 byte CRC
1601 len = ReaderReceiveIClass(resp);
1602 if (len != 10) return read_status;//Fail
1603
1604 //Success - level 1, we got CSN
1605 //Save CSN in response data
1606 memcpy(card_data, resp, 8);
1607
1608 //Flag that we got to at least stage 1, read CSN
1609 read_status = 1;
1610
1611 // Card selected, now read e-purse (cc) (only 8 bytes no CRC)
1612 ReaderTransmitIClass(readcheck_cc, sizeof(readcheck_cc));
1613 if (ReaderReceiveIClass(resp) == 8) {
1614 //Save CC (e-purse) in response data
1615 memcpy(card_data+8, resp, 8);
1616 read_status++;
1617 }
1618
1619 return read_status;
1620 }
1621
1622 static uint8_t handshakeIclassTag(uint8_t *card_data) {
1623 return handshakeIclassTag_ext(card_data, false);
1624 }
1625
1626
1627 // Reader iClass Anticollission
1628 void ReaderIClass(uint8_t arg0) {
1629
1630 uint8_t card_data[6 * 8] = {0};
1631 memset(card_data, 0xFF, sizeof(card_data));
1632 uint8_t last_csn[8] = {0,0,0,0,0,0,0,0};
1633 uint8_t resp[ICLASS_BUFFER_SIZE];
1634 memset(resp, 0xFF, sizeof(resp));
1635 //Read conf block CRC(0x01) => 0xfa 0x22
1636 uint8_t readConf[] = { ICLASS_CMD_READ_OR_IDENTIFY, 0x01, 0xfa, 0x22};
1637 //Read App Issuer Area block CRC(0x05) => 0xde 0x64
1638 uint8_t readAA[] = { ICLASS_CMD_READ_OR_IDENTIFY, 0x05, 0xde, 0x64};
1639
1640 int read_status= 0;
1641 uint8_t result_status = 0;
1642 // flag to read until one tag is found successfully
1643 bool abort_after_read = arg0 & FLAG_ICLASS_READER_ONLY_ONCE;
1644 // flag to only try 5 times to find one tag then return
1645 bool try_once = arg0 & FLAG_ICLASS_READER_ONE_TRY;
1646 // if neither abort_after_read nor try_once then continue reading until button pressed.
1647
1648 bool use_credit_key = arg0 & FLAG_ICLASS_READER_CEDITKEY;
1649 // test flags for what blocks to be sure to read
1650 uint8_t flagReadConfig = arg0 & FLAG_ICLASS_READER_CONF;
1651 uint8_t flagReadCC = arg0 & FLAG_ICLASS_READER_CC;
1652 uint8_t flagReadAA = arg0 & FLAG_ICLASS_READER_AA;
1653
1654 set_tracing(true);
1655 setupIclassReader();
1656
1657 uint16_t tryCnt = 0;
1658 bool userCancelled = BUTTON_PRESS() || usb_poll_validate_length();
1659 while (!userCancelled) {
1660 // if only looking for one card try 2 times if we missed it the first time
1661 if (try_once && tryCnt > 2) {
1662 break;
1663 }
1664 tryCnt++;
1665 if (!get_tracing()) {
1666 DbpString("Trace full");
1667 break;
1668 }
1669 WDT_HIT();
1670
1671 read_status = handshakeIclassTag_ext(card_data, use_credit_key);
1672
1673 if (read_status == 0) continue;
1674 if (read_status == 1) result_status = FLAG_ICLASS_READER_CSN;
1675 if (read_status == 2) result_status = FLAG_ICLASS_READER_CSN | FLAG_ICLASS_READER_CC;
1676
1677 // handshakeIclass returns CSN|CC, but the actual block
1678 // layout is CSN|CONFIG|CC, so here we reorder the data,
1679 // moving CC forward 8 bytes
1680 memcpy(card_data+16, card_data+8, 8);
1681 //Read block 1, config
1682 if (flagReadConfig) {
1683 if (sendCmdGetResponseWithRetries(readConf, sizeof(readConf), resp, 10, 10)) {
1684 result_status |= FLAG_ICLASS_READER_CONF;
1685 memcpy(card_data+8, resp, 8);
1686 } else {
1687 Dbprintf("Failed to dump config block");
1688 }
1689 }
1690
1691 //Read block 5, AA
1692 if (flagReadAA) {
1693 if (sendCmdGetResponseWithRetries(readAA, sizeof(readAA), resp, 10, 10)) {
1694 result_status |= FLAG_ICLASS_READER_AA;
1695 memcpy(card_data + (8*5), resp, 8);
1696 } else {
1697 //Dbprintf("Failed to dump AA block");
1698 }
1699 }
1700
1701 // 0 : CSN
1702 // 1 : Configuration
1703 // 2 : e-purse
1704 // 3 : kd / debit / aa2 (write-only)
1705 // 4 : kc / credit / aa1 (write-only)
1706 // 5 : AIA, Application issuer area
1707 //Then we can 'ship' back the 6 * 8 bytes of data,
1708 // with 0xFF:s in block 3 and 4.
1709
1710 LED_B_ON();
1711 //Send back to client, but don't bother if we already sent this -
1712 // only useful if looping in arm (not try_once && not abort_after_read)
1713 if (memcmp(last_csn, card_data, 8) != 0) {
1714 // If caller requires that we get Conf, CC, AA, continue until we got it
1715 if ( (result_status ^ FLAG_ICLASS_READER_CSN ^ flagReadConfig ^ flagReadCC ^ flagReadAA) == 0) {
1716 cmd_send(CMD_ACK, result_status, 0, 0, card_data, sizeof(card_data));
1717 if (abort_after_read) {
1718 LED_A_OFF();
1719 LED_B_OFF();
1720 return;
1721 }
1722 //Save that we already sent this....
1723 memcpy(last_csn, card_data, 8);
1724 }
1725
1726 }
1727 LED_B_OFF();
1728 userCancelled = BUTTON_PRESS() || usb_poll_validate_length();
1729 }
1730 if (userCancelled) {
1731 cmd_send(CMD_ACK, 0xFF, 0, 0, card_data, 0);
1732 } else {
1733 cmd_send(CMD_ACK, 0, 0, 0, card_data, 0);
1734 }
1735 LED_A_OFF();
1736 }
1737
1738 void ReaderIClass_Replay(uint8_t arg0, uint8_t *MAC) {
1739
1740 uint8_t card_data[USB_CMD_DATA_SIZE]={0};
1741 uint16_t block_crc_LUT[255] = {0};
1742
1743 //Generate a lookup table for block crc
1744 for (int block = 0; block < 255; block++){
1745 char bl = block;
1746 block_crc_LUT[block] = iclass_crc16(&bl ,1);
1747 }
1748 //Dbprintf("Lookup table: %02x %02x %02x" ,block_crc_LUT[0],block_crc_LUT[1],block_crc_LUT[2]);
1749
1750 uint8_t check[] = { 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
1751 uint8_t read[] = { 0x0c, 0x00, 0x00, 0x00 };
1752
1753 uint16_t crc = 0;
1754 uint8_t cardsize = 0;
1755 uint8_t mem = 0;
1756
1757 static struct memory_t {
1758 int k16;
1759 int book;
1760 int k2;
1761 int lockauth;
1762 int keyaccess;
1763 } memory;
1764
1765 uint8_t resp[ICLASS_BUFFER_SIZE];
1766
1767 setupIclassReader();
1768 set_tracing(true);
1769
1770 while (!BUTTON_PRESS()) {
1771
1772 WDT_HIT();
1773
1774 if (!get_tracing()) {
1775 DbpString("Trace full");
1776 break;
1777 }
1778
1779 uint8_t read_status = handshakeIclassTag(card_data);
1780 if (read_status < 2) continue;
1781
1782 //for now replay captured auth (as cc not updated)
1783 memcpy(check+5, MAC, 4);
1784
1785 if (!sendCmdGetResponseWithRetries(check, sizeof(check), resp, 4, 5)) {
1786 Dbprintf("Error: Authentication Fail!");
1787 continue;
1788 }
1789
1790 //first get configuration block (block 1)
1791 crc = block_crc_LUT[1];
1792 read[1] = 1;
1793 read[2] = crc >> 8;
1794 read[3] = crc & 0xff;
1795
1796 if (!sendCmdGetResponseWithRetries(read, sizeof(read),resp, 10, 10)) {
1797 Dbprintf("Dump config (block 1) failed");
1798 continue;
1799 }
1800
1801 mem = resp[5];
1802 memory.k16 = (mem & 0x80);
1803 memory.book = (mem & 0x20);
1804 memory.k2 = (mem & 0x8);
1805 memory.lockauth = (mem & 0x2);
1806 memory.keyaccess = (mem & 0x1);
1807
1808 cardsize = memory.k16 ? 255 : 32;
1809 WDT_HIT();
1810 //Set card_data to all zeroes, we'll fill it with data
1811 memset(card_data, 0x0, USB_CMD_DATA_SIZE);
1812 uint8_t failedRead = 0;
1813 uint32_t stored_data_length = 0;
1814 //then loop around remaining blocks
1815 for (int block = 0; block < cardsize; block++) {
1816 read[1] = block;
1817 crc = block_crc_LUT[block];
1818 read[2] = crc >> 8;
1819 read[3] = crc & 0xff;
1820
1821 if (sendCmdGetResponseWithRetries(read, sizeof(read), resp, 10, 10)) {
1822 Dbprintf(" %02x: %02x %02x %02x %02x %02x %02x %02x %02x",
1823 block, resp[0], resp[1], resp[2],
1824 resp[3], resp[4], resp[5],
1825 resp[6], resp[7]);
1826
1827 //Fill up the buffer
1828 memcpy(card_data+stored_data_length, resp, 8);
1829 stored_data_length += 8;
1830 if (stored_data_length +8 > USB_CMD_DATA_SIZE) {
1831 //Time to send this off and start afresh
1832 cmd_send(CMD_ACK,
1833 stored_data_length,//data length
1834 failedRead,//Failed blocks?
1835 0,//Not used ATM
1836 card_data, stored_data_length);
1837 //reset
1838 stored_data_length = 0;
1839 failedRead = 0;
1840 }
1841
1842 } else {
1843 failedRead = 1;
1844 stored_data_length += 8;//Otherwise, data becomes misaligned
1845 Dbprintf("Failed to dump block %d", block);
1846 }
1847 }
1848
1849 //Send off any remaining data
1850 if (stored_data_length > 0) {
1851 cmd_send(CMD_ACK,
1852 stored_data_length,//data length
1853 failedRead,//Failed blocks?
1854 0,//Not used ATM
1855 card_data,
1856 stored_data_length);
1857 }
1858 //If we got here, let's break
1859 break;
1860 }
1861 //Signal end of transmission
1862 cmd_send(CMD_ACK,
1863 0,//data length
1864 0,//Failed blocks?
1865 0,//Not used ATM
1866 card_data,
1867 0);
1868
1869 LED_A_OFF();
1870 }
1871
1872 void iClass_ReadCheck(uint8_t blockNo, uint8_t keyType) {
1873 uint8_t readcheck[] = { keyType, blockNo };
1874 uint8_t resp[] = {0,0,0,0,0,0,0,0};
1875 size_t isOK = 0;
1876 isOK = sendCmdGetResponseWithRetries(readcheck, sizeof(readcheck), resp, sizeof(resp), 6);
1877 cmd_send(CMD_ACK,isOK, 0, 0, 0, 0);
1878 }
1879
1880 void iClass_Authentication(uint8_t *MAC) {
1881 uint8_t check[] = { ICLASS_CMD_CHECK, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
1882 uint8_t resp[ICLASS_BUFFER_SIZE];
1883 memcpy(check+5, MAC, 4);
1884 bool isOK;
1885 isOK = sendCmdGetResponseWithRetries(check, sizeof(check), resp, 4, 6);
1886 cmd_send(CMD_ACK,isOK, 0, 0, 0, 0);
1887 }
1888
1889 bool iClass_ReadBlock(uint8_t blockNo, uint8_t *readdata) {
1890 uint8_t readcmd[] = {ICLASS_CMD_READ_OR_IDENTIFY, blockNo, 0x00, 0x00}; //0x88, 0x00 // can i use 0C?
1891 char bl = blockNo;
1892 uint16_t rdCrc = iclass_crc16(&bl, 1);
1893 readcmd[2] = rdCrc >> 8;
1894 readcmd[3] = rdCrc & 0xff;
1895 uint8_t resp[] = {0,0,0,0,0,0,0,0,0,0};
1896 bool isOK = false;
1897
1898 //readcmd[1] = blockNo;
1899 isOK = sendCmdGetResponseWithRetries(readcmd, sizeof(readcmd), resp, 10, 10);
1900 memcpy(readdata, resp, sizeof(resp));
1901
1902 return isOK;
1903 }
1904
1905 void iClass_ReadBlk(uint8_t blockno) {
1906 uint8_t readblockdata[] = {0,0,0,0,0,0,0,0,0,0};
1907 bool isOK = false;
1908 isOK = iClass_ReadBlock(blockno, readblockdata);
1909 cmd_send(CMD_ACK, isOK, 0, 0, readblockdata, 8);
1910 }
1911
1912 void iClass_Dump(uint8_t blockno, uint8_t numblks) {
1913 uint8_t readblockdata[] = {0,0,0,0,0,0,0,0,0,0};
1914 bool isOK = false;
1915 uint8_t blkCnt = 0;
1916
1917 BigBuf_free();
1918 uint8_t *dataout = BigBuf_malloc(255*8);
1919 if (dataout == NULL) {
1920 Dbprintf("out of memory");
1921 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1922 LED_D_OFF();
1923 cmd_send(CMD_ACK, 0, 1, 0, 0, 0);
1924 LED_A_OFF();
1925 return;
1926 }
1927 memset(dataout, 0xFF, 255*8);
1928
1929 for ( ; blkCnt < numblks; blkCnt++) {
1930 isOK = iClass_ReadBlock(blockno+blkCnt, readblockdata);
1931 if (!isOK || (readblockdata[0] == 0xBB || readblockdata[7] == 0xBB || readblockdata[2] == 0xBB)) { //try again
1932 isOK = iClass_ReadBlock(blockno+blkCnt, readblockdata);
1933 if (!isOK) {
1934 Dbprintf("Block %02X failed to read", blkCnt+blockno);
1935 break;
1936 }
1937 }
1938 memcpy(dataout + (blkCnt*8), readblockdata, 8);
1939 }
1940 //return pointer to dump memory in arg3
1941 cmd_send(CMD_ACK, isOK, blkCnt, BigBuf_max_traceLen(), 0, 0);
1942 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1943 LEDsoff();
1944 BigBuf_free();
1945 }
1946
1947 static bool iClass_WriteBlock_ext(uint8_t blockNo, uint8_t *data) {
1948 uint8_t write[] = { ICLASS_CMD_UPDATE, blockNo, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
1949 //uint8_t readblockdata[10];
1950 //write[1] = blockNo;
1951 memcpy(write+2, data, 12); // data + mac
1952 char *wrCmd = (char *)(write+1);
1953 uint16_t wrCrc = iclass_crc16(wrCmd, 13);
1954 write[14] = wrCrc >> 8;
1955 write[15] = wrCrc & 0xff;
1956 uint8_t resp[] = {0,0,0,0,0,0,0,0,0,0};
1957 bool isOK = false;
1958
1959 isOK = sendCmdGetResponseWithRetries(write, sizeof(write), resp, sizeof(resp), 10);
1960 if (isOK) { //if reader responded correctly
1961 //Dbprintf("WriteResp: %02X%02X%02X%02X%02X%02X%02X%02X%02X%02X",resp[0],resp[1],resp[2],resp[3],resp[4],resp[5],resp[6],resp[7],resp[8],resp[9]);
1962 if (memcmp(write+2, resp, 8)) { //if response is not equal to write values
1963 if (blockNo != 3 && blockNo != 4) { //if not programming key areas (note key blocks don't get programmed with actual key data it is xor data)
1964 //error try again
1965 isOK = sendCmdGetResponseWithRetries(write, sizeof(write), resp, sizeof(resp), 10);
1966 }
1967 }
1968 }
1969 return isOK;
1970 }
1971
1972 void iClass_WriteBlock(uint8_t blockNo, uint8_t *data) {
1973 bool isOK = iClass_WriteBlock_ext(blockNo, data);
1974 if (isOK){
1975 Dbprintf("Write block [%02x] successful", blockNo);
1976 } else {
1977 Dbprintf("Write block [%02x] failed", blockNo);
1978 }
1979 cmd_send(CMD_ACK, isOK, 0, 0, 0, 0);
1980 }
1981
1982 void iClass_Clone(uint8_t startblock, uint8_t endblock, uint8_t *data) {
1983 int i;
1984 int written = 0;
1985 int total_block = (endblock - startblock) + 1;
1986 for (i = 0; i < total_block; i++) {
1987 // block number
1988 if (iClass_WriteBlock_ext(i+startblock, data + (i*12))){
1989 Dbprintf("Write block [%02x] successful", i + startblock);
1990 written++;
1991 } else {
1992 if (iClass_WriteBlock_ext(i+startblock, data + (i*12))){
1993 Dbprintf("Write block [%02x] successful", i + startblock);
1994 written++;
1995 } else {
1996 Dbprintf("Write block [%02x] failed", i + startblock);
1997 }
1998 }
1999 }
2000 if (written == total_block)
2001 Dbprintf("Clone complete");
2002 else
2003 Dbprintf("Clone incomplete");
2004
2005 cmd_send(CMD_ACK, 1, 0, 0, 0, 0);
2006 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
2007 LEDsoff();
2008 }
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