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1 //-----------------------------------------------------------------------------
2 // Merlok - June 2011, 2012
3 // Gerhard de Koning Gans - May 2008
4 // Hagen Fritsch - June 2010
5 //
6 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
7 // at your option, any later version. See the LICENSE.txt file for the text of
8 // the license.
9 //-----------------------------------------------------------------------------
10 // Routines to support ISO 14443 type A.
11 //-----------------------------------------------------------------------------
12
13 #include "iso14443a.h"
14
15 #include <stdio.h>
16 #include <string.h>
17 #include "proxmark3.h"
18 #include "apps.h"
19 #include "util.h"
20 #include "cmd.h"
21 #include "iso14443crc.h"
22 #include "crapto1/crapto1.h"
23 #include "mifareutil.h"
24 #include "mifaresniff.h"
25 #include "BigBuf.h"
26 #include "protocols.h"
27 #include "parity.h"
28 #include "fpgaloader.h"
29
30 typedef struct {
31 enum {
32 DEMOD_UNSYNCD,
33 // DEMOD_HALF_SYNCD,
34 // DEMOD_MOD_FIRST_HALF,
35 // DEMOD_NOMOD_FIRST_HALF,
36 DEMOD_MANCHESTER_DATA
37 } state;
38 uint16_t twoBits;
39 uint16_t highCnt;
40 uint16_t bitCount;
41 uint16_t collisionPos;
42 uint16_t syncBit;
43 uint8_t parityBits;
44 uint8_t parityLen;
45 uint16_t shiftReg;
46 uint16_t samples;
47 uint16_t len;
48 uint32_t startTime, endTime;
49 uint8_t *output;
50 uint8_t *parity;
51 } tDemod;
52
53 typedef enum {
54 MOD_NOMOD = 0,
55 MOD_SECOND_HALF,
56 MOD_FIRST_HALF,
57 MOD_BOTH_HALVES
58 } Modulation_t;
59
60 typedef struct {
61 enum {
62 STATE_UNSYNCD,
63 STATE_START_OF_COMMUNICATION,
64 STATE_MILLER_X,
65 STATE_MILLER_Y,
66 STATE_MILLER_Z,
67 // DROP_NONE,
68 // DROP_FIRST_HALF,
69 } state;
70 uint16_t shiftReg;
71 int16_t bitCount;
72 uint16_t len;
73 uint16_t byteCntMax;
74 uint16_t posCnt;
75 uint16_t syncBit;
76 uint8_t parityBits;
77 uint8_t parityLen;
78 uint32_t fourBits;
79 uint32_t startTime, endTime;
80 uint8_t *output;
81 uint8_t *parity;
82 } tUart;
83
84 static uint32_t iso14a_timeout;
85 #define MAX_ISO14A_TIMEOUT 524288
86
87 int rsamples = 0;
88 uint8_t trigger = 0;
89 // the block number for the ISO14443-4 PCB
90 static uint8_t iso14_pcb_blocknum = 0;
91
92 //
93 // ISO14443 timing:
94 //
95 // minimum time between the start bits of consecutive transfers from reader to tag: 7000 carrier (13.56Mhz) cycles
96 #define REQUEST_GUARD_TIME (7000/16 + 1)
97 // minimum time between last modulation of tag and next start bit from reader to tag: 1172 carrier cycles
98 #define FRAME_DELAY_TIME_PICC_TO_PCD (1172/16 + 1)
99 // bool LastCommandWasRequest = false;
100
101 //
102 // Total delays including SSC-Transfers between ARM and FPGA. These are in carrier clock cycles (1/13,56MHz)
103 //
104 // When the PM acts as reader and is receiving tag data, it takes
105 // 3 ticks delay in the AD converter
106 // 16 ticks until the modulation detector completes and sets curbit
107 // 8 ticks until bit_to_arm is assigned from curbit
108 // 8*16 ticks for the transfer from FPGA to ARM
109 // 4*16 ticks until we measure the time
110 // - 8*16 ticks because we measure the time of the previous transfer
111 #define DELAY_AIR2ARM_AS_READER (3 + 16 + 8 + 8*16 + 4*16 - 8*16)
112
113 // When the PM acts as a reader and is sending, it takes
114 // 4*16 ticks until we can write data to the sending hold register
115 // 8*16 ticks until the SHR is transferred to the Sending Shift Register
116 // 8 ticks until the first transfer starts
117 // 8 ticks later the FPGA samples the data
118 // 1 tick to assign mod_sig_coil
119 #define DELAY_ARM2AIR_AS_READER (4*16 + 8*16 + 8 + 8 + 1)
120
121 // When the PM acts as tag and is receiving it takes
122 // 2 ticks delay in the RF part (for the first falling edge),
123 // 3 ticks for the A/D conversion,
124 // 8 ticks on average until the start of the SSC transfer,
125 // 8 ticks until the SSC samples the first data
126 // 7*16 ticks to complete the transfer from FPGA to ARM
127 // 8 ticks until the next ssp_clk rising edge
128 // 4*16 ticks until we measure the time
129 // - 8*16 ticks because we measure the time of the previous transfer
130 #define DELAY_AIR2ARM_AS_TAG (2 + 3 + 8 + 8 + 7*16 + 8 + 4*16 - 8*16)
131
132 // The FPGA will report its internal sending delay in
133 uint16_t FpgaSendQueueDelay;
134 // the 5 first bits are the number of bits buffered in mod_sig_buf
135 // the last three bits are the remaining ticks/2 after the mod_sig_buf shift
136 #define DELAY_FPGA_QUEUE (FpgaSendQueueDelay<<1)
137
138 // When the PM acts as tag and is sending, it takes
139 // 4*16 + 8 ticks until we can write data to the sending hold register
140 // 8*16 ticks until the SHR is transferred to the Sending Shift Register
141 // 8 ticks later the FPGA samples the first data
142 // + 16 ticks until assigned to mod_sig
143 // + 1 tick to assign mod_sig_coil
144 // + a varying number of ticks in the FPGA Delay Queue (mod_sig_buf)
145 #define DELAY_ARM2AIR_AS_TAG (4*16 + 8 + 8*16 + 8 + 16 + 1 + DELAY_FPGA_QUEUE)
146
147 // When the PM acts as sniffer and is receiving tag data, it takes
148 // 3 ticks A/D conversion
149 // 14 ticks to complete the modulation detection
150 // 8 ticks (on average) until the result is stored in to_arm
151 // + the delays in transferring data - which is the same for
152 // sniffing reader and tag data and therefore not relevant
153 #define DELAY_TAG_AIR2ARM_AS_SNIFFER (3 + 14 + 8)
154
155 // When the PM acts as sniffer and is receiving reader data, it takes
156 // 2 ticks delay in analogue RF receiver (for the falling edge of the
157 // start bit, which marks the start of the communication)
158 // 3 ticks A/D conversion
159 // 8 ticks on average until the data is stored in to_arm.
160 // + the delays in transferring data - which is the same for
161 // sniffing reader and tag data and therefore not relevant
162 #define DELAY_READER_AIR2ARM_AS_SNIFFER (2 + 3 + 8)
163
164 //variables used for timing purposes:
165 //these are in ssp_clk cycles:
166 static uint32_t NextTransferTime;
167 static uint32_t LastTimeProxToAirStart;
168 static uint32_t LastProxToAirDuration;
169
170
171
172 // CARD TO READER - manchester
173 // Sequence D: 11110000 modulation with subcarrier during first half
174 // Sequence E: 00001111 modulation with subcarrier during second half
175 // Sequence F: 00000000 no modulation with subcarrier
176 // READER TO CARD - miller
177 // Sequence X: 00001100 drop after half a period
178 // Sequence Y: 00000000 no drop
179 // Sequence Z: 11000000 drop at start
180 #define SEC_D 0xf0
181 #define SEC_E 0x0f
182 #define SEC_F 0x00
183 #define SEC_X 0x0c
184 #define SEC_Y 0x00
185 #define SEC_Z 0xc0
186
187 void iso14a_set_trigger(bool enable) {
188 trigger = enable;
189 }
190
191
192 void iso14a_set_timeout(uint32_t timeout) {
193 // adjust timeout by FPGA delays and 2 additional ssp_frames to detect SOF
194 iso14a_timeout = timeout + (DELAY_AIR2ARM_AS_READER + DELAY_ARM2AIR_AS_READER)/(16*8) + 2;
195 if(MF_DBGLEVEL >= 3) Dbprintf("ISO14443A Timeout set to %ld (%dms)", timeout, timeout / 106);
196 }
197
198
199 uint32_t iso14a_get_timeout(void) {
200 return iso14a_timeout - (DELAY_AIR2ARM_AS_READER + DELAY_ARM2AIR_AS_READER)/(16*8) - 2;
201 }
202
203 //-----------------------------------------------------------------------------
204 // Generate the parity value for a byte sequence
205 //
206 //-----------------------------------------------------------------------------
207 void GetParity(const uint8_t *pbtCmd, uint16_t iLen, uint8_t *par)
208 {
209 uint16_t paritybit_cnt = 0;
210 uint16_t paritybyte_cnt = 0;
211 uint8_t parityBits = 0;
212
213 for (uint16_t i = 0; i < iLen; i++) {
214 // Generate the parity bits
215 parityBits |= ((oddparity8(pbtCmd[i])) << (7-paritybit_cnt));
216 if (paritybit_cnt == 7) {
217 par[paritybyte_cnt] = parityBits; // save 8 Bits parity
218 parityBits = 0; // and advance to next Parity Byte
219 paritybyte_cnt++;
220 paritybit_cnt = 0;
221 } else {
222 paritybit_cnt++;
223 }
224 }
225
226 // save remaining parity bits
227 par[paritybyte_cnt] = parityBits;
228
229 }
230
231 void AppendCrc14443a(uint8_t* data, int len)
232 {
233 ComputeCrc14443(CRC_14443_A,data,len,data+len,data+len+1);
234 }
235
236 static void AppendCrc14443b(uint8_t* data, int len)
237 {
238 ComputeCrc14443(CRC_14443_B,data,len,data+len,data+len+1);
239 }
240
241
242 //=============================================================================
243 // ISO 14443 Type A - Miller decoder
244 //=============================================================================
245 // Basics:
246 // This decoder is used when the PM3 acts as a tag.
247 // The reader will generate "pauses" by temporarily switching of the field.
248 // At the PM3 antenna we will therefore measure a modulated antenna voltage.
249 // The FPGA does a comparison with a threshold and would deliver e.g.:
250 // ........ 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 .......
251 // The Miller decoder needs to identify the following sequences:
252 // 2 (or 3) ticks pause followed by 6 (or 5) ticks unmodulated: pause at beginning - Sequence Z ("start of communication" or a "0")
253 // 8 ticks without a modulation: no pause - Sequence Y (a "0" or "end of communication" or "no information")
254 // 4 ticks unmodulated followed by 2 (or 3) ticks pause: pause in second half - Sequence X (a "1")
255 // Note 1: the bitstream may start at any time. We therefore need to sync.
256 // Note 2: the interpretation of Sequence Y and Z depends on the preceding sequence.
257 //-----------------------------------------------------------------------------
258 static tUart Uart;
259
260 // Lookup-Table to decide if 4 raw bits are a modulation.
261 // We accept the following:
262 // 0001 - a 3 tick wide pause
263 // 0011 - a 2 tick wide pause, or a three tick wide pause shifted left
264 // 0111 - a 2 tick wide pause shifted left
265 // 1001 - a 2 tick wide pause shifted right
266 const bool Mod_Miller_LUT[] = {
267 false, true, false, true, false, false, false, true,
268 false, true, false, false, false, false, false, false
269 };
270 #define IsMillerModulationNibble1(b) (Mod_Miller_LUT[(b & 0x000000F0) >> 4])
271 #define IsMillerModulationNibble2(b) (Mod_Miller_LUT[(b & 0x0000000F)])
272
273 static void UartReset()
274 {
275 Uart.state = STATE_UNSYNCD;
276 Uart.bitCount = 0;
277 Uart.len = 0; // number of decoded data bytes
278 Uart.parityLen = 0; // number of decoded parity bytes
279 Uart.shiftReg = 0; // shiftreg to hold decoded data bits
280 Uart.parityBits = 0; // holds 8 parity bits
281 Uart.startTime = 0;
282 Uart.endTime = 0;
283 }
284
285 static void UartInit(uint8_t *data, uint8_t *parity)
286 {
287 Uart.output = data;
288 Uart.parity = parity;
289 Uart.fourBits = 0x00000000; // clear the buffer for 4 Bits
290 UartReset();
291 }
292
293 // use parameter non_real_time to provide a timestamp. Set to 0 if the decoder should measure real time
294 static RAMFUNC bool MillerDecoding(uint8_t bit, uint32_t non_real_time)
295 {
296
297 Uart.fourBits = (Uart.fourBits << 8) | bit;
298
299 if (Uart.state == STATE_UNSYNCD) { // not yet synced
300
301 Uart.syncBit = 9999; // not set
302 // The start bit is one ore more Sequence Y followed by a Sequence Z (... 11111111 00x11111). We need to distinguish from
303 // Sequence X followed by Sequence Y followed by Sequence Z (111100x1 11111111 00x11111)
304 // we therefore look for a ...xx11111111111100x11111xxxxxx... pattern
305 // (12 '1's followed by 2 '0's, eventually followed by another '0', followed by 5 '1's)
306 #define ISO14443A_STARTBIT_MASK 0x07FFEF80 // mask is 00000111 11111111 11101111 10000000
307 #define ISO14443A_STARTBIT_PATTERN 0x07FF8F80 // pattern is 00000111 11111111 10001111 10000000
308 if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 0)) == ISO14443A_STARTBIT_PATTERN >> 0) Uart.syncBit = 7;
309 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 1)) == ISO14443A_STARTBIT_PATTERN >> 1) Uart.syncBit = 6;
310 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 2)) == ISO14443A_STARTBIT_PATTERN >> 2) Uart.syncBit = 5;
311 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 3)) == ISO14443A_STARTBIT_PATTERN >> 3) Uart.syncBit = 4;
312 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 4)) == ISO14443A_STARTBIT_PATTERN >> 4) Uart.syncBit = 3;
313 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 5)) == ISO14443A_STARTBIT_PATTERN >> 5) Uart.syncBit = 2;
314 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 6)) == ISO14443A_STARTBIT_PATTERN >> 6) Uart.syncBit = 1;
315 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 7)) == ISO14443A_STARTBIT_PATTERN >> 7) Uart.syncBit = 0;
316
317 if (Uart.syncBit != 9999) { // found a sync bit
318 Uart.startTime = non_real_time?non_real_time:(GetCountSspClk() & 0xfffffff8);
319 Uart.startTime -= Uart.syncBit;
320 Uart.endTime = Uart.startTime;
321 Uart.state = STATE_START_OF_COMMUNICATION;
322 }
323
324 } else {
325
326 if (IsMillerModulationNibble1(Uart.fourBits >> Uart.syncBit)) {
327 if (IsMillerModulationNibble2(Uart.fourBits >> Uart.syncBit)) { // Modulation in both halves - error
328 UartReset();
329 } else { // Modulation in first half = Sequence Z = logic "0"
330 if (Uart.state == STATE_MILLER_X) { // error - must not follow after X
331 UartReset();
332 } else {
333 Uart.bitCount++;
334 Uart.shiftReg = (Uart.shiftReg >> 1); // add a 0 to the shiftreg
335 Uart.state = STATE_MILLER_Z;
336 Uart.endTime = Uart.startTime + 8*(9*Uart.len + Uart.bitCount + 1) - 6;
337 if(Uart.bitCount >= 9) { // if we decoded a full byte (including parity)
338 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff);
339 Uart.parityBits <<= 1; // make room for the parity bit
340 Uart.parityBits |= ((Uart.shiftReg >> 8) & 0x01); // store parity bit
341 Uart.bitCount = 0;
342 Uart.shiftReg = 0;
343 if((Uart.len&0x0007) == 0) { // every 8 data bytes
344 Uart.parity[Uart.parityLen++] = Uart.parityBits; // store 8 parity bits
345 Uart.parityBits = 0;
346 }
347 }
348 }
349 }
350 } else {
351 if (IsMillerModulationNibble2(Uart.fourBits >> Uart.syncBit)) { // Modulation second half = Sequence X = logic "1"
352 Uart.bitCount++;
353 Uart.shiftReg = (Uart.shiftReg >> 1) | 0x100; // add a 1 to the shiftreg
354 Uart.state = STATE_MILLER_X;
355 Uart.endTime = Uart.startTime + 8*(9*Uart.len + Uart.bitCount + 1) - 2;
356 if(Uart.bitCount >= 9) { // if we decoded a full byte (including parity)
357 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff);
358 Uart.parityBits <<= 1; // make room for the new parity bit
359 Uart.parityBits |= ((Uart.shiftReg >> 8) & 0x01); // store parity bit
360 Uart.bitCount = 0;
361 Uart.shiftReg = 0;
362 if ((Uart.len&0x0007) == 0) { // every 8 data bytes
363 Uart.parity[Uart.parityLen++] = Uart.parityBits; // store 8 parity bits
364 Uart.parityBits = 0;
365 }
366 }
367 } else { // no modulation in both halves - Sequence Y
368 if (Uart.state == STATE_MILLER_Z || Uart.state == STATE_MILLER_Y) { // Y after logic "0" - End of Communication
369 Uart.state = STATE_UNSYNCD;
370 Uart.bitCount--; // last "0" was part of EOC sequence
371 Uart.shiftReg <<= 1; // drop it
372 if(Uart.bitCount > 0) { // if we decoded some bits
373 Uart.shiftReg >>= (9 - Uart.bitCount); // right align them
374 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff); // add last byte to the output
375 Uart.parityBits <<= 1; // add a (void) parity bit
376 Uart.parityBits <<= (8 - (Uart.len&0x0007)); // left align parity bits
377 Uart.parity[Uart.parityLen++] = Uart.parityBits; // and store it
378 return true;
379 } else if (Uart.len & 0x0007) { // there are some parity bits to store
380 Uart.parityBits <<= (8 - (Uart.len&0x0007)); // left align remaining parity bits
381 Uart.parity[Uart.parityLen++] = Uart.parityBits; // and store them
382 }
383 if (Uart.len) {
384 return true; // we are finished with decoding the raw data sequence
385 } else {
386 UartReset(); // Nothing received - start over
387 }
388 }
389 if (Uart.state == STATE_START_OF_COMMUNICATION) { // error - must not follow directly after SOC
390 UartReset();
391 } else { // a logic "0"
392 Uart.bitCount++;
393 Uart.shiftReg = (Uart.shiftReg >> 1); // add a 0 to the shiftreg
394 Uart.state = STATE_MILLER_Y;
395 if(Uart.bitCount >= 9) { // if we decoded a full byte (including parity)
396 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff);
397 Uart.parityBits <<= 1; // make room for the parity bit
398 Uart.parityBits |= ((Uart.shiftReg >> 8) & 0x01); // store parity bit
399 Uart.bitCount = 0;
400 Uart.shiftReg = 0;
401 if ((Uart.len&0x0007) == 0) { // every 8 data bytes
402 Uart.parity[Uart.parityLen++] = Uart.parityBits; // store 8 parity bits
403 Uart.parityBits = 0;
404 }
405 }
406 }
407 }
408 }
409
410 }
411
412 return false; // not finished yet, need more data
413 }
414
415
416
417 //=============================================================================
418 // ISO 14443 Type A - Manchester decoder
419 //=============================================================================
420 // Basics:
421 // This decoder is used when the PM3 acts as a reader.
422 // The tag will modulate the reader field by asserting different loads to it. As a consequence, the voltage
423 // at the reader antenna will be modulated as well. The FPGA detects the modulation for us and would deliver e.g. the following:
424 // ........ 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 .......
425 // The Manchester decoder needs to identify the following sequences:
426 // 4 ticks modulated followed by 4 ticks unmodulated: Sequence D = 1 (also used as "start of communication")
427 // 4 ticks unmodulated followed by 4 ticks modulated: Sequence E = 0
428 // 8 ticks unmodulated: Sequence F = end of communication
429 // 8 ticks modulated: A collision. Save the collision position and treat as Sequence D
430 // Note 1: the bitstream may start at any time. We therefore need to sync.
431 // Note 2: parameter offset is used to determine the position of the parity bits (required for the anticollision command only)
432 static tDemod Demod;
433
434 // Lookup-Table to decide if 4 raw bits are a modulation.
435 // We accept three or four "1" in any position
436 const bool Mod_Manchester_LUT[] = {
437 false, false, false, false, false, false, false, true,
438 false, false, false, true, false, true, true, true
439 };
440
441 #define IsManchesterModulationNibble1(b) (Mod_Manchester_LUT[(b & 0x00F0) >> 4])
442 #define IsManchesterModulationNibble2(b) (Mod_Manchester_LUT[(b & 0x000F)])
443
444
445 static void DemodReset()
446 {
447 Demod.state = DEMOD_UNSYNCD;
448 Demod.len = 0; // number of decoded data bytes
449 Demod.parityLen = 0;
450 Demod.shiftReg = 0; // shiftreg to hold decoded data bits
451 Demod.parityBits = 0; //
452 Demod.collisionPos = 0; // Position of collision bit
453 Demod.twoBits = 0xffff; // buffer for 2 Bits
454 Demod.highCnt = 0;
455 Demod.startTime = 0;
456 Demod.endTime = 0;
457 }
458
459 static void DemodInit(uint8_t *data, uint8_t *parity)
460 {
461 Demod.output = data;
462 Demod.parity = parity;
463 DemodReset();
464 }
465
466 // use parameter non_real_time to provide a timestamp. Set to 0 if the decoder should measure real time
467 static RAMFUNC int ManchesterDecoding(uint8_t bit, uint16_t offset, uint32_t non_real_time)
468 {
469
470 Demod.twoBits = (Demod.twoBits << 8) | bit;
471
472 if (Demod.state == DEMOD_UNSYNCD) {
473
474 if (Demod.highCnt < 2) { // wait for a stable unmodulated signal
475 if (Demod.twoBits == 0x0000) {
476 Demod.highCnt++;
477 } else {
478 Demod.highCnt = 0;
479 }
480 } else {
481 Demod.syncBit = 0xFFFF; // not set
482 if ((Demod.twoBits & 0x7700) == 0x7000) Demod.syncBit = 7;
483 else if ((Demod.twoBits & 0x3B80) == 0x3800) Demod.syncBit = 6;
484 else if ((Demod.twoBits & 0x1DC0) == 0x1C00) Demod.syncBit = 5;
485 else if ((Demod.twoBits & 0x0EE0) == 0x0E00) Demod.syncBit = 4;
486 else if ((Demod.twoBits & 0x0770) == 0x0700) Demod.syncBit = 3;
487 else if ((Demod.twoBits & 0x03B8) == 0x0380) Demod.syncBit = 2;
488 else if ((Demod.twoBits & 0x01DC) == 0x01C0) Demod.syncBit = 1;
489 else if ((Demod.twoBits & 0x00EE) == 0x00E0) Demod.syncBit = 0;
490 if (Demod.syncBit != 0xFFFF) {
491 Demod.startTime = non_real_time?non_real_time:(GetCountSspClk() & 0xfffffff8);
492 Demod.startTime -= Demod.syncBit;
493 Demod.bitCount = offset; // number of decoded data bits
494 Demod.state = DEMOD_MANCHESTER_DATA;
495 }
496 }
497
498 } else {
499
500 if (IsManchesterModulationNibble1(Demod.twoBits >> Demod.syncBit)) { // modulation in first half
501 if (IsManchesterModulationNibble2(Demod.twoBits >> Demod.syncBit)) { // ... and in second half = collision
502 if (!Demod.collisionPos) {
503 Demod.collisionPos = (Demod.len << 3) + Demod.bitCount;
504 }
505 } // modulation in first half only - Sequence D = 1
506 Demod.bitCount++;
507 Demod.shiftReg = (Demod.shiftReg >> 1) | 0x100; // in both cases, add a 1 to the shiftreg
508 if(Demod.bitCount == 9) { // if we decoded a full byte (including parity)
509 Demod.output[Demod.len++] = (Demod.shiftReg & 0xff);
510 Demod.parityBits <<= 1; // make room for the parity bit
511 Demod.parityBits |= ((Demod.shiftReg >> 8) & 0x01); // store parity bit
512 Demod.bitCount = 0;
513 Demod.shiftReg = 0;
514 if((Demod.len&0x0007) == 0) { // every 8 data bytes
515 Demod.parity[Demod.parityLen++] = Demod.parityBits; // store 8 parity bits
516 Demod.parityBits = 0;
517 }
518 }
519 Demod.endTime = Demod.startTime + 8*(9*Demod.len + Demod.bitCount + 1) - 4;
520 } else { // no modulation in first half
521 if (IsManchesterModulationNibble2(Demod.twoBits >> Demod.syncBit)) { // and modulation in second half = Sequence E = 0
522 Demod.bitCount++;
523 Demod.shiftReg = (Demod.shiftReg >> 1); // add a 0 to the shiftreg
524 if(Demod.bitCount >= 9) { // if we decoded a full byte (including parity)
525 Demod.output[Demod.len++] = (Demod.shiftReg & 0xff);
526 Demod.parityBits <<= 1; // make room for the new parity bit
527 Demod.parityBits |= ((Demod.shiftReg >> 8) & 0x01); // store parity bit
528 Demod.bitCount = 0;
529 Demod.shiftReg = 0;
530 if ((Demod.len&0x0007) == 0) { // every 8 data bytes
531 Demod.parity[Demod.parityLen++] = Demod.parityBits; // store 8 parity bits1
532 Demod.parityBits = 0;
533 }
534 }
535 Demod.endTime = Demod.startTime + 8*(9*Demod.len + Demod.bitCount + 1);
536 } else { // no modulation in both halves - End of communication
537 if(Demod.bitCount > 0) { // there are some remaining data bits
538 Demod.shiftReg >>= (9 - Demod.bitCount); // right align the decoded bits
539 Demod.output[Demod.len++] = Demod.shiftReg & 0xff; // and add them to the output
540 Demod.parityBits <<= 1; // add a (void) parity bit
541 Demod.parityBits <<= (8 - (Demod.len&0x0007)); // left align remaining parity bits
542 Demod.parity[Demod.parityLen++] = Demod.parityBits; // and store them
543 return true;
544 } else if (Demod.len & 0x0007) { // there are some parity bits to store
545 Demod.parityBits <<= (8 - (Demod.len&0x0007)); // left align remaining parity bits
546 Demod.parity[Demod.parityLen++] = Demod.parityBits; // and store them
547 }
548 if (Demod.len) {
549 return true; // we are finished with decoding the raw data sequence
550 } else { // nothing received. Start over
551 DemodReset();
552 }
553 }
554 }
555
556 }
557
558 return false; // not finished yet, need more data
559 }
560
561 //=============================================================================
562 // Finally, a `sniffer' for ISO 14443 Type A
563 // Both sides of communication!
564 //=============================================================================
565
566 //-----------------------------------------------------------------------------
567 // Record the sequence of commands sent by the reader to the tag, with
568 // triggering so that we start recording at the point that the tag is moved
569 // near the reader.
570 //-----------------------------------------------------------------------------
571 void RAMFUNC SnoopIso14443a(uint8_t param) {
572 // param:
573 // bit 0 - trigger from first card answer
574 // bit 1 - trigger from first reader 7-bit request
575
576 LEDsoff();
577
578 iso14443a_setup(FPGA_HF_ISO14443A_SNIFFER);
579
580 // Allocate memory from BigBuf for some buffers
581 // free all previous allocations first
582 BigBuf_free();
583
584 // The command (reader -> tag) that we're receiving.
585 uint8_t *receivedCmd = BigBuf_malloc(MAX_FRAME_SIZE);
586 uint8_t *receivedCmdPar = BigBuf_malloc(MAX_PARITY_SIZE);
587
588 // The response (tag -> reader) that we're receiving.
589 uint8_t *receivedResponse = BigBuf_malloc(MAX_FRAME_SIZE);
590 uint8_t *receivedResponsePar = BigBuf_malloc(MAX_PARITY_SIZE);
591
592 // The DMA buffer, used to stream samples from the FPGA
593 uint8_t *dmaBuf = BigBuf_malloc(DMA_BUFFER_SIZE);
594
595 // init trace buffer
596 clear_trace();
597 set_tracing(true);
598
599 uint8_t *data = dmaBuf;
600 uint8_t previous_data = 0;
601 int maxDataLen = 0;
602 int dataLen = 0;
603 bool TagIsActive = false;
604 bool ReaderIsActive = false;
605
606 // Set up the demodulator for tag -> reader responses.
607 DemodInit(receivedResponse, receivedResponsePar);
608
609 // Set up the demodulator for the reader -> tag commands
610 UartInit(receivedCmd, receivedCmdPar);
611
612 // Setup and start DMA.
613 FpgaSetupSscDma((uint8_t *)dmaBuf, DMA_BUFFER_SIZE);
614
615 // We won't start recording the frames that we acquire until we trigger;
616 // a good trigger condition to get started is probably when we see a
617 // response from the tag.
618 // triggered == false -- to wait first for card
619 bool triggered = !(param & 0x03);
620
621 // And now we loop, receiving samples.
622 for(uint32_t rsamples = 0; true; ) {
623
624 if(BUTTON_PRESS()) {
625 DbpString("cancelled by button");
626 break;
627 }
628
629 LED_A_ON();
630 WDT_HIT();
631
632 int register readBufDataP = data - dmaBuf;
633 int register dmaBufDataP = DMA_BUFFER_SIZE - AT91C_BASE_PDC_SSC->PDC_RCR;
634 if (readBufDataP <= dmaBufDataP){
635 dataLen = dmaBufDataP - readBufDataP;
636 } else {
637 dataLen = DMA_BUFFER_SIZE - readBufDataP + dmaBufDataP;
638 }
639 // test for length of buffer
640 if(dataLen > maxDataLen) {
641 maxDataLen = dataLen;
642 if(dataLen > (9 * DMA_BUFFER_SIZE / 10)) {
643 Dbprintf("blew circular buffer! dataLen=%d", dataLen);
644 break;
645 }
646 }
647 if(dataLen < 1) continue;
648
649 // primary buffer was stopped( <-- we lost data!
650 if (!AT91C_BASE_PDC_SSC->PDC_RCR) {
651 AT91C_BASE_PDC_SSC->PDC_RPR = (uint32_t) dmaBuf;
652 AT91C_BASE_PDC_SSC->PDC_RCR = DMA_BUFFER_SIZE;
653 Dbprintf("RxEmpty ERROR!!! data length:%d", dataLen); // temporary
654 }
655 // secondary buffer sets as primary, secondary buffer was stopped
656 if (!AT91C_BASE_PDC_SSC->PDC_RNCR) {
657 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) dmaBuf;
658 AT91C_BASE_PDC_SSC->PDC_RNCR = DMA_BUFFER_SIZE;
659 }
660
661 LED_A_OFF();
662
663 if (rsamples & 0x01) { // Need two samples to feed Miller and Manchester-Decoder
664
665 if(!TagIsActive) { // no need to try decoding reader data if the tag is sending
666 uint8_t readerdata = (previous_data & 0xF0) | (*data >> 4);
667 if (MillerDecoding(readerdata, (rsamples-1)*4)) {
668 LED_C_ON();
669
670 // check - if there is a short 7bit request from reader
671 if ((!triggered) && (param & 0x02) && (Uart.len == 1) && (Uart.bitCount == 7)) triggered = true;
672
673 if(triggered) {
674 if (!LogTrace(receivedCmd,
675 Uart.len,
676 Uart.startTime*16 - DELAY_READER_AIR2ARM_AS_SNIFFER,
677 Uart.endTime*16 - DELAY_READER_AIR2ARM_AS_SNIFFER,
678 Uart.parity,
679 true)) break;
680 }
681 /* And ready to receive another command. */
682 UartReset();
683 /* And also reset the demod code, which might have been */
684 /* false-triggered by the commands from the reader. */
685 DemodReset();
686 LED_B_OFF();
687 }
688 ReaderIsActive = (Uart.state != STATE_UNSYNCD);
689 }
690
691 if(!ReaderIsActive) { // no need to try decoding tag data if the reader is sending - and we cannot afford the time
692 uint8_t tagdata = (previous_data << 4) | (*data & 0x0F);
693 if(ManchesterDecoding(tagdata, 0, (rsamples-1)*4)) {
694 LED_B_ON();
695
696 if (!LogTrace(receivedResponse,
697 Demod.len,
698 Demod.startTime*16 - DELAY_TAG_AIR2ARM_AS_SNIFFER,
699 Demod.endTime*16 - DELAY_TAG_AIR2ARM_AS_SNIFFER,
700 Demod.parity,
701 false)) break;
702
703 if ((!triggered) && (param & 0x01)) triggered = true;
704
705 // And ready to receive another response.
706 DemodReset();
707 // And reset the Miller decoder including itS (now outdated) input buffer
708 UartInit(receivedCmd, receivedCmdPar);
709
710 LED_C_OFF();
711 }
712 TagIsActive = (Demod.state != DEMOD_UNSYNCD);
713 }
714 }
715
716 previous_data = *data;
717 rsamples++;
718 data++;
719 if(data == dmaBuf + DMA_BUFFER_SIZE) {
720 data = dmaBuf;
721 }
722 } // main cycle
723
724 DbpString("COMMAND FINISHED");
725
726 FpgaDisableSscDma();
727 Dbprintf("maxDataLen=%d, Uart.state=%x, Uart.len=%d", maxDataLen, Uart.state, Uart.len);
728 Dbprintf("traceLen=%d, Uart.output[0]=%08x", BigBuf_get_traceLen(), (uint32_t)Uart.output[0]);
729 LEDsoff();
730 }
731
732 //-----------------------------------------------------------------------------
733 // Prepare tag messages
734 //-----------------------------------------------------------------------------
735 static void CodeIso14443aAsTagPar(const uint8_t *cmd, uint16_t len, uint8_t *parity)
736 {
737 ToSendReset();
738
739 // Correction bit, might be removed when not needed
740 ToSendStuffBit(0);
741 ToSendStuffBit(0);
742 ToSendStuffBit(0);
743 ToSendStuffBit(0);
744 ToSendStuffBit(1); // 1
745 ToSendStuffBit(0);
746 ToSendStuffBit(0);
747 ToSendStuffBit(0);
748
749 // Send startbit
750 ToSend[++ToSendMax] = SEC_D;
751 LastProxToAirDuration = 8 * ToSendMax - 4;
752
753 for(uint16_t i = 0; i < len; i++) {
754 uint8_t b = cmd[i];
755
756 // Data bits
757 for(uint16_t j = 0; j < 8; j++) {
758 if(b & 1) {
759 ToSend[++ToSendMax] = SEC_D;
760 } else {
761 ToSend[++ToSendMax] = SEC_E;
762 }
763 b >>= 1;
764 }
765
766 // Get the parity bit
767 if (parity[i>>3] & (0x80>>(i&0x0007))) {
768 ToSend[++ToSendMax] = SEC_D;
769 LastProxToAirDuration = 8 * ToSendMax - 4;
770 } else {
771 ToSend[++ToSendMax] = SEC_E;
772 LastProxToAirDuration = 8 * ToSendMax;
773 }
774 }
775
776 // Send stopbit
777 ToSend[++ToSendMax] = SEC_F;
778
779 // Convert from last byte pos to length
780 ToSendMax++;
781 }
782
783
784 static void Code4bitAnswerAsTag(uint8_t cmd)
785 {
786 int i;
787
788 ToSendReset();
789
790 // Correction bit, might be removed when not needed
791 ToSendStuffBit(0);
792 ToSendStuffBit(0);
793 ToSendStuffBit(0);
794 ToSendStuffBit(0);
795 ToSendStuffBit(1); // 1
796 ToSendStuffBit(0);
797 ToSendStuffBit(0);
798 ToSendStuffBit(0);
799
800 // Send startbit
801 ToSend[++ToSendMax] = SEC_D;
802
803 uint8_t b = cmd;
804 for(i = 0; i < 4; i++) {
805 if(b & 1) {
806 ToSend[++ToSendMax] = SEC_D;
807 LastProxToAirDuration = 8 * ToSendMax - 4;
808 } else {
809 ToSend[++ToSendMax] = SEC_E;
810 LastProxToAirDuration = 8 * ToSendMax;
811 }
812 b >>= 1;
813 }
814
815 // Send stopbit
816 ToSend[++ToSendMax] = SEC_F;
817
818 // Convert from last byte pos to length
819 ToSendMax++;
820 }
821
822
823 static uint8_t *LastReaderTraceTime = NULL;
824
825 static void EmLogTraceReader(void) {
826 // remember last reader trace start to fix timing info later
827 LastReaderTraceTime = BigBuf_get_addr() + BigBuf_get_traceLen();
828 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, true);
829 }
830
831
832 static void FixLastReaderTraceTime(uint32_t tag_StartTime) {
833 uint32_t reader_EndTime = Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG;
834 uint32_t reader_StartTime = Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG;
835 uint16_t reader_modlen = reader_EndTime - reader_StartTime;
836 uint16_t approx_fdt = tag_StartTime - reader_EndTime;
837 uint16_t exact_fdt = (approx_fdt - 20 + 32)/64 * 64 + 20;
838 reader_StartTime = tag_StartTime - exact_fdt - reader_modlen;
839 LastReaderTraceTime[0] = (reader_StartTime >> 0) & 0xff;
840 LastReaderTraceTime[1] = (reader_StartTime >> 8) & 0xff;
841 LastReaderTraceTime[2] = (reader_StartTime >> 16) & 0xff;
842 LastReaderTraceTime[3] = (reader_StartTime >> 24) & 0xff;
843 }
844
845
846 static void EmLogTraceTag(uint8_t *tag_data, uint16_t tag_len, uint8_t *tag_Parity, uint32_t ProxToAirDuration) {
847 uint32_t tag_StartTime = LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_TAG;
848 uint32_t tag_EndTime = (LastTimeProxToAirStart + ProxToAirDuration)*16 + DELAY_ARM2AIR_AS_TAG;
849 LogTrace(tag_data, tag_len, tag_StartTime, tag_EndTime, tag_Parity, false);
850 FixLastReaderTraceTime(tag_StartTime);
851 }
852
853
854 //-----------------------------------------------------------------------------
855 // Wait for commands from reader
856 // Stop when button is pressed
857 // Or return true when command is captured
858 //-----------------------------------------------------------------------------
859 static int GetIso14443aCommandFromReader(uint8_t *received, uint8_t *parity, int *len)
860 {
861 // Set FPGA mode to "simulated ISO 14443 tag", no modulation (listen
862 // only, since we are receiving, not transmitting).
863 // Signal field is off with the appropriate LED
864 LED_D_OFF();
865 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_LISTEN);
866
867 // Now run a `software UART' on the stream of incoming samples.
868 UartInit(received, parity);
869
870 // clear RXRDY:
871 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
872
873 for(;;) {
874 WDT_HIT();
875
876 if(BUTTON_PRESS()) return false;
877
878 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
879 b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
880 if(MillerDecoding(b, 0)) {
881 *len = Uart.len;
882 EmLogTraceReader();
883 return true;
884 }
885 }
886 }
887 }
888
889
890 static int EmSend4bitEx(uint8_t resp);
891 int EmSend4bit(uint8_t resp);
892 static int EmSendCmdExPar(uint8_t *resp, uint16_t respLen, uint8_t *par);
893 int EmSendCmdEx(uint8_t *resp, uint16_t respLen);
894 int EmSendPrecompiledCmd(tag_response_info_t *response_info);
895
896
897 static bool prepare_tag_modulation(tag_response_info_t* response_info, size_t max_buffer_size) {
898 // Example response, answer to MIFARE Classic read block will be 16 bytes + 2 CRC = 18 bytes
899 // This will need the following byte array for a modulation sequence
900 // 144 data bits (18 * 8)
901 // 18 parity bits
902 // 2 Start and stop
903 // 1 Correction bit (Answer in 1172 or 1236 periods, see FPGA)
904 // 1 just for the case
905 // ----------- +
906 // 166 bytes, since every bit that needs to be send costs us a byte
907 //
908
909
910 // Prepare the tag modulation bits from the message
911 GetParity(response_info->response, response_info->response_n, &(response_info->par));
912 CodeIso14443aAsTagPar(response_info->response,response_info->response_n, &(response_info->par));
913
914 // Make sure we do not exceed the free buffer space
915 if (ToSendMax > max_buffer_size) {
916 Dbprintf("Out of memory, when modulating bits for tag answer:");
917 Dbhexdump(response_info->response_n, response_info->response, false);
918 return false;
919 }
920
921 // Copy the byte array, used for this modulation to the buffer position
922 memcpy(response_info->modulation, ToSend, ToSendMax);
923
924 // Store the number of bytes that were used for encoding/modulation and the time needed to transfer them
925 response_info->modulation_n = ToSendMax;
926 response_info->ProxToAirDuration = LastProxToAirDuration;
927
928 return true;
929 }
930
931
932 // "precompile" responses. There are 7 predefined responses with a total of 28 bytes data to transmit.
933 // Coded responses need one byte per bit to transfer (data, parity, start, stop, correction)
934 // 28 * 8 data bits, 28 * 1 parity bits, 7 start bits, 7 stop bits, 7 correction bits for the modulation
935 // -> need 273 bytes buffer
936 #define ALLOCATED_TAG_MODULATION_BUFFER_SIZE 273
937
938 bool prepare_allocated_tag_modulation(tag_response_info_t* response_info, uint8_t **buffer, size_t *max_buffer_size) {
939
940 // Retrieve and store the current buffer index
941 response_info->modulation = *buffer;
942
943 // Forward the prepare tag modulation function to the inner function
944 if (prepare_tag_modulation(response_info, *max_buffer_size)) {
945 // Update the free buffer offset and the remaining buffer size
946 *buffer += ToSendMax;
947 *max_buffer_size -= ToSendMax;
948 return true;
949 } else {
950 return false;
951 }
952 }
953
954 //-----------------------------------------------------------------------------
955 // Main loop of simulated tag: receive commands from reader, decide what
956 // response to send, and send it.
957 //-----------------------------------------------------------------------------
958 void SimulateIso14443aTag(int tagType, int uid_1st, int uid_2nd, byte_t* data)
959 {
960 uint8_t sak;
961
962 // The first response contains the ATQA (note: bytes are transmitted in reverse order).
963 uint8_t response1[2];
964
965 switch (tagType) {
966 case 1: { // MIFARE Classic
967 // Says: I am Mifare 1k - original line
968 response1[0] = 0x04;
969 response1[1] = 0x00;
970 sak = 0x08;
971 } break;
972 case 2: { // MIFARE Ultralight
973 // Says: I am a stupid memory tag, no crypto
974 response1[0] = 0x04;
975 response1[1] = 0x00;
976 sak = 0x00;
977 } break;
978 case 3: { // MIFARE DESFire
979 // Says: I am a DESFire tag, ph33r me
980 response1[0] = 0x04;
981 response1[1] = 0x03;
982 sak = 0x20;
983 } break;
984 case 4: { // ISO/IEC 14443-4
985 // Says: I am a javacard (JCOP)
986 response1[0] = 0x04;
987 response1[1] = 0x00;
988 sak = 0x28;
989 } break;
990 case 5: { // MIFARE TNP3XXX
991 // Says: I am a toy
992 response1[0] = 0x01;
993 response1[1] = 0x0f;
994 sak = 0x01;
995 } break;
996 default: {
997 Dbprintf("Error: unkown tagtype (%d)",tagType);
998 return;
999 } break;
1000 }
1001
1002 // The second response contains the (mandatory) first 24 bits of the UID
1003 uint8_t response2[5] = {0x00};
1004
1005 // Check if the uid uses the (optional) part
1006 uint8_t response2a[5] = {0x00};
1007
1008 if (uid_2nd) {
1009 response2[0] = 0x88;
1010 num_to_bytes(uid_1st,3,response2+1);
1011 num_to_bytes(uid_2nd,4,response2a);
1012 response2a[4] = response2a[0] ^ response2a[1] ^ response2a[2] ^ response2a[3];
1013
1014 // Configure the ATQA and SAK accordingly
1015 response1[0] |= 0x40;
1016 sak |= 0x04;
1017 } else {
1018 num_to_bytes(uid_1st,4,response2);
1019 // Configure the ATQA and SAK accordingly
1020 response1[0] &= 0xBF;
1021 sak &= 0xFB;
1022 }
1023
1024 // Calculate the BitCountCheck (BCC) for the first 4 bytes of the UID.
1025 response2[4] = response2[0] ^ response2[1] ^ response2[2] ^ response2[3];
1026
1027 // Prepare the mandatory SAK (for 4 and 7 byte UID)
1028 uint8_t response3[3] = {0x00};
1029 response3[0] = sak;
1030 ComputeCrc14443(CRC_14443_A, response3, 1, &response3[1], &response3[2]);
1031
1032 // Prepare the optional second SAK (for 7 byte UID), drop the cascade bit
1033 uint8_t response3a[3] = {0x00};
1034 response3a[0] = sak & 0xFB;
1035 ComputeCrc14443(CRC_14443_A, response3a, 1, &response3a[1], &response3a[2]);
1036
1037 uint8_t response5[] = { 0x00, 0x00, 0x00, 0x00 }; // Very random tag nonce
1038 uint8_t response6[] = { 0x04, 0x58, 0x80, 0x02, 0x00, 0x00 }; // dummy ATS (pseudo-ATR), answer to RATS:
1039 // Format byte = 0x58: FSCI=0x08 (FSC=256), TA(1) and TC(1) present,
1040 // TA(1) = 0x80: different divisors not supported, DR = 1, DS = 1
1041 // TB(1) = not present. Defaults: FWI = 4 (FWT = 256 * 16 * 2^4 * 1/fc = 4833us), SFGI = 0 (SFG = 256 * 16 * 2^0 * 1/fc = 302us)
1042 // TC(1) = 0x02: CID supported, NAD not supported
1043 ComputeCrc14443(CRC_14443_A, response6, 4, &response6[4], &response6[5]);
1044
1045 #define TAG_RESPONSE_COUNT 7
1046 tag_response_info_t responses[TAG_RESPONSE_COUNT] = {
1047 { .response = response1, .response_n = sizeof(response1) }, // Answer to request - respond with card type
1048 { .response = response2, .response_n = sizeof(response2) }, // Anticollision cascade1 - respond with uid
1049 { .response = response2a, .response_n = sizeof(response2a) }, // Anticollision cascade2 - respond with 2nd half of uid if asked
1050 { .response = response3, .response_n = sizeof(response3) }, // Acknowledge select - cascade 1
1051 { .response = response3a, .response_n = sizeof(response3a) }, // Acknowledge select - cascade 2
1052 { .response = response5, .response_n = sizeof(response5) }, // Authentication answer (random nonce)
1053 { .response = response6, .response_n = sizeof(response6) }, // dummy ATS (pseudo-ATR), answer to RATS
1054 };
1055
1056 // Allocate 512 bytes for the dynamic modulation, created when the reader queries for it
1057 // Such a response is less time critical, so we can prepare them on the fly
1058 #define DYNAMIC_RESPONSE_BUFFER_SIZE 64
1059 #define DYNAMIC_MODULATION_BUFFER_SIZE 512
1060 uint8_t dynamic_response_buffer[DYNAMIC_RESPONSE_BUFFER_SIZE];
1061 uint8_t dynamic_modulation_buffer[DYNAMIC_MODULATION_BUFFER_SIZE];
1062 tag_response_info_t dynamic_response_info = {
1063 .response = dynamic_response_buffer,
1064 .response_n = 0,
1065 .modulation = dynamic_modulation_buffer,
1066 .modulation_n = 0
1067 };
1068
1069 // We need to listen to the high-frequency, peak-detected path.
1070 iso14443a_setup(FPGA_HF_ISO14443A_TAGSIM_LISTEN);
1071
1072 BigBuf_free_keep_EM();
1073
1074 // allocate buffers:
1075 uint8_t *receivedCmd = BigBuf_malloc(MAX_FRAME_SIZE);
1076 uint8_t *receivedCmdPar = BigBuf_malloc(MAX_PARITY_SIZE);
1077 uint8_t *free_buffer_pointer = BigBuf_malloc(ALLOCATED_TAG_MODULATION_BUFFER_SIZE);
1078 size_t free_buffer_size = ALLOCATED_TAG_MODULATION_BUFFER_SIZE;
1079 // clear trace
1080 clear_trace();
1081 set_tracing(true);
1082
1083 // Prepare the responses of the anticollision phase
1084 // there will be not enough time to do this at the moment the reader sends it REQA
1085 for (size_t i=0; i<TAG_RESPONSE_COUNT; i++) {
1086 prepare_allocated_tag_modulation(&responses[i], &free_buffer_pointer, &free_buffer_size);
1087 }
1088
1089 int len = 0;
1090
1091 // To control where we are in the protocol
1092 int order = 0;
1093 int lastorder;
1094
1095 // Just to allow some checks
1096 int happened = 0;
1097 int happened2 = 0;
1098 int cmdsRecvd = 0;
1099
1100 cmdsRecvd = 0;
1101 tag_response_info_t* p_response;
1102
1103 LED_A_ON();
1104 for(;;) {
1105 // Clean receive command buffer
1106 if(!GetIso14443aCommandFromReader(receivedCmd, receivedCmdPar, &len)) {
1107 DbpString("Button press");
1108 break;
1109 }
1110
1111 p_response = NULL;
1112
1113 // Okay, look at the command now.
1114 lastorder = order;
1115 if(receivedCmd[0] == 0x26) { // Received a REQUEST
1116 p_response = &responses[0]; order = 1;
1117 } else if(receivedCmd[0] == 0x52) { // Received a WAKEUP
1118 p_response = &responses[0]; order = 6;
1119 } else if(receivedCmd[1] == 0x20 && receivedCmd[0] == 0x93) { // Received request for UID (cascade 1)
1120 p_response = &responses[1]; order = 2;
1121 } else if(receivedCmd[1] == 0x20 && receivedCmd[0] == 0x95) { // Received request for UID (cascade 2)
1122 p_response = &responses[2]; order = 20;
1123 } else if(receivedCmd[1] == 0x70 && receivedCmd[0] == 0x93) { // Received a SELECT (cascade 1)
1124 p_response = &responses[3]; order = 3;
1125 } else if(receivedCmd[1] == 0x70 && receivedCmd[0] == 0x95) { // Received a SELECT (cascade 2)
1126 p_response = &responses[4]; order = 30;
1127 } else if(receivedCmd[0] == 0x30) { // Received a (plain) READ
1128 EmSendCmdEx(data+(4*receivedCmd[1]),16);
1129 // Dbprintf("Read request from reader: %x %x",receivedCmd[0],receivedCmd[1]);
1130 // We already responded, do not send anything with the EmSendCmd14443aRaw() that is called below
1131 p_response = NULL;
1132 } else if(receivedCmd[0] == 0x50) { // Received a HALT
1133 p_response = NULL;
1134 } else if(receivedCmd[0] == 0x60 || receivedCmd[0] == 0x61) { // Received an authentication request
1135 p_response = &responses[5]; order = 7;
1136 } else if(receivedCmd[0] == 0xE0) { // Received a RATS request
1137 if (tagType == 1 || tagType == 2) { // RATS not supported
1138 EmSend4bit(CARD_NACK_NA);
1139 p_response = NULL;
1140 } else {
1141 p_response = &responses[6]; order = 70;
1142 }
1143 } else if (order == 7 && len == 8) { // Received {nr] and {ar} (part of authentication)
1144 uint32_t nr = bytes_to_num(receivedCmd,4);
1145 uint32_t ar = bytes_to_num(receivedCmd+4,4);
1146 Dbprintf("Auth attempt {nr}{ar}: %08x %08x",nr,ar);
1147 } else {
1148 // Check for ISO 14443A-4 compliant commands, look at left nibble
1149 switch (receivedCmd[0]) {
1150
1151 case 0x0B:
1152 case 0x0A: { // IBlock (command)
1153 dynamic_response_info.response[0] = receivedCmd[0];
1154 dynamic_response_info.response[1] = 0x00;
1155 dynamic_response_info.response[2] = 0x90;
1156 dynamic_response_info.response[3] = 0x00;
1157 dynamic_response_info.response_n = 4;
1158 } break;
1159
1160 case 0x1A:
1161 case 0x1B: { // Chaining command
1162 dynamic_response_info.response[0] = 0xaa | ((receivedCmd[0]) & 1);
1163 dynamic_response_info.response_n = 2;
1164 } break;
1165
1166 case 0xaa:
1167 case 0xbb: {
1168 dynamic_response_info.response[0] = receivedCmd[0] ^ 0x11;
1169 dynamic_response_info.response_n = 2;
1170 } break;
1171
1172 case 0xBA: { //
1173 memcpy(dynamic_response_info.response,"\xAB\x00",2);
1174 dynamic_response_info.response_n = 2;
1175 } break;
1176
1177 case 0xCA:
1178 case 0xC2: { // Readers sends deselect command
1179 memcpy(dynamic_response_info.response,"\xCA\x00",2);
1180 dynamic_response_info.response_n = 2;
1181 } break;
1182
1183 default: {
1184 // Never seen this command before
1185 Dbprintf("Received unknown command (len=%d):",len);
1186 Dbhexdump(len,receivedCmd,false);
1187 // Do not respond
1188 dynamic_response_info.response_n = 0;
1189 } break;
1190 }
1191
1192 if (dynamic_response_info.response_n > 0) {
1193 // Copy the CID from the reader query
1194 dynamic_response_info.response[1] = receivedCmd[1];
1195
1196 // Add CRC bytes, always used in ISO 14443A-4 compliant cards
1197 AppendCrc14443a(dynamic_response_info.response,dynamic_response_info.response_n);
1198 dynamic_response_info.response_n += 2;
1199
1200 if (prepare_tag_modulation(&dynamic_response_info,DYNAMIC_MODULATION_BUFFER_SIZE) == false) {
1201 Dbprintf("Error preparing tag response");
1202 break;
1203 }
1204 p_response = &dynamic_response_info;
1205 }
1206 }
1207
1208 // Count number of wakeups received after a halt
1209 if(order == 6 && lastorder == 5) { happened++; }
1210
1211 // Count number of other messages after a halt
1212 if(order != 6 && lastorder == 5) { happened2++; }
1213
1214 if(cmdsRecvd > 999) {
1215 DbpString("1000 commands later...");
1216 break;
1217 }
1218 cmdsRecvd++;
1219
1220 if (p_response != NULL) {
1221 EmSendPrecompiledCmd(p_response);
1222 }
1223
1224 if (!get_tracing()) {
1225 Dbprintf("Trace Full. Simulation stopped.");
1226 break;
1227 }
1228 }
1229
1230 Dbprintf("%x %x %x", happened, happened2, cmdsRecvd);
1231 LED_A_OFF();
1232 BigBuf_free_keep_EM();
1233 }
1234
1235
1236 // prepare a delayed transfer. This simply shifts ToSend[] by a number
1237 // of bits specified in the delay parameter.
1238 static void PrepareDelayedTransfer(uint16_t delay)
1239 {
1240 uint8_t bitmask = 0;
1241 uint8_t bits_to_shift = 0;
1242 uint8_t bits_shifted = 0;
1243
1244 delay &= 0x07;
1245 if (delay) {
1246 for (uint16_t i = 0; i < delay; i++) {
1247 bitmask |= (0x01 << i);
1248 }
1249 ToSend[ToSendMax++] = 0x00;
1250 for (uint16_t i = 0; i < ToSendMax; i++) {
1251 bits_to_shift = ToSend[i] & bitmask;
1252 ToSend[i] = ToSend[i] >> delay;
1253 ToSend[i] = ToSend[i] | (bits_shifted << (8 - delay));
1254 bits_shifted = bits_to_shift;
1255 }
1256 }
1257 }
1258
1259
1260 //-------------------------------------------------------------------------------------
1261 // Transmit the command (to the tag) that was placed in ToSend[].
1262 // Parameter timing:
1263 // if NULL: transfer at next possible time, taking into account
1264 // request guard time, startup frame guard time and frame delay time
1265 // if == 0: transfer immediately and return time of transfer
1266 // if != 0: delay transfer until time specified
1267 //-------------------------------------------------------------------------------------
1268 static void TransmitFor14443a(const uint8_t *cmd, uint16_t len, uint32_t *timing)
1269 {
1270
1271 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_MOD);
1272
1273 uint32_t ThisTransferTime = 0;
1274
1275 if (timing) {
1276 if(*timing == 0) { // Measure time
1277 *timing = (GetCountSspClk() + 8) & 0xfffffff8;
1278 } else {
1279 PrepareDelayedTransfer(*timing & 0x00000007); // Delay transfer (fine tuning - up to 7 MF clock ticks)
1280 }
1281 if(MF_DBGLEVEL >= 4 && GetCountSspClk() >= (*timing & 0xfffffff8)) Dbprintf("TransmitFor14443a: Missed timing");
1282 while(GetCountSspClk() < (*timing & 0xfffffff8)); // Delay transfer (multiple of 8 MF clock ticks)
1283 LastTimeProxToAirStart = *timing;
1284 } else {
1285 ThisTransferTime = ((MAX(NextTransferTime, GetCountSspClk()) & 0xfffffff8) + 8);
1286 while(GetCountSspClk() < ThisTransferTime);
1287 LastTimeProxToAirStart = ThisTransferTime;
1288 }
1289
1290 // clear TXRDY
1291 AT91C_BASE_SSC->SSC_THR = SEC_Y;
1292
1293 uint16_t c = 0;
1294 for(;;) {
1295 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1296 AT91C_BASE_SSC->SSC_THR = cmd[c];
1297 c++;
1298 if(c >= len) {
1299 break;
1300 }
1301 }
1302 }
1303
1304 NextTransferTime = MAX(NextTransferTime, LastTimeProxToAirStart + REQUEST_GUARD_TIME);
1305 }
1306
1307
1308 //-----------------------------------------------------------------------------
1309 // Prepare reader command (in bits, support short frames) to send to FPGA
1310 //-----------------------------------------------------------------------------
1311 static void CodeIso14443aBitsAsReaderPar(const uint8_t *cmd, uint16_t bits, const uint8_t *parity)
1312 {
1313 int i, j;
1314 int last;
1315 uint8_t b;
1316
1317 ToSendReset();
1318
1319 // Start of Communication (Seq. Z)
1320 ToSend[++ToSendMax] = SEC_Z;
1321 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1322 last = 0;
1323
1324 size_t bytecount = nbytes(bits);
1325 // Generate send structure for the data bits
1326 for (i = 0; i < bytecount; i++) {
1327 // Get the current byte to send
1328 b = cmd[i];
1329 size_t bitsleft = MIN((bits-(i*8)),8);
1330
1331 for (j = 0; j < bitsleft; j++) {
1332 if (b & 1) {
1333 // Sequence X
1334 ToSend[++ToSendMax] = SEC_X;
1335 LastProxToAirDuration = 8 * (ToSendMax+1) - 2;
1336 last = 1;
1337 } else {
1338 if (last == 0) {
1339 // Sequence Z
1340 ToSend[++ToSendMax] = SEC_Z;
1341 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1342 } else {
1343 // Sequence Y
1344 ToSend[++ToSendMax] = SEC_Y;
1345 last = 0;
1346 }
1347 }
1348 b >>= 1;
1349 }
1350
1351 // Only transmit parity bit if we transmitted a complete byte
1352 if (j == 8 && parity != NULL) {
1353 // Get the parity bit
1354 if (parity[i>>3] & (0x80 >> (i&0x0007))) {
1355 // Sequence X
1356 ToSend[++ToSendMax] = SEC_X;
1357 LastProxToAirDuration = 8 * (ToSendMax+1) - 2;
1358 last = 1;
1359 } else {
1360 if (last == 0) {
1361 // Sequence Z
1362 ToSend[++ToSendMax] = SEC_Z;
1363 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1364 } else {
1365 // Sequence Y
1366 ToSend[++ToSendMax] = SEC_Y;
1367 last = 0;
1368 }
1369 }
1370 }
1371 }
1372
1373 // End of Communication: Logic 0 followed by Sequence Y
1374 if (last == 0) {
1375 // Sequence Z
1376 ToSend[++ToSendMax] = SEC_Z;
1377 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1378 } else {
1379 // Sequence Y
1380 ToSend[++ToSendMax] = SEC_Y;
1381 last = 0;
1382 }
1383 ToSend[++ToSendMax] = SEC_Y;
1384
1385 // Convert to length of command:
1386 ToSendMax++;
1387 }
1388
1389
1390 //-----------------------------------------------------------------------------
1391 // Wait for commands from reader
1392 // Stop when button is pressed (return 1) or field was gone (return 2)
1393 // Or return 0 when command is captured
1394 //-----------------------------------------------------------------------------
1395 int EmGetCmd(uint8_t *received, uint16_t *len, uint8_t *parity)
1396 {
1397 *len = 0;
1398
1399 uint32_t timer = 0, vtime = 0;
1400 int analogCnt = 0;
1401 int analogAVG = 0;
1402
1403 // Set ADC to read field strength
1404 AT91C_BASE_ADC->ADC_CR = AT91C_ADC_SWRST;
1405 AT91C_BASE_ADC->ADC_MR =
1406 ADC_MODE_PRESCALE(63) |
1407 ADC_MODE_STARTUP_TIME(1) |
1408 ADC_MODE_SAMPLE_HOLD_TIME(15);
1409 AT91C_BASE_ADC->ADC_CHER = ADC_CHANNEL(ADC_CHAN_HF_LOW);
1410 // start ADC
1411 AT91C_BASE_ADC->ADC_CR = AT91C_ADC_START;
1412
1413 // Run a 'software UART' on the stream of incoming samples.
1414 UartInit(received, parity);
1415
1416 // Ensure that the FPGA Delay Queue is empty before we switch to TAGSIM_LISTEN
1417 do {
1418 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1419 AT91C_BASE_SSC->SSC_THR = SEC_F;
1420 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR; (void) b;
1421 }
1422 } while (GetCountSspClk() < LastTimeProxToAirStart + LastProxToAirDuration + (FpgaSendQueueDelay>>3));
1423
1424 // Set FPGA mode to "simulated ISO 14443 tag", no modulation (listen
1425 // only, since we are receiving, not transmitting).
1426 // Signal field is off with the appropriate LED
1427 LED_D_OFF();
1428 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_LISTEN);
1429
1430 for(;;) {
1431 WDT_HIT();
1432
1433 if (BUTTON_PRESS()) return 1;
1434
1435 // test if the field exists
1436 if (AT91C_BASE_ADC->ADC_SR & ADC_END_OF_CONVERSION(ADC_CHAN_HF_LOW)) {
1437 analogCnt++;
1438 analogAVG += AT91C_BASE_ADC->ADC_CDR[ADC_CHAN_HF_LOW];
1439 AT91C_BASE_ADC->ADC_CR = AT91C_ADC_START;
1440 if (analogCnt >= 32) {
1441 if ((MAX_ADC_HF_VOLTAGE_LOW * (analogAVG / analogCnt) >> 10) < MF_MINFIELDV) {
1442 vtime = GetTickCount();
1443 if (!timer) timer = vtime;
1444 // 50ms no field --> card to idle state
1445 if (vtime - timer > 50) return 2;
1446 } else
1447 if (timer) timer = 0;
1448 analogCnt = 0;
1449 analogAVG = 0;
1450 }
1451 }
1452
1453 // receive and test the miller decoding
1454 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
1455 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1456 if(MillerDecoding(b, 0)) {
1457 *len = Uart.len;
1458 EmLogTraceReader();
1459 return 0;
1460 }
1461 }
1462
1463 }
1464 }
1465
1466
1467 static int EmSendCmd14443aRaw(uint8_t *resp, uint16_t respLen)
1468 {
1469 uint8_t b;
1470 uint16_t i = 0;
1471 bool correctionNeeded;
1472
1473 // Modulate Manchester
1474 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_MOD);
1475
1476 // include correction bit if necessary
1477 if (Uart.bitCount == 7)
1478 {
1479 // Short tags (7 bits) don't have parity, determine the correct value from MSB
1480 correctionNeeded = Uart.output[0] & 0x40;
1481 }
1482 else
1483 {
1484 // Look at the last parity bit
1485 correctionNeeded = Uart.parity[(Uart.len-1)/8] & (0x80 >> ((Uart.len-1) & 7));
1486 }
1487
1488 if(correctionNeeded) {
1489 // 1236, so correction bit needed
1490 i = 0;
1491 } else {
1492 i = 1;
1493 }
1494
1495 // clear receiving shift register and holding register
1496 while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
1497 b = AT91C_BASE_SSC->SSC_RHR; (void) b;
1498 while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
1499 b = AT91C_BASE_SSC->SSC_RHR; (void) b;
1500
1501 // wait for the FPGA to signal fdt_indicator == 1 (the FPGA is ready to queue new data in its delay line)
1502 for (uint16_t j = 0; j < 5; j++) { // allow timeout - better late than never
1503 while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
1504 if (AT91C_BASE_SSC->SSC_RHR) break;
1505 }
1506
1507 LastTimeProxToAirStart = (GetCountSspClk() & 0xfffffff8) + (correctionNeeded?8:0);
1508
1509 // send cycle
1510 for(; i < respLen; ) {
1511 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1512 AT91C_BASE_SSC->SSC_THR = resp[i++];
1513 FpgaSendQueueDelay = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1514 }
1515
1516 if(BUTTON_PRESS()) {
1517 break;
1518 }
1519 }
1520
1521 return 0;
1522 }
1523
1524
1525 static int EmSend4bitEx(uint8_t resp){
1526 Code4bitAnswerAsTag(resp);
1527 int res = EmSendCmd14443aRaw(ToSend, ToSendMax);
1528 // do the tracing for the previous reader request and this tag answer:
1529 EmLogTraceTag(&resp, 1, NULL, LastProxToAirDuration);
1530 return res;
1531 }
1532
1533
1534 int EmSend4bit(uint8_t resp){
1535 return EmSend4bitEx(resp);
1536 }
1537
1538
1539 static int EmSendCmdExPar(uint8_t *resp, uint16_t respLen, uint8_t *par){
1540 CodeIso14443aAsTagPar(resp, respLen, par);
1541 int res = EmSendCmd14443aRaw(ToSend, ToSendMax);
1542 // do the tracing for the previous reader request and this tag answer:
1543 EmLogTraceTag(resp, respLen, par, LastProxToAirDuration);
1544 return res;
1545 }
1546
1547
1548 int EmSendCmdEx(uint8_t *resp, uint16_t respLen){
1549 uint8_t par[MAX_PARITY_SIZE];
1550 GetParity(resp, respLen, par);
1551 return EmSendCmdExPar(resp, respLen, par);
1552 }
1553
1554
1555 int EmSendCmd(uint8_t *resp, uint16_t respLen){
1556 uint8_t par[MAX_PARITY_SIZE];
1557 GetParity(resp, respLen, par);
1558 return EmSendCmdExPar(resp, respLen, par);
1559 }
1560
1561
1562 int EmSendCmdPar(uint8_t *resp, uint16_t respLen, uint8_t *par){
1563 return EmSendCmdExPar(resp, respLen, par);
1564 }
1565
1566
1567 int EmSendPrecompiledCmd(tag_response_info_t *response_info) {
1568 int ret = EmSendCmd14443aRaw(response_info->modulation, response_info->modulation_n);
1569 // do the tracing for the previous reader request and this tag answer:
1570 EmLogTraceTag(response_info->response, response_info->response_n, &(response_info->par), response_info->ProxToAirDuration);
1571 return ret;
1572 }
1573
1574
1575 //-----------------------------------------------------------------------------
1576 // Wait a certain time for tag response
1577 // If a response is captured return true
1578 // If it takes too long return false
1579 //-----------------------------------------------------------------------------
1580 static int GetIso14443aAnswerFromTag(uint8_t *receivedResponse, uint8_t *receivedResponsePar, uint16_t offset)
1581 {
1582 uint32_t c;
1583
1584 // Set FPGA mode to "reader listen mode", no modulation (listen
1585 // only, since we are receiving, not transmitting).
1586 // Signal field is on with the appropriate LED
1587 LED_D_ON();
1588 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_LISTEN);
1589
1590 // Now get the answer from the card
1591 DemodInit(receivedResponse, receivedResponsePar);
1592
1593 // clear RXRDY:
1594 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1595
1596 c = 0;
1597 for(;;) {
1598 WDT_HIT();
1599
1600 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
1601 b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1602 if(ManchesterDecoding(b, offset, 0)) {
1603 NextTransferTime = MAX(NextTransferTime, Demod.endTime - (DELAY_AIR2ARM_AS_READER + DELAY_ARM2AIR_AS_READER)/16 + FRAME_DELAY_TIME_PICC_TO_PCD);
1604 return true;
1605 } else if (c++ > iso14a_timeout && Demod.state == DEMOD_UNSYNCD) {
1606 return false;
1607 }
1608 }
1609 }
1610 }
1611
1612
1613 void ReaderTransmitBitsPar(uint8_t* frame, uint16_t bits, uint8_t *par, uint32_t *timing)
1614 {
1615 CodeIso14443aBitsAsReaderPar(frame, bits, par);
1616
1617 // Send command to tag
1618 TransmitFor14443a(ToSend, ToSendMax, timing);
1619 if(trigger)
1620 LED_A_ON();
1621
1622 // Log reader command in trace buffer
1623 LogTrace(frame, nbytes(bits), LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_READER, (LastTimeProxToAirStart + LastProxToAirDuration)*16 + DELAY_ARM2AIR_AS_READER, par, true);
1624 }
1625
1626
1627 void ReaderTransmitPar(uint8_t* frame, uint16_t len, uint8_t *par, uint32_t *timing)
1628 {
1629 ReaderTransmitBitsPar(frame, len*8, par, timing);
1630 }
1631
1632
1633 static void ReaderTransmitBits(uint8_t* frame, uint16_t len, uint32_t *timing)
1634 {
1635 // Generate parity and redirect
1636 uint8_t par[MAX_PARITY_SIZE];
1637 GetParity(frame, len/8, par);
1638 ReaderTransmitBitsPar(frame, len, par, timing);
1639 }
1640
1641
1642 void ReaderTransmit(uint8_t* frame, uint16_t len, uint32_t *timing)
1643 {
1644 // Generate parity and redirect
1645 uint8_t par[MAX_PARITY_SIZE];
1646 GetParity(frame, len, par);
1647 ReaderTransmitBitsPar(frame, len*8, par, timing);
1648 }
1649
1650
1651 static int ReaderReceiveOffset(uint8_t* receivedAnswer, uint16_t offset, uint8_t *parity)
1652 {
1653 if (!GetIso14443aAnswerFromTag(receivedAnswer, parity, offset)) return false;
1654 LogTrace(receivedAnswer, Demod.len, Demod.startTime*16 - DELAY_AIR2ARM_AS_READER, Demod.endTime*16 - DELAY_AIR2ARM_AS_READER, parity, false);
1655 return Demod.len;
1656 }
1657
1658
1659 int ReaderReceive(uint8_t *receivedAnswer, uint8_t *parity)
1660 {
1661 if (!GetIso14443aAnswerFromTag(receivedAnswer, parity, 0)) return false;
1662 LogTrace(receivedAnswer, Demod.len, Demod.startTime*16 - DELAY_AIR2ARM_AS_READER, Demod.endTime*16 - DELAY_AIR2ARM_AS_READER, parity, false);
1663 return Demod.len;
1664 }
1665
1666
1667 static void iso14a_set_ATS_times(uint8_t *ats) {
1668
1669 uint8_t tb1;
1670 uint8_t fwi, sfgi;
1671 uint32_t fwt, sfgt;
1672
1673 if (ats[0] > 1) { // there is a format byte T0
1674 if ((ats[1] & 0x20) == 0x20) { // there is an interface byte TB(1)
1675 if ((ats[1] & 0x10) == 0x10) { // there is an interface byte TA(1) preceding TB(1)
1676 tb1 = ats[3];
1677 } else {
1678 tb1 = ats[2];
1679 }
1680 fwi = (tb1 & 0xf0) >> 4; // frame waiting time integer (FWI)
1681 if (fwi != 15) {
1682 fwt = 256 * 16 * (1 << fwi); // frame waiting time (FWT) in 1/fc
1683 iso14a_set_timeout(fwt/(8*16));
1684 }
1685 sfgi = tb1 & 0x0f; // startup frame guard time integer (SFGI)
1686 if (sfgi != 0 && sfgi != 15) {
1687 sfgt = 256 * 16 * (1 << sfgi); // startup frame guard time (SFGT) in 1/fc
1688 NextTransferTime = MAX(NextTransferTime, Demod.endTime + (sfgt - DELAY_AIR2ARM_AS_READER - DELAY_ARM2AIR_AS_READER)/16);
1689 }
1690 }
1691 }
1692 }
1693
1694
1695 static int GetATQA(uint8_t *resp, uint8_t *resp_par) {
1696
1697 #define WUPA_RETRY_TIMEOUT 10 // 10ms
1698 uint8_t wupa[] = { 0x52 }; // 0x26 - REQA 0x52 - WAKE-UP
1699
1700 uint32_t save_iso14a_timeout = iso14a_get_timeout();
1701 iso14a_set_timeout(1236/(16*8)+1); // response to WUPA is expected at exactly 1236/fc. No need to wait longer.
1702
1703 uint32_t start_time = GetTickCount();
1704 int len;
1705
1706 // we may need several tries if we did send an unknown command or a wrong authentication before...
1707 do {
1708 // Broadcast for a card, WUPA (0x52) will force response from all cards in the field
1709 ReaderTransmitBitsPar(wupa, 7, NULL, NULL);
1710 // Receive the ATQA
1711 len = ReaderReceive(resp, resp_par);
1712 } while (len == 0 && GetTickCount() <= start_time + WUPA_RETRY_TIMEOUT);
1713
1714 iso14a_set_timeout(save_iso14a_timeout);
1715 return len;
1716 }
1717
1718
1719 // performs iso14443a anticollision (optional) and card select procedure
1720 // fills the uid and cuid pointer unless NULL
1721 // fills the card info record unless NULL
1722 // if anticollision is false, then the UID must be provided in uid_ptr[]
1723 // and num_cascades must be set (1: 4 Byte UID, 2: 7 Byte UID, 3: 10 Byte UID)
1724 // requests ATS unless no_rats is true
1725 int iso14443a_select_card(byte_t *uid_ptr, iso14a_card_select_t *p_hi14a_card, uint32_t *cuid_ptr, bool anticollision, uint8_t num_cascades, bool no_rats) {
1726 uint8_t sel_all[] = { 0x93,0x20 };
1727 uint8_t sel_uid[] = { 0x93,0x70,0x00,0x00,0x00,0x00,0x00,0x00,0x00};
1728 uint8_t rats[] = { 0xE0,0x80,0x00,0x00 }; // FSD=256, FSDI=8, CID=0
1729 uint8_t resp[MAX_FRAME_SIZE]; // theoretically. A usual RATS will be much smaller
1730 uint8_t resp_par[MAX_PARITY_SIZE];
1731 byte_t uid_resp[4];
1732 size_t uid_resp_len;
1733
1734 uint8_t sak = 0x04; // cascade uid
1735 int cascade_level = 0;
1736 int len;
1737
1738 // init card struct
1739 if(p_hi14a_card) {
1740 p_hi14a_card->uidlen = 0;
1741 memset(p_hi14a_card->uid, 0, 10);
1742 p_hi14a_card->ats_len = 0;
1743 }
1744
1745 if (!GetATQA(resp, resp_par)) {
1746 return 0;
1747 }
1748
1749 if(p_hi14a_card) {
1750 memcpy(p_hi14a_card->atqa, resp, 2);
1751 }
1752
1753 if (anticollision) {
1754 // clear uid
1755 if (uid_ptr) {
1756 memset(uid_ptr,0,10);
1757 }
1758 }
1759
1760 // check for proprietary anticollision:
1761 if ((resp[0] & 0x1F) == 0) {
1762 return 3;
1763 }
1764
1765 // OK we will select at least at cascade 1, lets see if first byte of UID was 0x88 in
1766 // which case we need to make a cascade 2 request and select - this is a long UID
1767 // While the UID is not complete, the 3nd bit (from the right) is set in the SAK.
1768 for(; sak & 0x04; cascade_level++) {
1769 // SELECT_* (L1: 0x93, L2: 0x95, L3: 0x97)
1770 sel_uid[0] = sel_all[0] = 0x93 + cascade_level * 2;
1771
1772 if (anticollision) {
1773 // SELECT_ALL
1774 ReaderTransmit(sel_all, sizeof(sel_all), NULL);
1775 if (!ReaderReceive(resp, resp_par)) {
1776 return 0;
1777 }
1778
1779 if (Demod.collisionPos) { // we had a collision and need to construct the UID bit by bit
1780 memset(uid_resp, 0, 4);
1781 uint16_t uid_resp_bits = 0;
1782 uint16_t collision_answer_offset = 0;
1783 // anti-collision-loop:
1784 while (Demod.collisionPos) {
1785 Dbprintf("Multiple tags detected. Collision after Bit %d", Demod.collisionPos);
1786 for (uint16_t i = collision_answer_offset; i < Demod.collisionPos; i++, uid_resp_bits++) { // add valid UID bits before collision point
1787 uint16_t UIDbit = (resp[i/8] >> (i % 8)) & 0x01;
1788 uid_resp[uid_resp_bits / 8] |= UIDbit << (uid_resp_bits % 8);
1789 }
1790 uid_resp[uid_resp_bits/8] |= 1 << (uid_resp_bits % 8); // next time select the card(s) with a 1 in the collision position
1791 uid_resp_bits++;
1792 // construct anticollosion command:
1793 sel_uid[1] = ((2 + uid_resp_bits/8) << 4) | (uid_resp_bits & 0x07); // length of data in bytes and bits
1794 for (uint16_t i = 0; i <= uid_resp_bits/8; i++) {
1795 sel_uid[2+i] = uid_resp[i];
1796 }
1797 collision_answer_offset = uid_resp_bits%8;
1798 ReaderTransmitBits(sel_uid, 16 + uid_resp_bits, NULL);
1799 if (!ReaderReceiveOffset(resp, collision_answer_offset, resp_par)) {
1800 return 0;
1801 }
1802 }
1803 // finally, add the last bits and BCC of the UID
1804 for (uint16_t i = collision_answer_offset; i < (Demod.len-1)*8; i++, uid_resp_bits++) {
1805 uint16_t UIDbit = (resp[i/8] >> (i%8)) & 0x01;
1806 uid_resp[uid_resp_bits/8] |= UIDbit << (uid_resp_bits % 8);
1807 }
1808
1809 } else { // no collision, use the response to SELECT_ALL as current uid
1810 memcpy(uid_resp, resp, 4);
1811 }
1812 } else {
1813 if (cascade_level < num_cascades - 1) {
1814 uid_resp[0] = 0x88;
1815 memcpy(uid_resp+1, uid_ptr+cascade_level*3, 3);
1816 } else {
1817 memcpy(uid_resp, uid_ptr+cascade_level*3, 4);
1818 }
1819 }
1820 uid_resp_len = 4;
1821
1822 // calculate crypto UID. Always use last 4 Bytes.
1823 if(cuid_ptr) {
1824 *cuid_ptr = bytes_to_num(uid_resp, 4);
1825 }
1826
1827 // Construct SELECT UID command
1828 sel_uid[1] = 0x70; // transmitting a full UID (1 Byte cmd, 1 Byte NVB, 4 Byte UID, 1 Byte BCC, 2 Bytes CRC)
1829 memcpy(sel_uid+2, uid_resp, 4); // the UID received during anticollision, or the provided UID
1830 sel_uid[6] = sel_uid[2] ^ sel_uid[3] ^ sel_uid[4] ^ sel_uid[5]; // calculate and add BCC
1831 AppendCrc14443a(sel_uid, 7); // calculate and add CRC
1832 ReaderTransmit(sel_uid, sizeof(sel_uid), NULL);
1833
1834 // Receive the SAK
1835 if (!ReaderReceive(resp, resp_par)) {
1836 return 0;
1837 }
1838 sak = resp[0];
1839
1840 // Test if more parts of the uid are coming
1841 if ((sak & 0x04) /* && uid_resp[0] == 0x88 */) {
1842 // Remove first byte, 0x88 is not an UID byte, it CT, see page 3 of:
1843 // http://www.nxp.com/documents/application_note/AN10927.pdf
1844 uid_resp[0] = uid_resp[1];
1845 uid_resp[1] = uid_resp[2];
1846 uid_resp[2] = uid_resp[3];
1847 uid_resp_len = 3;
1848 }
1849
1850 if(uid_ptr && anticollision) {
1851 memcpy(uid_ptr + (cascade_level*3), uid_resp, uid_resp_len);
1852 }
1853
1854 if(p_hi14a_card) {
1855 memcpy(p_hi14a_card->uid + (cascade_level*3), uid_resp, uid_resp_len);
1856 p_hi14a_card->uidlen += uid_resp_len;
1857 }
1858 }
1859
1860 if(p_hi14a_card) {
1861 p_hi14a_card->sak = sak;
1862 }
1863
1864 // PICC compilant with iso14443a-4 ---> (SAK & 0x20 != 0)
1865 if( (sak & 0x20) == 0) return 2;
1866
1867 if (!no_rats) {
1868 // Request for answer to select
1869 AppendCrc14443a(rats, 2);
1870 ReaderTransmit(rats, sizeof(rats), NULL);
1871
1872 if (!(len = ReaderReceive(resp, resp_par))) {
1873 return 0;
1874 }
1875
1876 if(p_hi14a_card) {
1877 memcpy(p_hi14a_card->ats, resp, len);
1878 p_hi14a_card->ats_len = len;
1879 }
1880
1881 // reset the PCB block number
1882 iso14_pcb_blocknum = 0;
1883
1884 // set default timeout and delay next transfer based on ATS
1885 iso14a_set_ATS_times(resp);
1886
1887 }
1888 return 1;
1889 }
1890
1891
1892 void iso14443a_setup(uint8_t fpga_minor_mode) {
1893 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
1894 // Set up the synchronous serial port
1895 FpgaSetupSsc(FPGA_MAJOR_MODE_HF_ISO14443A);
1896 // connect Demodulated Signal to ADC:
1897 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
1898
1899 // Signal field is on with the appropriate LED
1900 if (fpga_minor_mode == FPGA_HF_ISO14443A_READER_MOD
1901 || fpga_minor_mode == FPGA_HF_ISO14443A_READER_LISTEN) {
1902 LED_D_ON();
1903 } else {
1904 LED_D_OFF();
1905 }
1906 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | fpga_minor_mode);
1907
1908 // Start the timer
1909 StartCountSspClk();
1910
1911 DemodReset();
1912 UartReset();
1913 NextTransferTime = 2*DELAY_ARM2AIR_AS_READER;
1914 iso14a_set_timeout(1060); // 10ms default
1915 }
1916
1917 /* Peter Fillmore 2015
1918 Added card id field to the function
1919 info from ISO14443A standard
1920 b1 = Block Number
1921 b2 = RFU (always 1)
1922 b3 = depends on block
1923 b4 = Card ID following if set to 1
1924 b5 = depends on block type
1925 b6 = depends on block type
1926 b7,b8 = block type.
1927 Coding of I-BLOCK:
1928 b8 b7 b6 b5 b4 b3 b2 b1
1929 0 0 0 x x x 1 x
1930 b5 = chaining bit
1931 Coding of R-block:
1932 b8 b7 b6 b5 b4 b3 b2 b1
1933 1 0 1 x x 0 1 x
1934 b5 = ACK/NACK
1935 Coding of S-block:
1936 b8 b7 b6 b5 b4 b3 b2 b1
1937 1 1 x x x 0 1 0
1938 b5,b6 = 00 - DESELECT
1939 11 - WTX
1940 */
1941 int iso14_apdu(uint8_t *cmd, uint16_t cmd_len, void *data, uint8_t *res) {
1942 uint8_t parity[MAX_PARITY_SIZE];
1943 uint8_t real_cmd[cmd_len + 4];
1944
1945 if (cmd_len) {
1946 // ISO 14443 APDU frame: PCB [CID] [NAD] APDU CRC PCB=0x02
1947 real_cmd[0] = 0x02; // bnr,nad,cid,chn=0; i-block(0x00)
1948 // put block number into the PCB
1949 real_cmd[0] |= iso14_pcb_blocknum;
1950 memcpy(real_cmd + 1, cmd, cmd_len);
1951 } else {
1952 // R-block. ACK
1953 real_cmd[0] = 0xA2; // r-block + ACK
1954 real_cmd[0] |= iso14_pcb_blocknum;
1955 }
1956 AppendCrc14443a(real_cmd, cmd_len + 1);
1957
1958 ReaderTransmit(real_cmd, cmd_len + 3, NULL);
1959
1960 size_t len = ReaderReceive(data, parity);
1961 uint8_t *data_bytes = (uint8_t *) data;
1962
1963 if (!len) {
1964 return 0; //DATA LINK ERROR
1965 } else{
1966 // S-Block WTX
1967 while(len && ((data_bytes[0] & 0xF2) == 0xF2)) {
1968 uint32_t save_iso14a_timeout = iso14a_get_timeout();
1969 // temporarily increase timeout
1970 iso14a_set_timeout(MAX((data_bytes[1] & 0x3f) * save_iso14a_timeout, MAX_ISO14A_TIMEOUT));
1971 // Transmit WTX back
1972 // byte1 - WTXM [1..59]. command FWT=FWT*WTXM
1973 data_bytes[1] = data_bytes[1] & 0x3f; // 2 high bits mandatory set to 0b
1974 // now need to fix CRC.
1975 AppendCrc14443a(data_bytes, len - 2);
1976 // transmit S-Block
1977 ReaderTransmit(data_bytes, len, NULL);
1978 // retrieve the result again (with increased timeout)
1979 len = ReaderReceive(data, parity);
1980 data_bytes = data;
1981 // restore timeout
1982 iso14a_set_timeout(save_iso14a_timeout);
1983 }
1984
1985 // if we received an I- or R(ACK)-Block with a block number equal to the
1986 // current block number, toggle the current block number
1987 if (len >= 3 // PCB+CRC = 3 bytes
1988 && ((data_bytes[0] & 0xC0) == 0 // I-Block
1989 || (data_bytes[0] & 0xD0) == 0x80) // R-Block with ACK bit set to 0
1990 && (data_bytes[0] & 0x01) == iso14_pcb_blocknum) // equal block numbers
1991 {
1992 iso14_pcb_blocknum ^= 1;
1993 }
1994
1995 // if we received I-block with chaining we need to send ACK and receive another block of data
1996 if (res)
1997 *res = data_bytes[0];
1998
1999 // crc check
2000 if (len >= 3 && !CheckCrc14443(CRC_14443_A, data_bytes, len)) {
2001 return -1;
2002 }
2003
2004 }
2005
2006 if (len) {
2007 // cut frame byte
2008 len -= 1;
2009 // memmove(data_bytes, data_bytes + 1, len);
2010 for (int i = 0; i < len; i++)
2011 data_bytes[i] = data_bytes[i + 1];
2012 }
2013
2014 return len;
2015 }
2016
2017
2018 //-----------------------------------------------------------------------------
2019 // Read an ISO 14443a tag. Send out commands and store answers.
2020 //
2021 //-----------------------------------------------------------------------------
2022 void ReaderIso14443a(UsbCommand *c)
2023 {
2024 iso14a_command_t param = c->arg[0];
2025 uint8_t *cmd = c->d.asBytes;
2026 size_t len = c->arg[1] & 0xffff;
2027 size_t lenbits = c->arg[1] >> 16;
2028 uint32_t timeout = c->arg[2];
2029 uint32_t arg0 = 0;
2030 byte_t buf[USB_CMD_DATA_SIZE] = {0};
2031 uint8_t par[MAX_PARITY_SIZE];
2032 bool cantSELECT = false;
2033
2034 set_tracing(true);
2035
2036 if(param & ISO14A_CLEAR_TRACE) {
2037 clear_trace();
2038 }
2039
2040 if(param & ISO14A_REQUEST_TRIGGER) {
2041 iso14a_set_trigger(true);
2042 }
2043
2044 if(param & ISO14A_CONNECT) {
2045 LED_A_ON();
2046 iso14443a_setup(FPGA_HF_ISO14443A_READER_LISTEN);
2047 if(!(param & ISO14A_NO_SELECT)) {
2048 iso14a_card_select_t *card = (iso14a_card_select_t*)buf;
2049 arg0 = iso14443a_select_card(NULL, card, NULL, true, 0, param & ISO14A_NO_RATS);
2050
2051 // if we cant select then we cant send data
2052 if (arg0 != 1 && arg0 != 2) {
2053 // 1 - all is OK with ATS, 2 - without ATS
2054 cantSELECT = true;
2055 }
2056 FpgaDisableTracing();
2057 LED_B_ON();
2058 cmd_send(CMD_ACK,arg0,card->uidlen,0,buf,sizeof(iso14a_card_select_t));
2059 LED_B_OFF();
2060 }
2061 }
2062
2063 if(param & ISO14A_SET_TIMEOUT) {
2064 iso14a_set_timeout(timeout);
2065 }
2066
2067 if(param & ISO14A_APDU && !cantSELECT) {
2068 uint8_t res;
2069 arg0 = iso14_apdu(cmd, len, buf, &res);
2070 FpgaDisableTracing();
2071 LED_B_ON();
2072 cmd_send(CMD_ACK, arg0, res, 0, buf, sizeof(buf));
2073 LED_B_OFF();
2074 }
2075
2076 if(param & ISO14A_RAW && !cantSELECT) {
2077 if(param & ISO14A_APPEND_CRC) {
2078 if(param & ISO14A_TOPAZMODE) {
2079 AppendCrc14443b(cmd,len);
2080 } else {
2081 AppendCrc14443a(cmd,len);
2082 }
2083 len += 2;
2084 if (lenbits) lenbits += 16;
2085 }
2086 if(lenbits>0) { // want to send a specific number of bits (e.g. short commands)
2087 if(param & ISO14A_TOPAZMODE) {
2088 int bits_to_send = lenbits;
2089 uint16_t i = 0;
2090 ReaderTransmitBitsPar(&cmd[i++], MIN(bits_to_send, 7), NULL, NULL); // first byte is always short (7bits) and no parity
2091 bits_to_send -= 7;
2092 while (bits_to_send > 0) {
2093 ReaderTransmitBitsPar(&cmd[i++], MIN(bits_to_send, 8), NULL, NULL); // following bytes are 8 bit and no parity
2094 bits_to_send -= 8;
2095 }
2096 } else {
2097 GetParity(cmd, lenbits/8, par);
2098 ReaderTransmitBitsPar(cmd, lenbits, par, NULL); // bytes are 8 bit with odd parity
2099 }
2100 } else { // want to send complete bytes only
2101 if(param & ISO14A_TOPAZMODE) {
2102 uint16_t i = 0;
2103 ReaderTransmitBitsPar(&cmd[i++], 7, NULL, NULL); // first byte: 7 bits, no paritiy
2104 while (i < len) {
2105 ReaderTransmitBitsPar(&cmd[i++], 8, NULL, NULL); // following bytes: 8 bits, no paritiy
2106 }
2107 } else {
2108 ReaderTransmit(cmd,len, NULL); // 8 bits, odd parity
2109 }
2110 }
2111 arg0 = ReaderReceive(buf, par);
2112 FpgaDisableTracing();
2113
2114 LED_B_ON();
2115 cmd_send(CMD_ACK,arg0,0,0,buf,sizeof(buf));
2116 LED_B_OFF();
2117 }
2118
2119 if(param & ISO14A_REQUEST_TRIGGER) {
2120 iso14a_set_trigger(false);
2121 }
2122
2123 if(param & ISO14A_NO_DISCONNECT) {
2124 return;
2125 }
2126
2127 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
2128 LEDsoff();
2129 }
2130
2131
2132 // Determine the distance between two nonces.
2133 // Assume that the difference is small, but we don't know which is first.
2134 // Therefore try in alternating directions.
2135 static int32_t dist_nt(uint32_t nt1, uint32_t nt2) {
2136
2137 uint16_t i;
2138 uint32_t nttmp1, nttmp2;
2139
2140 if (nt1 == nt2) return 0;
2141
2142 nttmp1 = nt1;
2143 nttmp2 = nt2;
2144
2145 for (i = 1; i < 32768; i++) {
2146 nttmp1 = prng_successor(nttmp1, 1);
2147 if (nttmp1 == nt2) return i;
2148 nttmp2 = prng_successor(nttmp2, 1);
2149 if (nttmp2 == nt1) return -i;
2150 }
2151
2152 return(-99999); // either nt1 or nt2 are invalid nonces
2153 }
2154
2155
2156 //-----------------------------------------------------------------------------
2157 // Recover several bits of the cypher stream. This implements (first stages of)
2158 // the algorithm described in "The Dark Side of Security by Obscurity and
2159 // Cloning MiFare Classic Rail and Building Passes, Anywhere, Anytime"
2160 // (article by Nicolas T. Courtois, 2009)
2161 //-----------------------------------------------------------------------------
2162 void ReaderMifare(bool first_try)
2163 {
2164 // Mifare AUTH
2165 uint8_t mf_auth[] = { 0x60,0x00,0xf5,0x7b };
2166 uint8_t mf_nr_ar[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 };
2167 static uint8_t mf_nr_ar3;
2168
2169 uint8_t receivedAnswer[MAX_MIFARE_FRAME_SIZE];
2170 uint8_t receivedAnswerPar[MAX_MIFARE_PARITY_SIZE];
2171
2172 iso14443a_setup(FPGA_HF_ISO14443A_READER_MOD);
2173
2174 // free eventually allocated BigBuf memory. We want all for tracing.
2175 BigBuf_free();
2176
2177 clear_trace();
2178 set_tracing(true);
2179
2180 uint8_t nt_diff = 0;
2181 uint8_t par[1] = {0}; // maximum 8 Bytes to be sent here, 1 byte parity is therefore enough
2182 static uint8_t par_low = 0;
2183 bool led_on = true;
2184 uint8_t uid[10] ={0};
2185 uint32_t cuid;
2186
2187 uint32_t nt = 0;
2188 uint32_t previous_nt = 0;
2189 static uint32_t nt_attacked = 0;
2190 uint8_t par_list[8] = {0x00};
2191 uint8_t ks_list[8] = {0x00};
2192
2193 #define PRNG_SEQUENCE_LENGTH (1 << 16);
2194 uint32_t sync_time = GetCountSspClk() & 0xfffffff8;
2195 static int32_t sync_cycles;
2196 int catch_up_cycles = 0;
2197 int last_catch_up = 0;
2198 uint16_t elapsed_prng_sequences;
2199 uint16_t consecutive_resyncs = 0;
2200 int isOK = 0;
2201
2202 if (first_try) {
2203 mf_nr_ar3 = 0;
2204 par[0] = par_low = 0;
2205 sync_cycles = PRNG_SEQUENCE_LENGTH; // theory: Mifare Classic's random generator repeats every 2^16 cycles (and so do the tag nonces).
2206 nt_attacked = 0;
2207 }
2208 else {
2209 // we were unsuccessful on a previous call. Try another READER nonce (first 3 parity bits remain the same)
2210 mf_nr_ar3++;
2211 mf_nr_ar[3] = mf_nr_ar3;
2212 par[0] = par_low;
2213 }
2214
2215 LED_A_ON();
2216 LED_B_OFF();
2217 LED_C_OFF();
2218
2219
2220 #define MAX_UNEXPECTED_RANDOM 4 // maximum number of unexpected (i.e. real) random numbers when trying to sync. Then give up.
2221 #define MAX_SYNC_TRIES 32
2222 #define SYNC_TIME_BUFFER 16 // if there is only SYNC_TIME_BUFFER left before next planned sync, wait for next PRNG cycle
2223 #define NUM_DEBUG_INFOS 8 // per strategy
2224 #define MAX_STRATEGY 3
2225 uint16_t unexpected_random = 0;
2226 uint16_t sync_tries = 0;
2227 int16_t debug_info_nr = -1;
2228 uint16_t strategy = 0;
2229 int32_t debug_info[MAX_STRATEGY][NUM_DEBUG_INFOS];
2230 uint32_t select_time;
2231 uint32_t halt_time;
2232
2233 for(uint16_t i = 0; true; i++) {
2234
2235 LED_C_ON();
2236 WDT_HIT();
2237
2238 // Test if the action was cancelled
2239 if(BUTTON_PRESS()) {
2240 isOK = -1;
2241 break;
2242 }
2243
2244 if (strategy == 2) {
2245 // test with additional hlt command
2246 halt_time = 0;
2247 int len = mifare_sendcmd_short(NULL, false, 0x50, 0x00, receivedAnswer, receivedAnswerPar, &halt_time);
2248 if (len && MF_DBGLEVEL >= 3) {
2249 Dbprintf("Unexpected response of %d bytes to hlt command (additional debugging).", len);
2250 }
2251 }
2252
2253 if (strategy == 3) {
2254 // test with FPGA power off/on
2255 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
2256 SpinDelay(200);
2257 iso14443a_setup(FPGA_HF_ISO14443A_READER_MOD);
2258 SpinDelay(100);
2259 }
2260
2261 if(!iso14443a_select_card(uid, NULL, &cuid, true, 0, true)) {
2262 if (MF_DBGLEVEL >= 1) Dbprintf("Mifare: Can't select card");
2263 continue;
2264 }
2265 select_time = GetCountSspClk();
2266
2267 elapsed_prng_sequences = 1;
2268 if (debug_info_nr == -1) {
2269 sync_time = (sync_time & 0xfffffff8) + sync_cycles + catch_up_cycles;
2270 catch_up_cycles = 0;
2271
2272 // if we missed the sync time already or are about to miss it, advance to the next nonce repeat
2273 while(sync_time < GetCountSspClk() + SYNC_TIME_BUFFER) {
2274 elapsed_prng_sequences++;
2275 sync_time = (sync_time & 0xfffffff8) + sync_cycles;
2276 }
2277
2278 // Transmit MIFARE_CLASSIC_AUTH at synctime. Should result in returning the same tag nonce (== nt_attacked)
2279 ReaderTransmit(mf_auth, sizeof(mf_auth), &sync_time);
2280 } else {
2281 // collect some information on tag nonces for debugging:
2282 #define DEBUG_FIXED_SYNC_CYCLES PRNG_SEQUENCE_LENGTH
2283 if (strategy == 0) {
2284 // nonce distances at fixed time after card select:
2285 sync_time = select_time + DEBUG_FIXED_SYNC_CYCLES;
2286 } else if (strategy == 1) {
2287 // nonce distances at fixed time between authentications:
2288 sync_time = sync_time + DEBUG_FIXED_SYNC_CYCLES;
2289 } else if (strategy == 2) {
2290 // nonce distances at fixed time after halt:
2291 sync_time = halt_time + DEBUG_FIXED_SYNC_CYCLES;
2292 } else {
2293 // nonce_distances at fixed time after power on
2294 sync_time = DEBUG_FIXED_SYNC_CYCLES;
2295 }
2296 ReaderTransmit(mf_auth, sizeof(mf_auth), &sync_time);
2297 }
2298
2299 // Receive the (4 Byte) "random" nonce
2300 if (!ReaderReceive(receivedAnswer, receivedAnswerPar)) {
2301 if (MF_DBGLEVEL >= 1) Dbprintf("Mifare: Couldn't receive tag nonce");
2302 continue;
2303 }
2304
2305 previous_nt = nt;
2306 nt = bytes_to_num(receivedAnswer, 4);
2307
2308 // Transmit reader nonce with fake par
2309 ReaderTransmitPar(mf_nr_ar, sizeof(mf_nr_ar), par, NULL);
2310
2311 if (first_try && previous_nt && !nt_attacked) { // we didn't calibrate our clock yet
2312 int nt_distance = dist_nt(previous_nt, nt);
2313 if (nt_distance == 0) {
2314 nt_attacked = nt;
2315 } else {
2316 if (nt_distance == -99999) { // invalid nonce received
2317 unexpected_random++;
2318 if (unexpected_random > MAX_UNEXPECTED_RANDOM) {
2319 isOK = -3; // Card has an unpredictable PRNG. Give up
2320 break;
2321 } else {
2322 continue; // continue trying...
2323 }
2324 }
2325 if (++sync_tries > MAX_SYNC_TRIES) {
2326 if (strategy > MAX_STRATEGY || MF_DBGLEVEL < 3) {
2327 isOK = -4; // Card's PRNG runs at an unexpected frequency or resets unexpectedly
2328 break;
2329 } else { // continue for a while, just to collect some debug info
2330 debug_info[strategy][debug_info_nr] = nt_distance;
2331 debug_info_nr++;
2332 if (debug_info_nr == NUM_DEBUG_INFOS) {
2333 strategy++;
2334 debug_info_nr = 0;
2335 }
2336 continue;
2337 }
2338 }
2339 sync_cycles = (sync_cycles - nt_distance/elapsed_prng_sequences);
2340 if (sync_cycles <= 0) {
2341 sync_cycles += PRNG_SEQUENCE_LENGTH;
2342 }
2343 if (MF_DBGLEVEL >= 3) {
2344 Dbprintf("calibrating in cycle %d. nt_distance=%d, elapsed_prng_sequences=%d, new sync_cycles: %d\n", i, nt_distance, elapsed_prng_sequences, sync_cycles);
2345 }
2346 continue;
2347 }
2348 }
2349
2350 if ((nt != nt_attacked) && nt_attacked) { // we somehow lost sync. Try to catch up again...
2351 catch_up_cycles = -dist_nt(nt_attacked, nt);
2352 if (catch_up_cycles == 99999) { // invalid nonce received. Don't resync on that one.
2353 catch_up_cycles = 0;
2354 continue;
2355 }
2356 catch_up_cycles /= elapsed_prng_sequences;
2357 if (catch_up_cycles == last_catch_up) {
2358 consecutive_resyncs++;
2359 }
2360 else {
2361 last_catch_up = catch_up_cycles;
2362 consecutive_resyncs = 0;
2363 }
2364 if (consecutive_resyncs < 3) {
2365 if (MF_DBGLEVEL >= 3) Dbprintf("Lost sync in cycle %d. nt_distance=%d. Consecutive Resyncs = %d. Trying one time catch up...\n", i, -catch_up_cycles, consecutive_resyncs);
2366 }
2367 else {
2368 sync_cycles = sync_cycles + catch_up_cycles;
2369 if (MF_DBGLEVEL >= 3) Dbprintf("Lost sync in cycle %d for the fourth time consecutively (nt_distance = %d). Adjusting sync_cycles to %d.\n", i, -catch_up_cycles, sync_cycles);
2370 last_catch_up = 0;
2371 catch_up_cycles = 0;
2372 consecutive_resyncs = 0;
2373 }
2374 continue;
2375 }
2376
2377 consecutive_resyncs = 0;
2378
2379 // Receive answer. This will be a 4 Bit NACK when the 8 parity bits are OK after decoding
2380 if (ReaderReceive(receivedAnswer, receivedAnswerPar)) {
2381 catch_up_cycles = 8; // the PRNG is delayed by 8 cycles due to the NAC (4Bits = 0x05 encrypted) transfer
2382
2383 if (nt_diff == 0) {
2384 par_low = par[0] & 0xE0; // there is no need to check all parities for other nt_diff. Parity Bits for mf_nr_ar[0..2] won't change
2385 }
2386
2387 led_on = !led_on;
2388 if(led_on) LED_B_ON(); else LED_B_OFF();
2389
2390 par_list[nt_diff] = SwapBits(par[0], 8);
2391 ks_list[nt_diff] = receivedAnswer[0] ^ 0x05;
2392
2393 // Test if the information is complete
2394 if (nt_diff == 0x07) {
2395 isOK = 1;
2396 break;
2397 }
2398
2399 nt_diff = (nt_diff + 1) & 0x07;
2400 mf_nr_ar[3] = (mf_nr_ar[3] & 0x1F) | (nt_diff << 5);
2401 par[0] = par_low;
2402 } else {
2403 if (nt_diff == 0 && first_try)
2404 {
2405 par[0]++;
2406 if (par[0] == 0x00) { // tried all 256 possible parities without success. Card doesn't send NACK.
2407 isOK = -2;
2408 break;
2409 }
2410 } else {
2411 par[0] = ((par[0] & 0x1F) + 1) | par_low;
2412 }
2413 }
2414 }
2415
2416
2417 mf_nr_ar[3] &= 0x1F;
2418
2419 if (isOK == -4) {
2420 if (MF_DBGLEVEL >= 3) {
2421 for (uint16_t i = 0; i <= MAX_STRATEGY; i++) {
2422 for(uint16_t j = 0; j < NUM_DEBUG_INFOS; j++) {
2423 Dbprintf("collected debug info[%d][%d] = %d", i, j, debug_info[i][j]);
2424 }
2425 }
2426 }
2427 }
2428
2429 FpgaDisableTracing();
2430
2431 uint8_t buf[32];
2432 memcpy(buf + 0, uid, 4);
2433 num_to_bytes(nt, 4, buf + 4);
2434 memcpy(buf + 8, par_list, 8);
2435 memcpy(buf + 16, ks_list, 8);
2436 memcpy(buf + 24, mf_nr_ar, 8);
2437
2438 cmd_send(CMD_ACK, isOK, 0, 0, buf, 32);
2439
2440 // Thats it...
2441 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
2442 LEDsoff();
2443
2444 set_tracing(false);
2445 }
2446
2447
2448 //-----------------------------------------------------------------------------
2449 // MIFARE sniffer.
2450 //
2451 //-----------------------------------------------------------------------------
2452 void RAMFUNC SniffMifare(uint8_t param) {
2453 // param:
2454 // bit 0 - trigger from first card answer
2455 // bit 1 - trigger from first reader 7-bit request
2456
2457 // C(red) A(yellow) B(green)
2458 LEDsoff();
2459 // init trace buffer
2460 clear_trace();
2461 set_tracing(true);
2462
2463 // The command (reader -> tag) that we're receiving.
2464 // The length of a received command will in most cases be no more than 18 bytes.
2465 // So 32 should be enough!
2466 uint8_t receivedCmd[MAX_MIFARE_FRAME_SIZE];
2467 uint8_t receivedCmdPar[MAX_MIFARE_PARITY_SIZE];
2468 // The response (tag -> reader) that we're receiving.
2469 uint8_t receivedResponse[MAX_MIFARE_FRAME_SIZE];
2470 uint8_t receivedResponsePar[MAX_MIFARE_PARITY_SIZE];
2471
2472 iso14443a_setup(FPGA_HF_ISO14443A_SNIFFER);
2473
2474 // free eventually allocated BigBuf memory
2475 BigBuf_free();
2476 // allocate the DMA buffer, used to stream samples from the FPGA
2477 uint8_t *dmaBuf = BigBuf_malloc(DMA_BUFFER_SIZE);
2478 uint8_t *data = dmaBuf;
2479 uint8_t previous_data = 0;
2480 int maxDataLen = 0;
2481 int dataLen = 0;
2482 bool ReaderIsActive = false;
2483 bool TagIsActive = false;
2484
2485 // Set up the demodulator for tag -> reader responses.
2486 DemodInit(receivedResponse, receivedResponsePar);
2487
2488 // Set up the demodulator for the reader -> tag commands
2489 UartInit(receivedCmd, receivedCmdPar);
2490
2491 // Setup for the DMA.
2492 FpgaSetupSscDma((uint8_t *)dmaBuf, DMA_BUFFER_SIZE); // set transfer address and number of bytes. Start transfer.
2493
2494 LED_D_OFF();
2495
2496 // init sniffer
2497 MfSniffInit();
2498
2499 // And now we loop, receiving samples.
2500 for(uint32_t sniffCounter = 0; true; ) {
2501
2502 if(BUTTON_PRESS()) {
2503 DbpString("Canceled by button.");
2504 break;
2505 }
2506
2507 LED_A_ON();
2508 WDT_HIT();
2509
2510 if ((sniffCounter & 0x0000FFFF) == 0) { // from time to time
2511 // check if a transaction is completed (timeout after 2000ms).
2512 // if yes, stop the DMA transfer and send what we have so far to the client
2513 if (MfSniffSend(2000)) {
2514 // Reset everything - we missed some sniffed data anyway while the DMA was stopped
2515 sniffCounter = 0;
2516 data = dmaBuf;
2517 maxDataLen = 0;
2518 ReaderIsActive = false;
2519 TagIsActive = false;
2520 FpgaSetupSscDma((uint8_t *)dmaBuf, DMA_BUFFER_SIZE); // set transfer address and number of bytes. Start transfer.
2521 }
2522 }
2523
2524 int register readBufDataP = data - dmaBuf; // number of bytes we have processed so far
2525 int register dmaBufDataP = DMA_BUFFER_SIZE - AT91C_BASE_PDC_SSC->PDC_RCR; // number of bytes already transferred
2526 if (readBufDataP <= dmaBufDataP){ // we are processing the same block of data which is currently being transferred
2527 dataLen = dmaBufDataP - readBufDataP; // number of bytes still to be processed
2528 } else {
2529 dataLen = DMA_BUFFER_SIZE - readBufDataP + dmaBufDataP; // number of bytes still to be processed
2530 }
2531 // test for length of buffer
2532 if(dataLen > maxDataLen) { // we are more behind than ever...
2533 maxDataLen = dataLen;
2534 if(dataLen > (9 * DMA_BUFFER_SIZE / 10)) {
2535 Dbprintf("blew circular buffer! dataLen=0x%x", dataLen);
2536 break;
2537 }
2538 }
2539 if(dataLen < 1) continue;
2540
2541 // primary buffer was stopped ( <-- we lost data!
2542 if (!AT91C_BASE_PDC_SSC->PDC_RCR) {
2543 AT91C_BASE_PDC_SSC->PDC_RPR = (uint32_t) dmaBuf;
2544 AT91C_BASE_PDC_SSC->PDC_RCR = DMA_BUFFER_SIZE;
2545 Dbprintf("RxEmpty ERROR!!! data length:%d", dataLen); // temporary
2546 }
2547 // secondary buffer sets as primary, secondary buffer was stopped
2548 if (!AT91C_BASE_PDC_SSC->PDC_RNCR) {
2549 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) dmaBuf;
2550 AT91C_BASE_PDC_SSC->PDC_RNCR = DMA_BUFFER_SIZE;
2551 }
2552
2553 LED_A_OFF();
2554
2555 if (sniffCounter & 0x01) {
2556
2557 if(!TagIsActive) { // no need to try decoding tag data if the reader is sending
2558 uint8_t readerdata = (previous_data & 0xF0) | (*data >> 4);
2559 if(MillerDecoding(readerdata, (sniffCounter-1)*4)) {
2560 LED_B_ON();
2561 LED_C_OFF();
2562
2563 if (MfSniffLogic(receivedCmd, Uart.len, Uart.parity, Uart.bitCount, true)) break;
2564
2565 /* And ready to receive another command. */
2566 UartInit(receivedCmd, receivedCmdPar);
2567
2568 /* And also reset the demod code */
2569 DemodReset();
2570 }
2571 ReaderIsActive = (Uart.state != STATE_UNSYNCD);
2572 }
2573
2574 if(!ReaderIsActive) { // no need to try decoding tag data if the reader is sending
2575 uint8_t tagdata = (previous_data << 4) | (*data & 0x0F);
2576 if(ManchesterDecoding(tagdata, 0, (sniffCounter-1)*4)) {
2577 LED_B_OFF();
2578 LED_C_ON();
2579
2580 if (MfSniffLogic(receivedResponse, Demod.len, Demod.parity, Demod.bitCount, false)) break;
2581
2582 // And ready to receive another response.
2583 DemodReset();
2584 // And reset the Miller decoder including its (now outdated) input buffer
2585 UartInit(receivedCmd, receivedCmdPar);
2586 }
2587 TagIsActive = (Demod.state != DEMOD_UNSYNCD);
2588 }
2589 }
2590
2591 previous_data = *data;
2592 sniffCounter++;
2593 data++;
2594 if(data == dmaBuf + DMA_BUFFER_SIZE) {
2595 data = dmaBuf;
2596 }
2597
2598 } // main cycle
2599
2600 DbpString("COMMAND FINISHED.");
2601
2602 FpgaDisableSscDma();
2603 FpgaDisableTracing();
2604 MfSniffEnd();
2605
2606 Dbprintf("maxDataLen=%x, Uart.state=%x, Uart.len=%x", maxDataLen, Uart.state, Uart.len);
2607 LEDsoff();
2608 }
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