git.zerfleddert.de Git - proxmark3-svn/blob - fpga/hi_read_rx_xcorr.v

   1 //-----------------------------------------------------------------------------
   2 //
   3 // Jonathan Westhues, April 2006
   4 //-----------------------------------------------------------------------------
   5
   6 module hi_read_rx_xcorr(
   7     pck0, ck_1356meg, ck_1356megb,
   8     pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
   9     adc_d, adc_clk,
  10     ssp_frame, ssp_din, ssp_dout, ssp_clk,
  11     cross_hi, cross_lo,
  12     dbg,
  13     xcorr_is_848, snoop
  14 );
  15     input pck0, ck_1356meg, ck_1356megb;
  16     output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
  17     input [7:0] adc_d;
  18     output adc_clk;
  19     input ssp_dout;
  20     output ssp_frame, ssp_din, ssp_clk;
  21     input cross_hi, cross_lo;
  22     output dbg;
  23     input xcorr_is_848, snoop;
  24
  25 // Carrier is steady on through this, unless we're snooping.
  26 assign pwr_hi = ck_1356megb & (~snoop);
  27 assign pwr_oe1 = 1'b0;
  28 assign pwr_oe3 = 1'b0;
  29 assign pwr_oe4 = 1'b0;
  30
  31 (* clock_signal = "yes" *) reg fc_div_2;
  32 always @(negedge ck_1356megb)
  33     fc_div_2 <= fc_div_2 + 1;
  34
  35 (* clock_signal = "yes" *) reg adc_clk;
  36 always @(xcorr_is_848, ck_1356megb, fc_div_2)
  37 if (xcorr_is_848)
  38         // The subcarrier frequency is fc/16; we will sample at fc, so that
  39         // means the subcarrier is 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 ...
  40         adc_clk <= ck_1356megb;
  41 else
  42     // The subcarrier frequency is fc/32; we will sample at fc/2, and
  43     // the subcarrier will look identical.
  44     adc_clk <= fc_div_2;
  45
  46
  47 // When we're a reader, we just need to do the BPSK demod; but when we're an
  48 // eavesdropper, we also need to pick out the commands sent by the reader,
  49 // using AM. Do this the same way that we do it for the simulated tag.
  50 reg after_hysteresis, after_hysteresis_prev, after_hysteresis_prev_prev;
  51 reg [11:0] has_been_low_for;
  52 always @(negedge adc_clk)
  53 begin
  54     if(& adc_d[7:0]) after_hysteresis <= 1'b1;
  55     else if(~(| adc_d[7:0])) after_hysteresis <= 1'b0;
  56
  57     if(after_hysteresis)
  58     begin
  59         has_been_low_for <= 7'b0;
  60     end
  61     else
  62     begin
  63         if(has_been_low_for == 12'd4095)
  64         begin
  65             has_been_low_for <= 12'd0;
  66             after_hysteresis <= 1'b1;
  67         end
  68         else
  69             has_been_low_for <= has_been_low_for + 1;
  70     end
  71 end
  72
  73 // Let us report a correlation every 4 subcarrier cycles, or 4*16 samples,
  74 // so we need a 6-bit counter.
  75 reg [5:0] corr_i_cnt;
  76 // And a couple of registers in which to accumulate the correlations.
  77 // we would add at most 32 times adc_d, the result can be held in 13 bits.
  78 // Need one additional bit because it can be negative as well
  79 reg signed [13:0] corr_i_accum;
  80 reg signed [13:0] corr_q_accum;
  81 reg signed [7:0] corr_i_out;
  82 reg signed [7:0] corr_q_out;
  83 // clock and frame signal for communication to ARM
  84 reg ssp_clk;
  85 reg ssp_frame;
  86
  87
  88
  89 // ADC data appears on the rising edge, so sample it on the falling edge
  90 always @(negedge adc_clk)
  91 begin
  92     corr_i_cnt <= corr_i_cnt + 1;
  93
  94     // These are the correlators: we correlate against in-phase and quadrature
  95     // versions of our reference signal, and keep the (signed) result to
  96     // send out later over the SSP.
  97     if(corr_i_cnt == 7'd0)
  98     begin
  99         if(snoop)
 100         begin
 101                         // 7 most significant bits of tag signal (signed), 1 bit reader signal:
 102             corr_i_out <= {corr_i_accum[13:7], after_hysteresis_prev_prev};
 103             corr_q_out <= {corr_q_accum[13:7], after_hysteresis_prev};
 104                         after_hysteresis_prev_prev <= after_hysteresis;
 105         end
 106         else
 107         begin
 108             // 8 most significant bits of tag signal
 109             corr_i_out <= corr_i_accum[13:6];
 110             corr_q_out <= corr_q_accum[13:6];
 111         end
 112
 113         corr_i_accum <= adc_d;
 114         corr_q_accum <= adc_d;
 115     end
 116     else
 117     begin
 118         if(corr_i_cnt[3])
 119             corr_i_accum <= corr_i_accum - adc_d;
 120         else
 121             corr_i_accum <= corr_i_accum + adc_d;
 122
 123         if(corr_i_cnt[3] == corr_i_cnt[2])                      // phase shifted by pi/2
 124             corr_q_accum <= corr_q_accum + adc_d;
 125         else
 126             corr_q_accum <= corr_q_accum - adc_d;
 127
 128     end
 129
 130     // The logic in hi_simulate.v reports 4 samples per bit. We report two
 131     // (I, Q) pairs per bit, so we should do 2 samples per pair.
 132     if(corr_i_cnt == 6'd31)
 133         after_hysteresis_prev <= after_hysteresis;
 134
 135     // Then the result from last time is serialized and send out to the ARM.
 136     // We get one report each cycle, and each report is 16 bits, so the
 137     // ssp_clk should be the adc_clk divided by 64/16 = 4.
 138
 139     if(corr_i_cnt[1:0] == 2'b10)
 140         ssp_clk <= 1'b0;
 141
 142     if(corr_i_cnt[1:0] == 2'b00)
 143     begin
 144         ssp_clk <= 1'b1;
 145         // Don't shift if we just loaded new data, obviously.
 146         if(corr_i_cnt != 7'd0)
 147         begin
 148             corr_i_out[7:0] <= {corr_i_out[6:0], corr_q_out[7]};
 149             corr_q_out[7:1] <= corr_q_out[6:0];
 150         end
 151     end
 152
 153         // set ssp_frame signal for corr_i_cnt = 0..3 and corr_i_cnt = 32..35
 154         // (send two frames with 8 Bits each)
 155     if(corr_i_cnt[5:2] == 4'b0000 || corr_i_cnt[5:2] == 4'b1000)
 156         ssp_frame = 1'b1;
 157     else
 158         ssp_frame = 1'b0;
 159
 160 end
 161
 162 assign ssp_din = corr_i_out[7];
 163
 164 assign dbg = corr_i_cnt[3];
 165
 166 // Unused.
 167 assign pwr_lo = 1'b0;
 168 assign pwr_oe2 = 1'b0;
 169
 170 endmodule