git.zerfleddert.de Git - proxmark3-svn/blob - armsrc/fpga.c

   1 //-----------------------------------------------------------------------------
   2 // Routines to load the FPGA image, and then to configure the FPGA's major
   3 // mode once it is configured.
   4 //
   5 // Jonathan Westhues, April 2006
   6 //-----------------------------------------------------------------------------
   7 #include <proxmark3.h>
   8 #include "apps.h"
   9
  10 //-----------------------------------------------------------------------------
  11 // Set up the Serial Peripheral Interface as master
  12 // Used to write the FPGA config word
  13 // May also be used to write to other SPI attached devices like an LCD
  14 //-----------------------------------------------------------------------------
  15 void SetupSpi(int mode)
  16 {
  17         // PA10 -> SPI_NCS2 chip select (LCD)
  18         // PA11 -> SPI_NCS0 chip select (FPGA)
  19         // PA12 -> SPI_MISO Master-In Slave-Out
  20         // PA13 -> SPI_MOSI Master-Out Slave-In
  21         // PA14 -> SPI_SPCK Serial Clock
  22
  23         // Disable PIO control of the following pins, allows use by the SPI peripheral
  24         PIO_DISABLE                      =      (1 << GPIO_NCS0)        |
  25                                                         (1 << GPIO_NCS2)        |
  26                                                         (1 << GPIO_MISO)        |
  27                                                         (1 << GPIO_MOSI)        |
  28                                                         (1 << GPIO_SPCK);
  29
  30         PIO_PERIPHERAL_A_SEL =  (1 << GPIO_NCS0)        |
  31                                                         (1 << GPIO_MISO)        |
  32                                                         (1 << GPIO_MOSI)        |
  33                                                         (1 << GPIO_SPCK);
  34
  35         PIO_PERIPHERAL_B_SEL =  (1 << GPIO_NCS2);
  36
  37         //enable the SPI Peripheral clock
  38         PMC_PERIPHERAL_CLK_ENABLE = (1<<PERIPH_SPI);
  39         // Enable SPI
  40         SPI_CONTROL = SPI_CONTROL_ENABLE;
  41
  42         switch (mode) {
  43                 case SPI_FPGA_MODE:
  44                         SPI_MODE =
  45                                 ( 0 << 24)      |       // Delay between chip selects (take default: 6 MCK periods)
  46                                 (14 << 16)      |       // Peripheral Chip Select (selects FPGA SPI_NCS0 or PA11)
  47                                 ( 0 << 7)       |       // Local Loopback Disabled
  48                                 ( 1 << 4)       |       // Mode Fault Detection disabled
  49                                 ( 0 << 2)       |       // Chip selects connected directly to peripheral
  50                                 ( 0 << 1)       |       // Fixed Peripheral Select
  51                                 ( 1 << 0);              // Master Mode
  52                         SPI_FOR_CHIPSEL_0 =
  53                                 ( 1 << 24)      |       // Delay between Consecutive Transfers (32 MCK periods)
  54                                 ( 1 << 16)      |       // Delay Before SPCK (1 MCK period)
  55                                 ( 6 << 8)       |       // Serial Clock Baud Rate (baudrate = MCK/6 = 24Mhz/6 = 4M baud
  56                                 ( 0 << 4)       |       // Bits per Transfer (8 bits)
  57                                 ( 0 << 3)       |       // Chip Select inactive after transfer
  58                                 ( 1 << 1)       |       // Clock Phase data captured on leading edge, changes on following edge
  59                                 ( 0 << 0);              // Clock Polarity inactive state is logic 0
  60                         break;
  61                 case SPI_LCD_MODE:
  62                         SPI_MODE =
  63                                 ( 0 << 24)      |       // Delay between chip selects (take default: 6 MCK periods)
  64                                 (11 << 16)      |       // Peripheral Chip Select (selects LCD SPI_NCS2 or PA10)
  65                                 ( 0 << 7)       |       // Local Loopback Disabled
  66                                 ( 1 << 4)       |       // Mode Fault Detection disabled
  67                                 ( 0 << 2)       |       // Chip selects connected directly to peripheral
  68                                 ( 0 << 1)       |       // Fixed Peripheral Select
  69                                 ( 1 << 0);              // Master Mode
  70                         SPI_FOR_CHIPSEL_2 =
  71                                 ( 1 << 24)      |       // Delay between Consecutive Transfers (32 MCK periods)
  72                                 ( 1 << 16)      |       // Delay Before SPCK (1 MCK period)
  73                                 ( 6 << 8)       |       // Serial Clock Baud Rate (baudrate = MCK/6 = 24Mhz/6 = 4M baud
  74                                 ( 1 << 4)       |       // Bits per Transfer (9 bits)
  75                                 ( 0 << 3)       |       // Chip Select inactive after transfer
  76                                 ( 1 << 1)       |       // Clock Phase data captured on leading edge, changes on following edge
  77                                 ( 0 << 0);              // Clock Polarity inactive state is logic 0
  78                         break;
  79                 default:                                // Disable SPI
  80                         SPI_CONTROL = SPI_CONTROL_DISABLE;
  81                         break;
  82         }
  83 }
  84
  85 //-----------------------------------------------------------------------------
  86 // Set up the synchronous serial port, with the one set of options that we
  87 // always use when we are talking to the FPGA. Both RX and TX are enabled.
  88 //-----------------------------------------------------------------------------
  89 void FpgaSetupSsc(void)
  90 {
  91         // First configure the GPIOs, and get ourselves a clock.
  92         PIO_PERIPHERAL_A_SEL =  (1 << GPIO_SSC_FRAME)   |
  93                                                         (1 << GPIO_SSC_DIN)             |
  94                                                         (1 << GPIO_SSC_DOUT)    |
  95                                                         (1 << GPIO_SSC_CLK);
  96         PIO_DISABLE = (1 << GPIO_SSC_DOUT);
  97
  98         PMC_PERIPHERAL_CLK_ENABLE = (1 << PERIPH_SSC);
  99
 100         // Now set up the SSC proper, starting from a known state.
 101         SSC_CONTROL = SSC_CONTROL_RESET;
 102
 103         // RX clock comes from TX clock, RX starts when TX starts, data changes
 104         // on RX clock rising edge, sampled on falling edge
 105         SSC_RECEIVE_CLOCK_MODE = SSC_CLOCK_MODE_SELECT(1) | SSC_CLOCK_MODE_START(1);
 106
 107         // 8 bits per transfer, no loopback, MSB first, 1 transfer per sync
 108         // pulse, no output sync, start on positive-going edge of sync
 109         SSC_RECEIVE_FRAME_MODE = SSC_FRAME_MODE_BITS_IN_WORD(8) |
 110                 SSC_FRAME_MODE_MSB_FIRST | SSC_FRAME_MODE_WORDS_PER_TRANSFER(0);
 111
 112         // clock comes from TK pin, no clock output, outputs change on falling
 113         // edge of TK, start on rising edge of TF
 114         SSC_TRANSMIT_CLOCK_MODE = SSC_CLOCK_MODE_SELECT(2) |
 115                 SSC_CLOCK_MODE_START(5);
 116
 117         // tx framing is the same as the rx framing
 118         SSC_TRANSMIT_FRAME_MODE = SSC_RECEIVE_FRAME_MODE;
 119
 120         SSC_CONTROL = SSC_CONTROL_RX_ENABLE | SSC_CONTROL_TX_ENABLE;
 121 }
 122
 123 //-----------------------------------------------------------------------------
 124 // Set up DMA to receive samples from the FPGA. We will use the PDC, with
 125 // a single buffer as a circular buffer (so that we just chain back to
 126 // ourselves, not to another buffer). The stuff to manipulate those buffers
 127 // is in apps.h, because it should be inlined, for speed.
 128 //-----------------------------------------------------------------------------
 129 void FpgaSetupSscDma(BYTE *buf, int len)
 130 {
 131         PDC_RX_POINTER(SSC_BASE) = (DWORD)buf;
 132         PDC_RX_COUNTER(SSC_BASE) = len;
 133         PDC_RX_NEXT_POINTER(SSC_BASE) = (DWORD)buf;
 134         PDC_RX_NEXT_COUNTER(SSC_BASE) = len;
 135         PDC_CONTROL(SSC_BASE) = PDC_RX_ENABLE;
 136 }
 137
 138 //-----------------------------------------------------------------------------
 139 // Download the FPGA image stored in flash (slave serial).
 140 //-----------------------------------------------------------------------------
 141 void FpgaDownloadAndGo(void)
 142 {
 143         // FPGA image lives in FLASH at base address 0x2000
 144         // The current board design can not accomodate anything bigger than a XC2S30
 145         // FPGA and the config file size is fixed at 336,768 bits = 10,524 DWORDs
 146         const DWORD *FpgaImage=((DWORD *)0x2000);
 147         const DWORD FpgaImageLen=10524;
 148
 149         int i, j;
 150
 151         PIO_OUTPUT_ENABLE = (1 << GPIO_FPGA_ON);
 152         PIO_ENABLE = (1 << GPIO_FPGA_ON);
 153         PIO_OUTPUT_DATA_SET = (1 << GPIO_FPGA_ON);
 154
 155         SpinDelay(50);
 156
 157         LED_D_ON();
 158
 159         HIGH(GPIO_FPGA_NPROGRAM);
 160         LOW(GPIO_FPGA_CCLK);
 161         LOW(GPIO_FPGA_DIN);
 162         PIO_OUTPUT_ENABLE = (1 << GPIO_FPGA_NPROGRAM)   |
 163                                                 (1 << GPIO_FPGA_CCLK)           |
 164                                                 (1 << GPIO_FPGA_DIN);
 165         SpinDelay(1);
 166
 167         LOW(GPIO_FPGA_NPROGRAM);
 168         SpinDelay(50);
 169         HIGH(GPIO_FPGA_NPROGRAM);
 170
 171         for(i = 0; i < FpgaImageLen; i++) {
 172                 DWORD v = FpgaImage[i];
 173                 for(j = 0; j < 32; j++) {
 174                         if(v & 0x80000000) {
 175                                 HIGH(GPIO_FPGA_DIN);
 176                         } else {
 177                                 LOW(GPIO_FPGA_DIN);
 178                         }
 179                         HIGH(GPIO_FPGA_CCLK);
 180                         LOW(GPIO_FPGA_CCLK);
 181                         v <<= 1;
 182                 }
 183         }
 184
 185         LED_D_OFF();
 186 }
 187
 188 //-----------------------------------------------------------------------------
 189 // Write the FPGA setup word (that determines what mode the logic is in, read
 190 // vs. clone vs. etc.).
 191 //-----------------------------------------------------------------------------
 192 void FpgaWriteConfWord(BYTE v)
 193 {
 194         SetupSpi(SPI_FPGA_MODE);
 195         while ((SPI_STATUS & SPI_STATUS_TX_EMPTY) == 0);        // wait for the transfer to complete
 196         SPI_TX_DATA = SPI_CONTROL_LAST_TRANSFER | v;            // send the data
 197 }
 198
 199 //-----------------------------------------------------------------------------
 200 // Set up the CMOS switches that mux the ADC: four switches, independently
 201 // closable, but should only close one at a time. Not an FPGA thing, but
 202 // the samples from the ADC always flow through the FPGA.
 203 //-----------------------------------------------------------------------------
 204 void SetAdcMuxFor(int whichGpio)
 205 {
 206         PIO_OUTPUT_ENABLE = (1 << GPIO_MUXSEL_HIPKD) |
 207                                                 (1 << GPIO_MUXSEL_LOPKD) |
 208                                                 (1 << GPIO_MUXSEL_LORAW) |
 209                                                 (1 << GPIO_MUXSEL_HIRAW);
 210
 211         PIO_ENABLE              =       (1 << GPIO_MUXSEL_HIPKD) |
 212                                                 (1 << GPIO_MUXSEL_LOPKD) |
 213                                                 (1 << GPIO_MUXSEL_LORAW) |
 214                                                 (1 << GPIO_MUXSEL_HIRAW);
 215
 216         LOW(GPIO_MUXSEL_HIPKD);
 217         LOW(GPIO_MUXSEL_HIRAW);
 218         LOW(GPIO_MUXSEL_LORAW);
 219         LOW(GPIO_MUXSEL_LOPKD);
 220
 221         HIGH(whichGpio);
 222 }