1 //-----------------------------------------------------------------------------
2 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
3 // at your option, any later version. See the LICENSE.txt file for the text of
5 //-----------------------------------------------------------------------------
6 // HitagS emulation (preliminary test version)
8 // (c) 2016 Oguzhan Cicek, Hendrik Schwartke, Ralf Spenneberg
10 //-----------------------------------------------------------------------------
11 // Some code was copied from Hitag2.c
12 //-----------------------------------------------------------------------------
16 #include "proxmark3.h"
23 #include "fpgaloader.h"
25 #define CRC_PRESET 0xFF
26 #define CRC_POLYNOM 0x1D
31 #define rev8(x) ((((x)>>7)&1)+((((x)>>6)&1)<<1)+((((x)>>5)&1)<<2)+((((x)>>4)&1)<<3)+((((x)>>3)&1)<<4)+((((x)>>2)&1)<<5)+((((x)>>1)&1)<<6)+(((x)&1)<<7))
32 #define rev16(x) (rev8 (x)+(rev8 (x>> 8)<< 8))
33 #define rev32(x) (rev16(x)+(rev16(x>>16)<<16))
34 #define rev64(x) (rev32(x)+(rev32(x>>32)<<32))
35 #define bit(x,n) (((x)>>(n))&1)
36 #define bit32(x,n) ((((x)[(n)>>5])>>((n)))&1)
37 #define inv32(x,i,n) ((x)[(i)>>5]^=((u32)(n))<<((i)&31))
38 #define rotl64(x, n) ((((u64)(x))<<((n)&63))+(((u64)(x))>>((0-(n))&63)))
41 static bool bSuccessful
;
42 static struct hitagS_tag tag
;
43 static byte_t page_to_be_written
= 0;
44 static int block_data_left
= 0;
45 typedef enum modulation
{
46 AC2K
= 0, AC4K
, MC4K
, MC8K
48 static MOD m
= AC2K
; //used modulation
49 static uint32_t temp_uid
;
51 static int sof_bits
; //number of start-of-frame bits
52 static byte_t pwdh0
, pwdl0
, pwdl1
; //password bytes
53 static uint32_t rnd
= 0x74124485; //randomnumber
58 // Single bit Hitag2 functions:
59 #define i4(x,a,b,c,d) ((u32)((((x)>>(a))&1)+(((x)>>(b))&1)*2+(((x)>>(c))&1)*4+(((x)>>(d))&1)*8))
60 static const u32 ht2_f4a
= 0x2C79; // 0010 1100 0111 1001
61 static const u32 ht2_f4b
= 0x6671; // 0110 0110 0111 0001
62 static const u32 ht2_f5c
= 0x7907287B; // 0111 1001 0000 0111 0010 1000 0111 1011
63 #define ht2bs_4a(a,b,c,d) (~(((a|b)&c)^(a|d)^b))
64 #define ht2bs_4b(a,b,c,d) (~(((d|c)&(a^b))^(d|a|b)))
65 #define ht2bs_5c(a,b,c,d,e) (~((((((c^e)|d)&a)^b)&(c^b))^(((d^e)|a)&((d^b)|c))))
68 static u32
f20(const u64 x
) {
71 i5
= ((ht2_f4a
>> i4(x
, 1, 2, 4, 5)) & 1) * 1
72 + ((ht2_f4b
>> i4(x
, 7, 11, 13, 14)) & 1) * 2
73 + ((ht2_f4b
>> i4(x
, 16, 20, 22, 25)) & 1) * 4
74 + ((ht2_f4b
>> i4(x
, 27, 28, 30, 32)) & 1) * 8
75 + ((ht2_f4a
>> i4(x
, 33, 42, 43, 45)) & 1) * 16;
77 return (ht2_f5c
>> i5
) & 1;
79 static u64
hitag2_round(u64
*state
) {
83 + ((((x
>> 0) ^ (x
>> 2) ^ (x
>> 3) ^ (x
>> 6) ^ (x
>> 7) ^ (x
>> 8)
84 ^ (x
>> 16) ^ (x
>> 22) ^ (x
>> 23) ^ (x
>> 26) ^ (x
>> 30)
85 ^ (x
>> 41) ^ (x
>> 42) ^ (x
>> 43) ^ (x
>> 46) ^ (x
>> 47))
91 static u64
hitag2_init(const u64 key
, const u32 serial
, const u32 IV
) {
93 u64 x
= ((key
& 0xFFFF) << 32) + serial
;
94 for (i
= 0; i
< 32; i
++) {
96 x
+= (u64
) (f20(x
) ^ (((IV
>> i
) ^ (key
>> (i
+ 16))) & 1)) << 47;
100 static u32
hitag2_byte(u64
*x
) {
103 for (i
= 0, c
= 0; i
< 8; i
++)
104 c
+= (u32
) hitag2_round(x
) << (i
^ 7);
108 // Sam7s has several timers, we will use the source TIMER_CLOCK1 (aka AT91C_TC_CLKS_TIMER_DIV1_CLOCK)
109 // TIMER_CLOCK1 = MCK/2, MCK is running at 48 MHz, Timer is running at 48/2 = 24 MHz
110 // Hitag units (T0) have duration of 8 microseconds (us), which is 1/125000 per second (carrier)
111 // T0 = TIMER_CLOCK1 / 125000 = 192
114 #define SHORT_COIL() LOW(GPIO_SSC_DOUT)
115 #define OPEN_COIL() HIGH(GPIO_SSC_DOUT)
117 #define HITAG_FRAME_LEN 20
118 #define HITAG_T_STOP 36 /* T_EOF should be > 36 */
119 #define HITAG_T_LOW 8 /* T_LOW should be 4..10 */
120 #define HITAG_T_0_MIN 15 /* T[0] should be 18..22 */
121 #define HITAG_T_1_MIN 25 /* T[1] should be 26..30 */
122 //#define HITAG_T_EOF 40 /* T_EOF should be > 36 */
123 #define HITAG_T_EOF 80 /* T_EOF should be > 36 */
124 #define HITAG_T_WAIT_1 200 /* T_wresp should be 199..206 */
125 #define HITAG_T_WAIT_2 90 /* T_wresp should be 199..206 */
126 #define HITAG_T_WAIT_MAX 300 /* bit more than HITAG_T_WAIT_1 + HITAG_T_WAIT_2 */
128 #define HITAG_T_TAG_ONE_HALF_PERIOD 10
129 #define HITAG_T_TAG_TWO_HALF_PERIOD 25
130 #define HITAG_T_TAG_THREE_HALF_PERIOD 41
131 #define HITAG_T_TAG_FOUR_HALF_PERIOD 57
133 #define HITAG_T_TAG_HALF_PERIOD 16
134 #define HITAG_T_TAG_FULL_PERIOD 32
136 #define HITAG_T_TAG_CAPTURE_ONE_HALF 13
137 #define HITAG_T_TAG_CAPTURE_TWO_HALF 25
138 #define HITAG_T_TAG_CAPTURE_THREE_HALF 41
139 #define HITAG_T_TAG_CAPTURE_FOUR_HALF 57
144 * Implementation of the crc8 calculation from Hitag S
145 * from http://www.proxmark.org/files/Documents/125%20kHz%20-%20Hitag/HitagS.V11.pdf
147 void calc_crc(unsigned char * crc
, unsigned char data
, unsigned char Bitcount
) {
148 *crc
^= data
; // crc = crc (exor) data
150 if (*crc
& 0x80) // if (MSB-CRC == 1)
152 *crc
<<= 1; // CRC = CRC Bit-shift left
153 *crc
^= CRC_POLYNOM
; // CRC = CRC (exor) CRC_POLYNOM
155 *crc
<<= 1; // CRC = CRC Bit-shift left
157 } while (--Bitcount
);
161 static void hitag_send_bit(int bit
) {
163 // Reset clock for the next bit
164 AT91C_BASE_TC0
->TC_CCR
= AT91C_TC_SWTRG
;
171 while (AT91C_BASE_TC0
->TC_CV
< T0
* 32)
174 while (AT91C_BASE_TC0
->TC_CV
< T0
* 64)
179 while (AT91C_BASE_TC0
->TC_CV
< T0
* 16)
182 while (AT91C_BASE_TC0
->TC_CV
< T0
* 32)
185 while (AT91C_BASE_TC0
->TC_CV
< T0
* 48)
188 while (AT91C_BASE_TC0
->TC_CV
< T0
* 64)
197 while (AT91C_BASE_TC0
->TC_CV
< T0
* HITAG_T_TAG_HALF_PERIOD
)
200 while (AT91C_BASE_TC0
->TC_CV
< T0
* HITAG_T_TAG_FULL_PERIOD
)
205 while (AT91C_BASE_TC0
->TC_CV
< T0
* 8)
208 while (AT91C_BASE_TC0
->TC_CV
< T0
* 16)
211 while (AT91C_BASE_TC0
->TC_CV
< T0
* 24)
214 while (AT91C_BASE_TC0
->TC_CV
< T0
* 32)
221 // Manchester: Unloaded, then loaded |__--|
223 while (AT91C_BASE_TC0
->TC_CV
< T0
* 16)
226 while (AT91C_BASE_TC0
->TC_CV
< T0
* 32)
229 // Manchester: Loaded, then unloaded |--__|
231 while (AT91C_BASE_TC0
->TC_CV
< T0
* 16)
234 while (AT91C_BASE_TC0
->TC_CV
< T0
* 32)
241 // Manchester: Unloaded, then loaded |__--|
243 while (AT91C_BASE_TC0
->TC_CV
< T0
* 8)
246 while (AT91C_BASE_TC0
->TC_CV
< T0
* 16)
249 // Manchester: Loaded, then unloaded |--__|
251 while (AT91C_BASE_TC0
->TC_CV
< T0
* 8)
254 while (AT91C_BASE_TC0
->TC_CV
< T0
* 16)
264 static void hitag_tag_send_frame(const byte_t
* frame
, size_t frame_len
) {
265 // Send start of frame
266 for (size_t i
= 0; i
< sof_bits
; i
++) {
270 // Send the content of the frame
271 for (size_t i
= 0; i
< frame_len
; i
++) {
272 hitag_send_bit((frame
[i
/ 8] >> (7 - (i
% 8))) & 1);
274 // Drop the modulation
278 static void hitag_reader_send_bit(int bit
) {
279 //Dbprintf("BIT: %d",bit);
281 // Reset clock for the next bit
282 AT91C_BASE_TC0
->TC_CCR
= AT91C_TC_SWTRG
;
284 // Binary puls length modulation (BPLM) is used to encode the data stream
285 // This means that a transmission of a one takes longer than that of a zero
287 // Enable modulation, which means, drop the the field
290 // Wait for 4-10 times the carrier period
291 while (AT91C_BASE_TC0
->TC_CV
< T0
* 6)
295 // Disable modulation, just activates the field again
300 while (AT91C_BASE_TC0
->TC_CV
< T0
* 11)
302 // SpinDelayUs(16*8);
305 while (AT91C_BASE_TC0
->TC_CV
< T0
* 14)
307 // SpinDelayUs(22*8);
310 // Wait for 4-10 times the carrier period
311 while (AT91C_BASE_TC0
->TC_CV
< T0
* 6)
315 // Disable modulation, just activates the field again
320 while (AT91C_BASE_TC0
->TC_CV
< T0
* 22)
322 // SpinDelayUs(16*8);
325 while (AT91C_BASE_TC0
->TC_CV
< T0
* 28)
327 // SpinDelayUs(22*8);
334 static void hitag_reader_send_frame(const byte_t
* frame
, size_t frame_len
) {
335 // Send the content of the frame
336 for (size_t i
= 0; i
< frame_len
; i
++) {
337 if (frame
[0] == 0xf8) {
338 //Dbprintf("BIT: %d",(frame[i / 8] >> (7 - (i % 8))) & 1);
340 hitag_reader_send_bit(((frame
[i
/ 8] >> (7 - (i
% 8))) & 1));
343 AT91C_BASE_TC0
->TC_CCR
= AT91C_TC_SWTRG
;
344 // Enable modulation, which means, drop the the field
346 // Wait for 4-10 times the carrier period
347 while (AT91C_BASE_TC0
->TC_CV
< T0
* 6)
349 // Disable modulation, just activates the field again
353 static void hitag_decode_frame_MC(int bitRate
, int sofBits
, byte_t
* rx
, size_t* rxlenOrg
, int* response
, int rawMod
[], int rawLen
) {
363 for (int i
=0; i
< rawLen
; i
++) {
365 if (ra
>= HITAG_T_EOF
) {
367 //DbpString("wierd1?");
371 // Capture the T0 periods that have passed since last communication or field drop (reset)
372 // We always recieve a 'one' first, which has the falling edge after a half period |-_|
373 *response
= ra
- HITAG_T_TAG_HALF_PERIOD
;
374 } else if (ra
>= HITAG_T_TAG_CAPTURE_FOUR_HALF
/ timing
) {
376 // Manchester coding example |-_|_-|-_| (101)
377 rx
[rxlen
/ 8] |= 0 << (7 - (rxlen
% 8));
379 rx
[rxlen
/ 8] |= 1 << (7 - (rxlen
% 8));
381 } else if (ra
>= HITAG_T_TAG_CAPTURE_THREE_HALF
/ timing
) {
383 // Manchester coding example |_-|...|_-|-_| (0...01)
384 rx
[rxlen
/ 8] |= 0 << (7 - (rxlen
% 8));
386 // We have to skip this half period at start and add the 'one' the second time
388 rx
[rxlen
/ 8] |= 1 << (7 - (rxlen
% 8));
393 } else if (ra
>= HITAG_T_TAG_CAPTURE_TWO_HALF
/ timing
) {
394 // Manchester coding example |_-|_-| (00) or |-_|-_| (11)
396 // Ignore bits that are transmitted during SOF
399 // bit is same as last bit
400 rx
[rxlen
/ 8] |= lastbit
<< (7 - (rxlen
% 8));
404 // Ignore wierd value, is to small to mean anything
411 static void hitag_decode_frame_AC2K_rising(byte_t* rx, size_t* rxlenOrg, int* response, int rawMod[], int rawLen) {
412 int tag_sof = 1; //skip start of frame
415 for (int i=0; i < rawLen; i++) {
417 if (ra >= HITAG_T_EOF) {
419 //DbpString("wierd1?");
421 // Capture the T0 periods that have passed since last communication or field drop (reset)
422 // We always recieve a 'one' first, which has the falling edge after a half period |-_|
424 *response = ra - HITAG_T_TAG_HALF_PERIOD;
425 } else if (ra >= HITAG_T_TAG_CAPTURE_FOUR_HALF) {
426 // AC coding example |--__|--__| means 0
427 rx[rxlen / 8] |= 0 << (7 - (rxlen % 8));
429 if (rawMod[i+1] == 0) { //TODO: this is weird - may we miss one capture with current configuration
430 rx[rxlen / 8] |= 0 << (7 - (rxlen % 8));
432 i++; //drop next capture
434 } else if (ra >= HITAG_T_TAG_CAPTURE_TWO_HALF) {
436 // Ignore bits that are transmitted during SOF
439 // AC coding example |-_-_|-_-_| which means 1
440 //check if another high is coming (only -_-_ = 1) except end of the frame (support 0)
441 if (rawMod[i+1] == 0 || rawMod[i+1] >= HITAG_T_TAG_CAPTURE_TWO_HALF) {
442 rx[rxlen / 8] |= 1 << (7 - (rxlen % 8));
444 i++; //drop next capture
446 Dbprintf("got weird high - %d,%d", ra, rawMod[i+1]);
450 // Ignore wierd value, is to small to mean anything
457 static void hitag_decode_frame_AC(int bitRate
, int sofBits
, byte_t
* rx
, size_t* rxlenOrg
, int* response
, int rawMod
[], int rawLen
) {
466 for (int i
=0; i
< rawLen
; i
++) {
468 if (ra
>= HITAG_T_EOF
) {
470 //DbpString("wierd1?");
473 // Capture the T0 periods that have passed since last communication or field drop (reset)
474 // We always recieve a 'one' first, which has the falling edge after a half period |-_|
476 *response
= ra
- HITAG_T_TAG_HALF_PERIOD
;
477 } else if (ra
>= HITAG_T_TAG_CAPTURE_FOUR_HALF
/ timing
) {
480 // AC coding example |--__|--__| means 0
481 rx
[rxlen
/ 8] |= 0 << (7 - (rxlen
% 8));
483 } else if (ra
>= HITAG_T_TAG_CAPTURE_THREE_HALF
/ timing
) {
486 if (rawMod
[i
-1] >= HITAG_T_TAG_CAPTURE_THREE_HALF
/ timing
) {
487 //treat like HITAG_T_TAG_CAPTURE_TWO_HALF
488 if (rawMod
[i
+1] >= HITAG_T_TAG_CAPTURE_TWO_HALF
/ timing
) {
489 rx
[rxlen
/ 8] |= 1 << (7 - (rxlen
% 8));
491 i
++; //drop next capture
493 Dbprintf("got weird value - %d,%d", ra
, rawMod
[i
+1]);
496 //treat like HITAG_T_TAG_CAPTURE_FOUR_HALF
497 rx
[rxlen
/ 8] |= 0 << (7 - (rxlen
% 8));
500 } else if (ra
>= HITAG_T_TAG_CAPTURE_TWO_HALF
/ timing
) {
502 // Ignore bits that are transmitted during SOF
505 // AC coding example |-_-_|-_-_| which means 1
506 //check if another high is coming (only -_-_ = 1) except end of the frame (support 0)
507 if (rawMod
[i
+1] == 0 || rawMod
[i
+1] >= HITAG_T_TAG_CAPTURE_TWO_HALF
/ timing
) {
508 rx
[rxlen
/ 8] |= 1 << (7 - (rxlen
% 8));
510 i
++; //drop next capture
512 Dbprintf("got weird value - %d,%d", ra
, rawMod
[i
+1]);
516 // Ignore wierd value, is to small to mean anything
522 static void hitag_receive_frame(byte_t
* rx
, size_t* rxlen
, int* response
) {
523 int rawMod
[200] = {0};
529 if (tag
.pstate
== READY
) {
537 sofBits
= 5; //3 sof bits but 5 captures
541 sofBits
= 5; //3 sof bits but 5 captures
550 sofBits
= 0; //in theory 1
554 sofBits
= 5; //in theory 6
558 sofBits
= 5; //in theory 6
565 //rising AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_TIMER_DIV1_CLOCK | AT91C_TC_ETRGEDG_RISING | AT91C_TC_ABETRG | AT91C_TC_LDRA_RISING;
566 AT91C_BASE_TC1
->TC_CMR
= AT91C_TC_CLKS_TIMER_DIV1_CLOCK
| AT91C_TC_ETRGEDG_FALLING
| AT91C_TC_ABETRG
| AT91C_TC_LDRA_FALLING
;
569 //first capture timing values
570 while (AT91C_BASE_TC1
->TC_CV
< T0
* HITAG_T_WAIT_MAX
) {
571 // Check if rising edge in modulation is detected
572 if (AT91C_BASE_TC1
->TC_SR
& AT91C_TC_LDRAS
) {
573 // Retrieve the new timing values
574 int ra
= (AT91C_BASE_TC1
->TC_RA
/ T0
);
577 // Reset timer every frame, we have to capture the last edge for timing
578 AT91C_BASE_TC0
->TC_CCR
= AT91C_TC_CLKEN
| AT91C_TC_SWTRG
;
579 //AT91C_BASE_TC0->TC_CCR = AT91C_TC_SWTRG;
581 if (rawLen
>= 200) { //avoid exception
587 // We can break this loop if we received the last bit from a frame
588 if (AT91C_BASE_TC1
->TC_CV
> T0
* HITAG_T_EOF
) {
590 if (DEBUG
>= 2) { Dbprintf("AT91C_BASE_TC1->TC_CV > T0 * HITAG_T_EOF breaking (%d)", rawLen
); }
598 for (i
=0; i
< rawLen
; i
+=20) {
599 Dbprintf("raw modulation: - %d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d",
600 rawMod
[i
],rawMod
[i
+1],rawMod
[i
+2],rawMod
[i
+3], rawMod
[i
+4],rawMod
[i
+5],rawMod
[i
+6],rawMod
[i
+7],
601 rawMod
[i
+8],rawMod
[i
+9],rawMod
[i
+10],rawMod
[i
+11], rawMod
[i
+12],rawMod
[i
+13],rawMod
[i
+14],rawMod
[i
+15],
602 rawMod
[i
+16],rawMod
[i
+17],rawMod
[i
+18],rawMod
[i
+19]
608 // DATA | 1 | 0 | 1 | 1 | 0 |
609 // Manchester |--__|__--|--__|--__|__--|
610 // Anti Collision |-_-_|--__|-_-_|-_-_|--__|
614 if (DEBUG
>= 2) { Dbprintf("decoding frame with modulation AC2K"); }
615 hitag_decode_frame_AC(2, sofBits
, rx
, rxlen
, response
, rawMod
, rawLen
);
618 if (DEBUG
>= 2) { Dbprintf("decoding frame with modulation AC4K"); }
619 hitag_decode_frame_AC(4, sofBits
, rx
, rxlen
, response
, rawMod
, rawLen
);
622 if (DEBUG
>= 2) { Dbprintf("decoding frame with modulation MC4K"); }
623 hitag_decode_frame_MC(4, sofBits
, rx
, rxlen
, response
, rawMod
, rawLen
);
626 if (DEBUG
>= 2) { Dbprintf("decoding frame with modulation MC8K"); }
627 hitag_decode_frame_MC(8, sofBits
, rx
, rxlen
, response
, rawMod
, rawLen
);
633 int rb
[200] = {0}; int z
= 0;
634 for (i
= 0; i
< 16; i
++) { for (int j
= 0; j
< 8; j
++) {
636 if ((rx
[i
] & ((1 << 7) >> j
)) != 0) { rb
[z
] = 1; }
639 for (i
=0; i
< z
; i
+=8) {
640 Dbprintf("raw bit: - %d%d%d%d%d%d%d%d", rb
[i
],rb
[i
+1],rb
[i
+2],rb
[i
+3],rb
[i
+4],rb
[i
+5],rb
[i
+6],rb
[i
+7] );
645 static void hitag_start_auth(byte_t
* tx
, size_t* txlen
) {
649 //00110 - 0x30 - STANDARD MODE
650 memcpy(tx
, "\x30", nbytes(*txlen
));
653 //11000 - 0xc0 - Advance Mode
654 memcpy(tx
, "\xc0", nbytes(*txlen
));
659 default: //STANDARD MODE
660 memcpy(tx
, "\x30", nbytes(*txlen
));
667 static int hitag_read_page(hitag_function htf
, uint64_t key
, byte_t
* rx
, size_t* rxlen
, byte_t
* tx
, size_t* txlen
, int pageNum
) {
669 int response_bit
[200];
670 unsigned char mask
= 1;
672 unsigned char pageData
[32];
674 if (pageNum
>= tag
.max_page
) {
677 if (tag
.pstate
== SELECTED
&& tag
.tstate
== NO_OP
&& *rxlen
> 0) {
679 tag
.tstate
= READING_PAGE
;
682 tx
[0] = 0xc0 + (pageNum
/ 16);
683 calc_crc(&crc
, tx
[0], 8);
684 calc_crc(&crc
, 0x00 + ((pageNum
% 16) * 16), 4);
685 tx
[1] = 0x00 + ((pageNum
% 16) * 16) + (crc
/ 16);
686 tx
[2] = 0x00 + (crc
% 16) * 16;
687 } else if (tag
.pstate
== SELECTED
&& tag
.tstate
== READING_PAGE
&& *rxlen
> 0) {
690 for (i
= 0; i
< 4; i
++) {
691 for (j
= 0; j
< 8; j
++) {
693 if ((rx
[i
] & ((mask
<< 7) >> j
)) != 0) {
697 pageData
[z
] = response_bit
[z
];
703 for (i
= 0; i
< 4; i
++) {
704 tag
.pages
[pageNum
][i
] = 0x0;
706 for (i
= 0; i
< 4; i
++) {
707 tag
.pages
[pageNum
][i
] += ((pageData
[i
* 8] << 7) | (pageData
[1 + (i
* 8)] << 6) |
708 (pageData
[2 + (i
* 8)] << 5) | (pageData
[3 + (i
* 8)] << 4) |
709 (pageData
[4 + (i
* 8)] << 3) | (pageData
[5 + (i
* 8)] << 2) |
710 (pageData
[6 + (i
* 8)]
711 << 1) | pageData
[7 + (i
* 8)]);
713 if (tag
.auth
&& tag
.LKP
&& pageNum
== 1) {
714 Dbprintf("Page[%2d]: %02X %02X %02X %02X", pageNum
, pwdh0
,
715 tag
.pages
[pageNum
][2], tag
.pages
[pageNum
][1], tag
.pages
[pageNum
][0]);
717 Dbprintf("Page[%2d]: %02X %02X %02X %02X", pageNum
,
718 tag
.pages
[pageNum
][3], tag
.pages
[pageNum
][2],
719 tag
.pages
[pageNum
][1], tag
.pages
[pageNum
][0]);
723 //display key and password if possible
724 if (pageNum
== 1 && tag
.auth
== 1 && tag
.LKP
) {
725 if (htf
== 02) { //RHTS_KEY
726 Dbprintf("Page[ 2]: %02X %02X %02X %02X",
727 (byte_t
)(key
>> 8) & 0xff,
728 (byte_t
) key
& 0xff, pwdl1
, pwdl0
);
729 Dbprintf("Page[ 3]: %02X %02X %02X %02X",
730 (byte_t
)(key
>> 40) & 0xff,
731 (byte_t
)(key
>> 32) & 0xff,
732 (byte_t
)(key
>> 24) & 0xff,
733 (byte_t
)(key
>> 16) & 0xff);
735 //if the authentication is done with a challenge the key and password are unknown
736 Dbprintf("Page[ 2]: __ __ __ __");
737 Dbprintf("Page[ 3]: __ __ __ __");
743 tx
[0] = 0xc0 + ((pageNum
+1) / 16);
744 calc_crc(&crc
, tx
[0], 8);
745 calc_crc(&crc
, 0x00 + (((pageNum
+1) % 16) * 16), 4);
746 tx
[1] = 0x00 + (((pageNum
+1) % 16) * 16) + (crc
/ 16);
747 tx
[2] = 0x00 + (crc
% 16) * 16;
754 static int hitag_read_block(hitag_function htf
, uint64_t key
, byte_t
* rx
, size_t* rxlen
, byte_t
* tx
, size_t* txlen
, int blockNum
) {
756 int response_bit
[200];
757 unsigned char mask
= 1;
759 unsigned char blockData
[128];
761 if (blockNum
+4 >= tag
.max_page
) { //block always = 4 pages
765 if (tag
.pstate
== SELECTED
&& tag
.tstate
== NO_OP
&& *rxlen
> 0) {
767 tag
.tstate
= READING_BLOCK
;
770 tx
[0] = 0xd0 + (blockNum
/ 16);
771 calc_crc(&crc
, tx
[0], 8);
772 calc_crc(&crc
, 0x00 + ((blockNum
% 16) * 16), 4);
773 tx
[1] = 0x00 + ((blockNum
% 16) * 16) + (crc
/ 16);
774 tx
[2] = 0x00 + (crc
% 16) * 16;
775 } else if (tag
.pstate
== SELECTED
&& tag
.tstate
== READING_BLOCK
&& *rxlen
> 0) {
778 for (i
= 0; i
< 16; i
++) {
779 for (j
= 0; j
< 8; j
++) {
781 if ((rx
[i
] & ((mask
<< 7) >> j
)) != 0) {
785 blockData
[z
] = response_bit
[z
];
791 for (z
= 0; z
< 4; z
++) { //4 pages
792 for (i
= 0; i
< 4; i
++) {
793 tag
.pages
[blockNum
+z
][i
] = 0x0;
796 for (z
= 0; z
< 4; z
++) { //4 pages
797 for (i
= 0; i
< 4; i
++) {
798 j
= (i
* 8) + (z
*32); //bit in page + pageStart
799 tag
.pages
[blockNum
+z
][i
] = ((blockData
[j
] << 7) | (blockData
[1 + j
] << 6) |
800 (blockData
[2 + j
] << 5) | (blockData
[3 + j
] << 4) |
801 (blockData
[4 + j
] << 3) | (blockData
[5 + j
] << 2) |
802 (blockData
[6 + j
] << 1) | blockData
[7 + j
]);
806 for (z
= 0; z
< 4; z
++) {
807 Dbprintf("Page[%2d]: %02X %02X %02X %02X", blockNum
+z
,
808 tag
.pages
[blockNum
+z
][3], tag
.pages
[blockNum
+z
][2],
809 tag
.pages
[blockNum
+z
][1], tag
.pages
[blockNum
+z
][0]);
812 Dbprintf("Block[%2d]: %02X %02X %02X %02X - %02X %02X %02X %02X - %02X %02X %02X %02X - %02X %02X %02X %02X", blockNum
,
813 tag
.pages
[blockNum
][3], tag
.pages
[blockNum
][2], tag
.pages
[blockNum
][1], tag
.pages
[blockNum
][0],
814 tag
.pages
[blockNum
+1][3], tag
.pages
[blockNum
+1][2], tag
.pages
[blockNum
+1][1], tag
.pages
[blockNum
+1][0],
815 tag
.pages
[blockNum
+2][3], tag
.pages
[blockNum
+2][2], tag
.pages
[blockNum
+2][1], tag
.pages
[blockNum
+2][0],
816 tag
.pages
[blockNum
+3][3], tag
.pages
[blockNum
+3][2], tag
.pages
[blockNum
+3][1], tag
.pages
[blockNum
+3][0]);
820 tx
[0] = 0xd0 + ((blockNum
+4) / 16);
821 calc_crc(&crc
, tx
[0], 8);
822 calc_crc(&crc
, 0x00 + (((blockNum
+4) % 16) * 16), 4);
823 tx
[1] = 0x00 + (((blockNum
+4) % 16) * 16) + (crc
/ 16);
824 tx
[2] = 0x00 + (crc
% 16) * 16;
833 * to check if the right uid was selected
835 static int check_select(byte_t
* rx
, uint32_t uid
) {
836 unsigned char resp
[48];
839 for (i
= 0; i
< 48; i
++)
840 resp
[i
] = (rx
[i
/ 8] >> (7 - (i
% 8))) & 0x1;
841 for (i
= 0; i
< 32; i
++)
842 ans
+= resp
[5 + i
] << (31 - i
);
843 /*if (rx[0] == 0x01 && rx[1] == 0x15 && rx[2] == 0xc1 && rx[3] == 0x14
844 && rx[4] == 0x65 && rx[5] == 0x38)
845 Dbprintf("got uid %X", ans);*/
853 * handles all commands from a reader
855 static void hitagS_handle_reader_command(byte_t
* rx
, const size_t rxlen
,
856 byte_t
* tx
, size_t* txlen
) {
857 byte_t rx_air
[HITAG_FRAME_LEN
];
863 // Copy the (original) received frame how it is send over the air
864 memcpy(rx_air
, rx
, nbytes(rxlen
));
865 // Reset the transmission frame length
867 // Try to find out which command was send by selecting on length (in bits)
870 //UID request with a selected response protocol mode
873 if ((rx
[0] & 0xf0) == 0x30) {
874 Dbprintf("recieved uid request in Standard Mode");
879 if ((rx
[0] & 0xf0) == 0xc0) {
880 Dbprintf("recieved uid request in ADVANCE Mode");
885 if ((rx
[0] & 0xf0) == 0xd0) {
886 Dbprintf("recieved uid request in FAST_ADVANCE Mode");
887 tag
.mode
= FAST_ADVANCED
;
891 //send uid as a response
893 for (i
= 0; i
< 4; i
++) {
894 tx
[i
] = (tag
.uid
>> (24 - (i
* 8))) & 0xff;
899 //select command from reader received
900 if (check_select(rx
, tag
.uid
) == 1) {
901 //if the right tag was selected
905 Dbprintf("uid selected in Standard Mode");
910 Dbprintf("uid selected in ADVANCE Mode");
915 Dbprintf("uid selected in FAST_ADVANCE Mode");
924 tx
[0] = tag
.pages
[1][3];
925 tx
[1] = tag
.pages
[1][2];
926 tx
[2] = tag
.pages
[1][1];
928 if (tag
.mode
!= STANDARD
) {
931 for (i
= 0; i
< 4; i
++)
932 calc_crc(&crc
, tx
[i
], 8);
955 //challenge message received
956 Dbprintf("Challenge for UID: %X", temp_uid
);
958 state
= hitag2_init(rev64(tag
.key
), rev32(tag
.pages
[0][0]),
959 rev32(((rx
[3] << 24) + (rx
[2] << 16) + (rx
[1] << 8) + rx
[0])));
961 ",{0x%02X, 0x%02X, 0x%02X, 0x%02X, 0x%02X, 0x%02X, 0x%02X, 0x%02X}",
962 rx
[0], rx
[1], rx
[2], rx
[3], rx
[4], rx
[5], rx
[6], rx
[7]);
964 for (i
= 0; i
< 4; i
++) {
969 //send con2,pwdh0,pwdl0,pwdl1 encrypted as a response
970 tx
[0] = hitag2_byte(&state
) ^ tag
.pages
[1][1];
971 tx
[1] = hitag2_byte(&state
) ^ tag
.pwdh0
;
972 tx
[2] = hitag2_byte(&state
) ^ tag
.pwdl0
;
973 tx
[3] = hitag2_byte(&state
) ^ tag
.pwdl1
;
974 if (tag
.mode
!= STANDARD
) {
978 calc_crc(&crc
, tag
.pages
[1][1], 8);
979 calc_crc(&crc
, tag
.pwdh0
, 8);
980 calc_crc(&crc
, tag
.pwdl0
, 8);
981 calc_crc(&crc
, tag
.pwdl1
, 8);
982 tx
[4] = (crc
^ hitag2_byte(&state
));
986 //data received to be written
987 if (tag
.tstate
== WRITING_PAGE_DATA
) {
989 tag
.pages
[page_to_be_written
][0] = rx
[3];
990 tag
.pages
[page_to_be_written
][1] = rx
[2];
991 tag
.pages
[page_to_be_written
][2] = rx
[1];
992 tag
.pages
[page_to_be_written
][3] = rx
[0];
997 page_to_be_written
= 0;
1014 } else if (tag
.tstate
== WRITING_BLOCK_DATA
) {
1015 tag
.pages
[page_to_be_written
][0] = rx
[0];
1016 tag
.pages
[page_to_be_written
][1] = rx
[1];
1017 tag
.pages
[page_to_be_written
][2] = rx
[2];
1018 tag
.pages
[page_to_be_written
][3] = rx
[3];
1039 page_to_be_written
++;
1041 if (block_data_left
== 0) {
1043 page_to_be_written
= 0;
1048 //write page, write block, read page or read block command received
1049 if ((rx
[0] & 0xf0) == 0xc0) { //read page
1051 page
= ((rx
[0] & 0x0f) * 16) + ((rx
[1] & 0xf0) / 16);
1052 Dbprintf("reading page %d", page
);
1054 tx
[0] = tag
.pages
[page
][0];
1055 tx
[1] = tag
.pages
[page
][1];
1056 tx
[2] = tag
.pages
[page
][2];
1057 tx
[3] = tag
.pages
[page
][3];
1059 if (tag
.LKP
&& page
== 1)
1079 if (tag
.mode
!= STANDARD
) {
1083 for (i
= 0; i
< 4; i
++)
1084 calc_crc(&crc
, tx
[i
], 8);
1088 if (tag
.LKP
&& (page
== 2 || page
== 3)) {
1089 //if reader asks for key or password and the LKP-mark is set do not respond
1093 } else if ((rx
[0] & 0xf0) == 0xd0) { //read block
1094 page
= ((rx
[0] & 0x0f) * 16) + ((rx
[1] & 0xf0) / 16);
1095 Dbprintf("reading block %d", page
);
1097 //send page,...,page+3 data
1098 for (i
= 0; i
< 4; i
++) {
1099 tx
[0 + (i
* 4)] = tag
.pages
[page
][0];
1100 tx
[1 + (i
* 4)] = tag
.pages
[page
][1];
1101 tx
[2 + (i
* 4)] = tag
.pages
[page
][2];
1102 tx
[3 + (i
* 4)] = tag
.pages
[page
][3];
1123 if (tag
.mode
!= STANDARD
) {
1125 *txlen
= 32 * 4 + 8;
1127 for (i
= 0; i
< 16; i
++)
1128 calc_crc(&crc
, tx
[i
], 8);
1132 if ((page
- 4) % 4 != 0 || (tag
.LKP
&& (page
- 4) == 0)) {
1136 } else if ((rx
[0] & 0xf0) == 0x80) { //write page
1137 page
= ((rx
[0] & 0x0f) * 16) + ((rx
[1] & 0xf0) / 16);
1155 if ((tag
.LCON
&& page
== 1)
1156 || (tag
.LKP
&& (page
== 2 || page
== 3))) {
1163 page_to_be_written
= page
;
1164 tag
.tstate
= WRITING_PAGE_DATA
;
1167 } else if ((rx
[0] & 0xf0) == 0x90) { //write block
1168 page
= ((rx
[0] & 0x0f) * 6) + ((rx
[1] & 0xf0) / 16);
1185 if (page
% 4 != 0 || page
== 0) {
1192 page_to_be_written
= page
;
1193 block_data_left
= 4;
1194 tag
.tstate
= WRITING_BLOCK_DATA
;
1207 * to autenticate to a tag with the given key or challenge
1209 static int hitagS_handle_tag_auth(hitag_function htf
,uint64_t key
, uint64_t NrAr
, byte_t
* rx
,
1210 const size_t rxlen
, byte_t
* tx
, size_t* txlen
) {
1211 byte_t rx_air
[HITAG_FRAME_LEN
];
1212 int response_bit
[200] = {0};
1214 unsigned char mask
= 1;
1215 unsigned char uid
[32];
1216 byte_t uid1
= 0x00, uid2
= 0x00, uid3
= 0x00, uid4
= 0x00;
1220 byte_t conf_pages
[3];
1221 memcpy(rx_air
, rx
, nbytes(rxlen
));
1225 Dbprintf("START hitagS_handle_tag_auth - rxlen: %d, tagstate=%d", rxlen
, (int)tag
.pstate
);
1228 if (tag
.pstate
== READY
&& rxlen
>= 32) {
1231 Dbprintf("authentication failed!");
1235 for (i
= 0; i
< 10; i
++) {
1236 for (j
= 0; j
< 8; j
++) {
1237 response_bit
[z
] = 0;
1238 if ((rx
[i
] & ((mask
<< 7) >> j
)) != 0)
1239 response_bit
[z
] = 1;
1243 for (i
= 0; i
< 32; i
++) {
1244 uid
[i
] = response_bit
[i
];
1247 uid1
= (uid
[0] << 7) | (uid
[1] << 6) | (uid
[2] << 5) | (uid
[3] << 4)
1248 | (uid
[4] << 3) | (uid
[5] << 2) | (uid
[6] << 1) | uid
[7];
1249 uid2
= (uid
[8] << 7) | (uid
[9] << 6) | (uid
[10] << 5) | (uid
[11] << 4)
1250 | (uid
[12] << 3) | (uid
[13] << 2) | (uid
[14] << 1) | uid
[15];
1251 uid3
= (uid
[16] << 7) | (uid
[17] << 6) | (uid
[18] << 5) | (uid
[19] << 4)
1252 | (uid
[20] << 3) | (uid
[21] << 2) | (uid
[22] << 1) | uid
[23];
1253 uid4
= (uid
[24] << 7) | (uid
[25] << 6) | (uid
[26] << 5) | (uid
[27] << 4)
1254 | (uid
[28] << 3) | (uid
[29] << 2) | (uid
[30] << 1) | uid
[31];
1255 Dbprintf("UID: %02X %02X %02X %02X", uid1
, uid2
, uid3
, uid4
);
1256 tag
.uid
= (uid4
<< 24 | uid3
<< 16 | uid2
<< 8 | uid1
);
1260 calc_crc(&crc
, 0x00, 5);
1261 calc_crc(&crc
, uid1
, 8);
1262 calc_crc(&crc
, uid2
, 8);
1263 calc_crc(&crc
, uid3
, 8);
1264 calc_crc(&crc
, uid4
, 8);
1265 Dbprintf("crc: %02X", crc
);
1267 //resetting response bit
1268 for (i
= 0; i
< 100; i
++) {
1269 response_bit
[i
] = 0;
1273 for (i
= 5; i
< 37; i
++) {
1274 response_bit
[i
] = uid
[i
- 5];
1277 for (j
= 0; j
< 8; j
++) {
1278 response_bit
[i
] = 0;
1279 if ((crc
& ((mask
<< 7) >> j
)) != 0)
1280 response_bit
[i
] = 1;
1285 for (i
= 0; i
< 6; i
++) {
1286 tx
[i
] = (response_bit
[k
] << 7) | (response_bit
[k
+ 1] << 6)
1287 | (response_bit
[k
+ 2] << 5) | (response_bit
[k
+ 3] << 4)
1288 | (response_bit
[k
+ 4] << 3) | (response_bit
[k
+ 5] << 2)
1289 | (response_bit
[k
+ 6] << 1) | response_bit
[k
+ 7];
1294 } else if (tag
.pstate
== INIT
&& rxlen
> 24) {
1295 // received configuration after select command
1297 for (i
= 0; i
< 4; i
++) {
1298 for (j
= 0; j
< 8; j
++) {
1299 response_bit
[z
] = 0;
1300 if ((rx
[i
] & ((mask
<< 7) >> j
)) != 0) {
1301 response_bit
[z
] = 1;
1307 //check wich memorysize this tag has
1309 if (response_bit
[6] == 0 && response_bit
[7] == 0)
1310 tag
.max_page
= 32 / 32;
1311 if (response_bit
[6] == 0 && response_bit
[7] == 1)
1312 tag
.max_page
= 256 / 32;
1313 if (response_bit
[6] == 1 && response_bit
[7] == 0)
1314 tag
.max_page
= 2048 / 32;
1315 if (response_bit
[6] == 1 && response_bit
[7] == 1) //reserved but some tags got this setting
1316 tag
.max_page
= 2048 / 32;
1319 tag
.auth
= response_bit
[8];
1320 tag
.TTFC
= response_bit
[9];
1321 //tag.TTFDR in response_bit[10] and response_bit[11]
1322 //tag.TTFM in response_bit[12] and response_bit[13]
1323 tag
.LCON
= response_bit
[14];
1324 tag
.LKP
= response_bit
[15];
1327 tag
.LCK7
= response_bit
[16];
1328 tag
.LCK6
= response_bit
[17];
1329 tag
.LCK5
= response_bit
[18];
1330 tag
.LCK4
= response_bit
[19];
1331 tag
.LCK3
= response_bit
[20];
1332 tag
.LCK2
= response_bit
[21];
1333 tag
.LCK1
= response_bit
[22];
1334 tag
.LCK0
= response_bit
[23];
1337 conf_pages
[0] = ((response_bit
[0] << 7) | (response_bit
[1] << 6)
1338 | (response_bit
[2] << 5) | (response_bit
[3] << 4)
1339 | (response_bit
[4] << 3) | (response_bit
[5] << 2)
1340 | (response_bit
[6] << 1) | response_bit
[7]);
1341 conf_pages
[1] = ((response_bit
[8] << 7) | (response_bit
[9] << 6)
1342 | (response_bit
[10] << 5) | (response_bit
[11] << 4)
1343 | (response_bit
[12] << 3) | (response_bit
[13] << 2)
1344 | (response_bit
[14] << 1) | response_bit
[15]);
1345 conf_pages
[2] = ((response_bit
[16] << 7) | (response_bit
[17] << 6)
1346 | (response_bit
[18] << 5) | (response_bit
[19] << 4)
1347 | (response_bit
[20] << 3) | (response_bit
[21] << 2)
1348 | (response_bit
[22] << 1) | response_bit
[23]);
1349 Dbprintf("conf0: %02X conf1: %02X conf2: %02X", conf_pages
[0], conf_pages
[1], conf_pages
[2]);
1350 Dbprintf("tag.max_page: %d, tag.auth: %d", tag
.max_page
, tag
.auth
);
1353 if (tag
.auth
== 1) {
1354 //if the tag is in authentication mode try the key or challenge
1357 if(htf
==02||htf
==04){ //RHTS_KEY //WHTS_KEY
1358 state
= hitag2_init(rev64(key
), rev32(tag
.uid
), rev32(rnd
));
1360 Dbprintf("key: %02X %02X\n\n", key, rev64(key));
1361 Dbprintf("tag.uid: %02X %02X\n\n", tag.uid, rev32(tag.uid));
1362 Dbprintf("rnd: %02X %02X\n\n", rnd, rev32(rnd));
1364 for (i
= 0; i
< 4; i
++) {
1365 auth_ks
[i
] = hitag2_byte(&state
) ^ 0xff;
1369 tx
[1] = (rnd
>> 8) & 0xff;
1370 tx
[2] = (rnd
>> 16) & 0xff;
1371 tx
[3] = (rnd
>> 24) & 0xff;
1378 Dbprintf("%02X %02X %02X %02X %02X %02X %02X %02X", tx
[0],
1379 tx
[1], tx
[2], tx
[3], tx
[4], tx
[5], tx
[6], tx
[7]);
1380 } else if(htf
==01 || htf
==03) { //RHTS_CHALLENGE //WHTS_CHALLENGE
1381 for (i
= 0; i
< 8; i
++)
1382 tx
[i
]=((NrAr
>>(56-(i
*8)))&0xff);
1385 tag
.pstate
= AUTHENTICATE
;
1387 Dbprintf("authentication failed!");
1390 } else if (tag
.auth
== 0) {
1391 tag
.pstate
= SELECTED
;
1394 } else if (tag
.pstate
== AUTHENTICATE
&& rxlen
>= 32) {
1395 //encrypted con2,password received.
1397 Dbprintf("UID:::%X", tag
.uid
);
1398 Dbprintf("RND:::%X", rnd
);
1405 if(htf
==02 || htf
==04) { //RHTS_KEY //WHTS_KEY
1406 state
= hitag2_init(rev64(key
), rev32(tag
.uid
), rev32(rnd
));
1407 for (i
= 0; i
< 5; i
++) {
1408 hitag2_byte(&state
);
1410 pwdh0
= ((rx
[1] & 0x0f) * 16 + ((rx
[2] & 0xf0) / 16)) ^ hitag2_byte(&state
);
1411 pwdl0
= ((rx
[2] & 0x0f) * 16 + ((rx
[3] & 0xf0) / 16)) ^ hitag2_byte(&state
);
1412 pwdl1
= ((rx
[3] & 0x0f) * 16 + ((rx
[4] & 0xf0) / 16)) ^ hitag2_byte(&state
);
1414 Dbprintf("pwdh0 %02X pwdl0 %02X pwdl1 %02X", pwdh0
, pwdl0
, pwdl1
);
1417 tag
.pstate
= SELECTED
; //tag is now ready for read/write commands
1421 Dbprintf("END hitagS_handle_tag_auth - tagstate=%d", (int)tag
.pstate
);
1428 * Emulates a Hitag S Tag with the given data from the .hts file
1430 void SimulateHitagSTag(bool tag_mem_supplied
, byte_t
* data
) {
1435 byte_t rx
[HITAG_FRAME_LEN
];
1438 byte_t txbuf
[HITAG_FRAME_LEN
];
1441 uint8_t con0
, con1
, con2
;
1444 // Clean up trace and prepare it for storing frames
1448 DbpString("Starting HitagS simulation");
1453 //read tag data into memory
1454 if (tag_mem_supplied
) {
1455 DbpString("Loading hitagS memory...");
1456 for (i
= 0; i
< 64; i
++) {
1457 for (j
= 0; j
< 4; j
++) {
1458 tag
.pages
[i
][j
] = 0x0;
1462 for (i
= 0; i
< 64; i
++) {
1463 for (j
= 0; j
< 4; j
++) {
1464 tag
.pages
[i
][j
] = data
[(i
*4)+j
];
1468 tag
.uid
= (tag
.pages
[0][3] << 24 | tag
.pages
[0][2] << 16 | tag
.pages
[0][1] << 8 | tag
.pages
[0][0]);
1469 con0
= tag
.pages
[1][3];
1470 con1
= tag
.pages
[1][2];
1471 con2
= tag
.pages
[1][1];
1472 Dbprintf("UID: %X", tag
.uid
);
1473 Dbprintf("Hitag S simulation started");
1475 //0x01 plain mode - Reserved, CON2, CON1, CON0
1476 //0x01 auth mode - PWDH 0, CON2, CON1, CON0
1477 //0x02 auth mode - KEYH 1, KEYH 0, PWDL 1, PWDL 0
1478 //0x03 auth mode - KEYL 3, KEYL 2, KEYL 1, KEYL 0
1481 tag
.max_page
= 2048 / 32;
1482 if ((con0
& 0x2) == 0 && (con0
& 0x1) == 1)
1483 tag
.max_page
= 256 / 32;
1484 if ((con0
& 0x2) == 0 && (con0
& 0x1) == 0)
1485 tag
.max_page
= 32 / 32;
1488 tag
.auth
= ((con1
& 0x80) == 0x80) ? 1 : 0;
1489 tag
.TTFC
= ((con1
& 0x40) == 0x40) ? 1 : 0;
1490 //tag.TTFDR in response_bit[10] and response_bit[11]
1491 //tag.TTFM in response_bit[12] and response_bit[13]
1492 tag
.LCON
= ((con1
& 0x2) == 0x2) ? 1 : 0;
1493 tag
.LKP
= ((con1
& 0x1) == 0x1) ? 1 : 0;
1496 tag
.LCK7
= ((con2
& 0x80) == 0x80) ? 1 : 0;
1497 tag
.LCK6
= ((con2
& 0x40) == 0x40) ? 1 : 0;
1498 tag
.LCK5
= ((con2
& 0x20) == 0x20) ? 1 : 0;
1499 tag
.LCK4
= ((con2
& 0x10) == 0x10) ? 1 : 0;
1500 tag
.LCK3
= ((con2
& 0x8) == 0x8) ? 1 : 0;
1501 tag
.LCK2
= ((con2
& 0x4) == 0x4) ? 1 : 0;
1502 tag
.LCK1
= ((con2
& 0x2) == 0x2) ? 1 : 0;
1503 tag
.LCK0
= ((con2
& 0x1) == 0x1) ? 1 : 0;
1505 if (tag
.auth
== 1) {
1506 //TODO check if this working :D
1507 tag
.key
=(intptr_t)tag
.pages
[3];
1509 tag
.key
+=((tag
.pages
[2][0])<<8)+tag
.pages
[2][1];
1510 tag
.pwdl0
=tag
.pages
[2][3];
1511 tag
.pwdl1
=tag
.pages
[2][2];
1512 tag
.pwdh0
=tag
.pages
[1][0];
1515 // Set up simulator mode, frequency divisor which will drive the FPGA
1516 // and analog mux selection.
1517 FpgaDownloadAndGo(FPGA_BITSTREAM_LF
);
1518 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT
);
1519 FpgaSendCommand(FPGA_CMD_SET_DIVISOR
, 95); //125Khz
1520 SetAdcMuxFor(GPIO_MUXSEL_LOPKD
);
1523 // Configure output pin that is connected to the FPGA (for modulating)
1524 AT91C_BASE_PIOA
->PIO_OER
= GPIO_SSC_DOUT
;
1525 AT91C_BASE_PIOA
->PIO_PER
= GPIO_SSC_DOUT
;
1527 // Disable modulation at default, which means release resistance
1530 // Enable Peripheral Clock for TIMER_CLOCK0, used to measure exact timing before answering
1531 AT91C_BASE_PMC
->PMC_PCER
= (1 << AT91C_ID_TC0
);
1533 // Enable Peripheral Clock for TIMER_CLOCK1, used to capture edges of the reader frames
1534 AT91C_BASE_PMC
->PMC_PCER
= (1 << AT91C_ID_TC1
);
1535 AT91C_BASE_PIOA
->PIO_BSR
= GPIO_SSC_FRAME
;
1537 // Disable timer during configuration
1538 AT91C_BASE_TC1
->TC_CCR
= AT91C_TC_CLKDIS
;
1540 // Capture mode, default timer source = MCK/2 (TIMER_CLOCK1), TIOA is external trigger,
1541 // external trigger rising edge, load RA on rising edge of TIOA.
1542 AT91C_BASE_TC1
->TC_CMR
= AT91C_TC_CLKS_TIMER_DIV1_CLOCK
| AT91C_TC_ETRGEDG_RISING
| AT91C_TC_ABETRG
| AT91C_TC_LDRA_RISING
;
1544 // Reset the received frame, frame count and timing info
1545 memset(rx
, 0x00, sizeof(rx
));
1550 // Enable and reset counter
1551 AT91C_BASE_TC1
->TC_CCR
= AT91C_TC_CLKEN
| AT91C_TC_SWTRG
;
1553 while (!BUTTON_PRESS()) {
1557 // Receive frame, watch for at most T0*EOF periods
1559 while (AT91C_BASE_TC1
->TC_CV
< T0
* HITAG_T_EOF
) {
1560 // Check if rising edge in modulation is detected
1561 if (AT91C_BASE_TC1
->TC_SR
& AT91C_TC_LDRAS
) {
1562 // Retrieve the new timing values
1563 int ra
= (AT91C_BASE_TC1
->TC_RA
/ T0
) + overflow
;
1566 // Reset timer every frame, we have to capture the last edge for timing
1567 AT91C_BASE_TC0
->TC_CCR
= AT91C_TC_CLKEN
| AT91C_TC_SWTRG
;
1571 // Capture reader frame
1572 if (ra
>= HITAG_T_STOP
) {
1574 //DbpString("wierd0?");
1576 // Capture the T0 periods that have passed since last communication or field drop (reset)
1577 response
= (ra
- HITAG_T_LOW
);
1578 } else if (ra
>= HITAG_T_1_MIN
) {
1580 rx
[rxlen
/ 8] |= 1 << (7 - (rxlen
% 8));
1582 } else if (ra
>= HITAG_T_0_MIN
) {
1584 rx
[rxlen
/ 8] |= 0 << (7 - (rxlen
% 8));
1587 // Ignore wierd value, is to small to mean anything
1592 // Check if frame was captured
1596 if (!LogTraceHitag(rx
, rxlen
, response
, 0, true)) {
1597 DbpString("Trace full");
1602 // Disable timer 1 with external trigger to avoid triggers during our own modulation
1603 AT91C_BASE_TC1
->TC_CCR
= AT91C_TC_CLKDIS
;
1605 // Process the incoming frame (rx) and prepare the outgoing frame (tx)
1606 hitagS_handle_reader_command(rx
, rxlen
, tx
, &txlen
);
1608 // Wait for HITAG_T_WAIT_1 carrier periods after the last reader bit,
1609 // not that since the clock counts since the rising edge, but T_Wait1 is
1610 // with respect to the falling edge, we need to wait actually (T_Wait1 - T_Low)
1611 // periods. The gap time T_Low varies (4..10). All timer values are in
1612 // terms of T0 units
1613 while (AT91C_BASE_TC0
->TC_CV
< T0
* (HITAG_T_WAIT_1
- HITAG_T_LOW
)) { }
1615 // Send and store the tag answer (if there is any)
1617 // Transmit the tag frame
1618 hitag_tag_send_frame(tx
, txlen
);
1620 // Store the frame in the trace
1622 if (!LogTraceHitag(tx
, txlen
, 0, 0, false)) {
1623 DbpString("Trace full");
1629 // Enable and reset external trigger in timer for capturing future frames
1630 AT91C_BASE_TC1
->TC_CCR
= AT91C_TC_CLKEN
| AT91C_TC_SWTRG
;
1632 // Reset the received frame and response timing info
1633 memset(rx
, 0x00, sizeof(rx
));
1638 // Reset the frame length
1640 // Save the timer overflow, will be 0 when frame was received
1641 overflow
+= (AT91C_BASE_TC1
->TC_CV
/ T0
);
1642 // Reset the timer to restart while-loop that receives frames
1643 AT91C_BASE_TC1
->TC_CCR
= AT91C_TC_SWTRG
;
1645 Dbprintf("Hitag S simulation stopped");
1648 AT91C_BASE_TC1
->TC_CCR
= AT91C_TC_CLKDIS
;
1649 AT91C_BASE_TC0
->TC_CCR
= AT91C_TC_CLKDIS
;
1650 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF
);
1654 * Authenticates to the Tag with the given key or challenge.
1655 * If the key was given the password will be decrypted.
1656 * Reads every page of a hitag S transpoder.
1658 void ReadHitagSintern(hitag_function htf
, hitag_data
* htd
, stype tagMode
, int startPage
, bool readBlock
) {
1661 int sendNum
= startPage
;
1665 //int response_bit[200];
1666 //unsigned char mask = 1;
1669 byte_t rx
[HITAG_FRAME_LEN
];
1671 byte_t txbuf
[HITAG_FRAME_LEN
];
1675 int t_wait
= HITAG_T_WAIT_MAX
;
1677 bool bQuitTraceFull
= false;
1679 page_to_be_written
= 0;
1681 //read given key/challenge
1688 case 03: { //RHTS_CHALLENGE
1689 DbpString("Authenticating using nr,ar pair:");
1690 memcpy(NrAr_
,htd
->auth
.NrAr
,8);
1691 Dbhexdump(8,NrAr_
,false);
1692 NrAr
=NrAr_
[7] | ((uint64_t)NrAr_
[6]) << 8 | ((uint64_t)NrAr_
[5]) << 16 | ((uint64_t)NrAr_
[4]) << 24 | ((uint64_t)NrAr_
[3]) << 32 |
1693 ((uint64_t)NrAr_
[2]) << 40| ((uint64_t)NrAr_
[1]) << 48 | ((uint64_t)NrAr_
[0]) << 56;
1696 case 04: { //RHTS_KEY
1697 DbpString("Authenticating using key:");
1698 memcpy(key_
,htd
->crypto
.key
,6);
1699 Dbhexdump(6,key_
,false);
1700 key
=key_
[5] | ((uint64_t)key_
[4]) << 8 | ((uint64_t)key_
[3]) << 16 | ((uint64_t)key_
[2]) << 24 | ((uint64_t)key_
[1]) << 32 | ((uint64_t)key_
[0]) << 40;
1703 Dbprintf("Error , unknown function: %d",htf
);
1710 FpgaDownloadAndGo(FPGA_BITSTREAM_LF
);
1711 // Reset the return status
1712 bSuccessful
= false;
1714 // Clean up trace and prepare it for storing frames
1722 // Configure output and enable pin that is connected to the FPGA (for modulating)
1723 AT91C_BASE_PIOA
->PIO_OER
= GPIO_SSC_DOUT
;
1724 AT91C_BASE_PIOA
->PIO_PER
= GPIO_SSC_DOUT
;
1726 // Set fpga in edge detect with reader field, we can modulate as reader now
1727 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT
| FPGA_LF_EDGE_DETECT_READER_FIELD
);
1729 // Set Frequency divisor which will drive the FPGA and analog mux selection
1730 FpgaSendCommand(FPGA_CMD_SET_DIVISOR
, 95); //125Khz
1731 SetAdcMuxFor(GPIO_MUXSEL_LOPKD
);
1734 // Disable modulation at default, which means enable the field
1737 // Give it a bit of time for the resonant antenna to settle.
1740 // Enable Peripheral Clock for TIMER_CLOCK0, used to measure exact timing before answering
1741 AT91C_BASE_PMC
->PMC_PCER
= (1 << AT91C_ID_TC0
);
1743 // Enable Peripheral Clock for TIMER_CLOCK1, used to capture edges of the tag frames
1744 AT91C_BASE_PMC
->PMC_PCER
= (1 << AT91C_ID_TC1
);
1745 AT91C_BASE_PIOA
->PIO_BSR
= GPIO_SSC_FRAME
;
1747 // Disable timer during configuration
1748 AT91C_BASE_TC1
->TC_CCR
= AT91C_TC_CLKDIS
;
1750 // Capture mode, defaul timer source = MCK/2 (TIMER_CLOCK1), TIOA is external trigger,
1751 // external trigger rising edge, load RA on falling edge of TIOA.
1752 AT91C_BASE_TC1
->TC_CMR
= AT91C_TC_CLKS_TIMER_DIV1_CLOCK
| AT91C_TC_ETRGEDG_FALLING
| AT91C_TC_ABETRG
| AT91C_TC_LDRA_FALLING
;
1754 // Enable and reset counters
1755 AT91C_BASE_TC0
->TC_CCR
= AT91C_TC_CLKEN
| AT91C_TC_SWTRG
;
1756 AT91C_BASE_TC1
->TC_CCR
= AT91C_TC_CLKEN
| AT91C_TC_SWTRG
;
1758 // Reset the received frame, frame count and timing info
1765 while (!bStop
&& !BUTTON_PRESS()) {
1770 // Add transmitted frame to total count
1774 if (tag
.pstate
== READY
&& rxlen
< 1) {
1775 //skip logging starting auths if no response
1778 // Store the frame in the trace
1779 if (!LogTraceHitag(tx
, txlen
, HITAG_T_WAIT_2
, 0, true)) {
1780 if (bQuitTraceFull
) {
1781 DbpString("Trace full");
1791 // Check if frame was captured and store it
1795 if (!LogTraceHitag(rx
, rxlen
, response
, 0, false)) {
1796 DbpString("Trace full");
1797 if (bQuitTraceFull
) {
1806 // By default reset the transmission buffer
1811 Dbprintf("FRO %d rxlen: %d, pstate=%d, tstate=%d", frame_count
, rxlen
, (int)tag
.pstate
, (int)tag
.tstate
);
1815 //start authentication
1816 hitag_start_auth(tx
, &txlen
);
1817 } else if (tag
.pstate
!= SELECTED
) {
1818 if (hitagS_handle_tag_auth(htf
, key
,NrAr
,rx
, rxlen
, tx
, &txlen
) == -1) {
1819 Dbprintf("hitagS_handle_tag_auth - bStop = !false");
1826 if (readBlock
&& tag
.pstate
== SELECTED
&& (tag
.tstate
== READING_BLOCK
|| tag
.tstate
== NO_OP
) && rxlen
> 0) {
1827 i
= hitag_read_block(htf
, key
, rx
, &rxlen
, tx
, &txlen
, sendNum
);
1828 if (i
> 0) { sendNum
+=4; }
1829 if (sendNum
+4 >= tag
.max_page
) {
1832 } else if (!readBlock
&& tag
.pstate
== SELECTED
&& (tag
.tstate
== READING_PAGE
|| tag
.tstate
== NO_OP
) && rxlen
> 0) {
1833 i
= hitag_read_page(htf
, key
, rx
, &rxlen
, tx
, &txlen
, sendNum
);
1834 if (i
> 0) { sendNum
++; }
1835 if (sendNum
>= tag
.max_page
) {
1840 // Send and store the reader command
1841 // Disable timer 1 with external trigger to avoid triggers during our own modulation
1842 AT91C_BASE_TC1
->TC_CCR
= AT91C_TC_CLKDIS
;
1844 // Wait for HITAG_T_WAIT_2 carrier periods after the last tag bit before transmitting,
1845 // Since the clock counts since the last falling edge, a 'one' means that the
1846 // falling edge occured halfway the period. with respect to this falling edge,
1847 // we need to wait (T_Wait2 + half_tag_period) when the last was a 'one'.
1848 // All timer values are in terms of T0 units
1850 while (AT91C_BASE_TC0
->TC_CV
< T0
* (t_wait
+ (HITAG_T_TAG_HALF_PERIOD
* lastbit
))) { }
1852 // Transmit the reader frame
1853 hitag_reader_send_frame(tx
, txlen
);
1856 // Enable and reset external trigger in timer for capturing future frames
1857 AT91C_BASE_TC1
->TC_CCR
= AT91C_TC_CLKEN
| AT91C_TC_SWTRG
;
1860 // Reset values for receiving frames
1861 memset(rx
, 0x00, sizeof(rx
));
1866 // get tag id in anti-collision mode (proprietary data format, so switch off manchester and read at double the data rate, for 4 x the data bits)
1867 hitag_receive_frame(rx
, &rxlen
, &response
);
1872 AT91C_BASE_TC1
->TC_CCR
= AT91C_TC_CLKDIS
;
1873 AT91C_BASE_TC0
->TC_CCR
= AT91C_TC_CLKDIS
;
1874 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF
);
1875 cmd_send(CMD_ACK
, bSuccessful
, 0, 0, 0, 0);
1878 void ReadHitagSCmd(hitag_function htf
, hitag_data
* htd
, uint64_t startPage
, uint64_t tagMode
, bool readBlock
) {
1880 Dbprintf("ReadHitagS in mode=ADVANCED, blockRead=%d, startPage=%d", readBlock
, startPage
);
1881 ReadHitagSintern(htf
, htd
, ADVANCED
, (int)startPage
, readBlock
);
1882 } else if (tagMode
== 2) {
1883 Dbprintf("ReadHitagS in mode=FAST_ADVANCED, blockRead=%d, startPage=%d", readBlock
, startPage
);
1884 ReadHitagSintern(htf
, htd
, FAST_ADVANCED
, (int)startPage
, readBlock
);
1886 Dbprintf("ReadHitagS in mode=STANDARD, blockRead=%d, startPage=%d", readBlock
, startPage
);
1887 ReadHitagSintern(htf
, htd
, STANDARD
, (int)startPage
, readBlock
);
1894 * Authenticates to the Tag with the given Key or Challenge.
1895 * Writes the given 32Bit data into page_
1897 void WritePageHitagS(hitag_function htf
, hitag_data
* htd
,int page_
) {
1900 byte_t rx
[HITAG_FRAME_LEN
];
1902 byte_t txbuf
[HITAG_FRAME_LEN
];
1906 int t_wait
= HITAG_T_WAIT_MAX
;
1908 bool bQuitTraceFull
= false;
1911 byte_t data
[4]= {0,0,0,0};
1913 //read given key/challenge, the page and the data
1919 case 03: { //WHTS_CHALLENGE
1920 memcpy(data
,htd
->auth
.data
,4);
1921 DbpString("Authenticating using nr,ar pair:");
1922 memcpy(NrAr_
,htd
->auth
.NrAr
,8);
1923 Dbhexdump(8,NrAr_
,false);
1924 NrAr
=NrAr_
[7] | ((uint64_t)NrAr_
[6]) << 8 | ((uint64_t)NrAr_
[5]) << 16 | ((uint64_t)NrAr_
[4]) << 24 | ((uint64_t)NrAr_
[3]) << 32 |
1925 ((uint64_t)NrAr_
[2]) << 40| ((uint64_t)NrAr_
[1]) << 48 | ((uint64_t)NrAr_
[0]) << 56;
1927 case 04: { //WHTS_KEY
1928 memcpy(data
,htd
->crypto
.data
,4);
1929 DbpString("Authenticating using key:");
1930 memcpy(key_
,htd
->crypto
.key
,6);
1931 Dbhexdump(6,key_
,false);
1932 key
=key_
[5] | ((uint64_t)key_
[4]) << 8 | ((uint64_t)key_
[3]) << 16 | ((uint64_t)key_
[2]) << 24 | ((uint64_t)key_
[1]) << 32 | ((uint64_t)key_
[0]) << 40;
1935 Dbprintf("Error , unknown function: %d",htf
);
1940 Dbprintf("Page: %d",page_
);
1941 Dbprintf("DATA: %02X %02X %02X %02X", data
[0], data
[1], data
[2], data
[3]);
1942 FpgaDownloadAndGo(FPGA_BITSTREAM_LF
);
1943 // Reset the return status
1944 bSuccessful
= false;
1949 // Clean up trace and prepare it for storing frames
1957 // Configure output and enable pin that is connected to the FPGA (for modulating)
1958 AT91C_BASE_PIOA
->PIO_OER
= GPIO_SSC_DOUT
;
1959 AT91C_BASE_PIOA
->PIO_PER
= GPIO_SSC_DOUT
;
1961 // Set fpga in edge detect with reader field, we can modulate as reader now
1962 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT
| FPGA_LF_EDGE_DETECT_READER_FIELD
);
1964 // Set Frequency divisor which will drive the FPGA and analog mux selection
1965 FpgaSendCommand(FPGA_CMD_SET_DIVISOR
, 95); //125Khz
1966 SetAdcMuxFor(GPIO_MUXSEL_LOPKD
);
1969 // Disable modulation at default, which means enable the field
1972 // Give it a bit of time for the resonant antenna to settle.
1975 // Enable Peripheral Clock for TIMER_CLOCK0, used to measure exact timing before answering
1976 AT91C_BASE_PMC
->PMC_PCER
= (1 << AT91C_ID_TC0
);
1978 // Enable Peripheral Clock for TIMER_CLOCK1, used to capture edges of the tag frames
1979 AT91C_BASE_PMC
->PMC_PCER
= (1 << AT91C_ID_TC1
);
1980 AT91C_BASE_PIOA
->PIO_BSR
= GPIO_SSC_FRAME
;
1982 // Disable timer during configuration
1983 AT91C_BASE_TC1
->TC_CCR
= AT91C_TC_CLKDIS
;
1985 // Capture mode, defaul timer source = MCK/2 (TIMER_CLOCK1), TIOA is external trigger,
1986 // external trigger rising edge, load RA on falling edge of TIOA.
1987 AT91C_BASE_TC1
->TC_CMR
= AT91C_TC_CLKS_TIMER_DIV1_CLOCK
1988 | AT91C_TC_ETRGEDG_FALLING
| AT91C_TC_ABETRG
1989 | AT91C_TC_LDRA_FALLING
;
1991 // Enable and reset counters
1992 AT91C_BASE_TC0
->TC_CCR
= AT91C_TC_CLKEN
| AT91C_TC_SWTRG
;
1993 AT91C_BASE_TC1
->TC_CCR
= AT91C_TC_CLKEN
| AT91C_TC_SWTRG
;
1995 // Reset the received frame, frame count and timing info
2002 while (!bStop
&& !BUTTON_PRESS()) {
2006 // Check if frame was captured and store it
2010 if (!LogTraceHitag(rx
, rxlen
, response
, 0, false)) {
2011 DbpString("Trace full");
2012 if (bQuitTraceFull
) {
2021 //check for valid input
2024 Dbprintf("usage: lf hitag writer [03 | 04] [CHALLENGE | KEY] [page] [byte0] [byte1] [byte2] [byte3]");
2029 // By default reset the transmission buffer
2033 if (rxlen
== 0 && tag
.tstate
== WRITING_PAGE_ACK
) {
2034 //no write access on this page
2035 Dbprintf("no write access on page %d", page_
);
2037 } else if (rxlen
== 0 && tag
.tstate
!= WRITING_PAGE_DATA
) {
2038 //start the authetication
2039 //tag.mode = ADVANCED;
2040 tag
.mode
= STANDARD
;
2041 hitag_start_auth(tx
, &txlen
);
2043 } else if (tag
.pstate
!= SELECTED
) {
2044 //try to authenticate with the given key or challenge
2045 if (hitagS_handle_tag_auth(htf
,key
,NrAr
,rx
, rxlen
, tx
, &txlen
) == -1) {
2051 if (tag
.pstate
== SELECTED
&& tag
.tstate
== NO_OP
&& rxlen
> 0) {
2052 //check if the given page exists
2053 if (page
> tag
.max_page
) {
2054 Dbprintf("page number too big");
2057 //ask Tag for write permission
2058 tag
.tstate
= WRITING_PAGE_ACK
;
2061 tx
[0] = 0x90 + (page
/ 16);
2062 calc_crc(&crc
, tx
[0], 8);
2063 calc_crc(&crc
, 0x00 + ((page
% 16) * 16), 4);
2064 tx
[1] = 0x00 + ((page
% 16) * 16) + (crc
/ 16);
2065 tx
[2] = 0x00 + (crc
% 16) * 16;
2066 } else if (tag
.pstate
== SELECTED
&& tag
.tstate
== WRITING_PAGE_ACK
2067 && rxlen
== 2 && rx
[0] == 0x40) {
2068 //ACK recieved to write the page. send data
2069 tag
.tstate
= WRITING_PAGE_DATA
;
2072 calc_crc(&crc
, data
[3], 8);
2073 calc_crc(&crc
, data
[2], 8);
2074 calc_crc(&crc
, data
[1], 8);
2075 calc_crc(&crc
, data
[0], 8);
2081 } else if (tag
.pstate
== SELECTED
&& tag
.tstate
== WRITING_PAGE_DATA
2082 && rxlen
== 2 && rx
[0] == 0x40) {
2084 Dbprintf("Successful!");
2088 // Send and store the reader command
2089 // Disable timer 1 with external trigger to avoid triggers during our own modulation
2090 AT91C_BASE_TC1
->TC_CCR
= AT91C_TC_CLKDIS
;
2092 // Wait for HITAG_T_WAIT_2 carrier periods after the last tag bit before transmitting,
2093 // Since the clock counts since the last falling edge, a 'one' means that the
2094 // falling edge occured halfway the period. with respect to this falling edge,
2095 // we need to wait (T_Wait2 + half_tag_period) when the last was a 'one'.
2096 // All timer values are in terms of T0 units
2098 while (AT91C_BASE_TC0
->TC_CV
2099 < T0
* (t_wait
+ (HITAG_T_TAG_HALF_PERIOD
* lastbit
)))
2102 // Transmit the reader frame
2103 hitag_reader_send_frame(tx
, txlen
);
2105 // Enable and reset external trigger in timer for capturing future frames
2106 AT91C_BASE_TC1
->TC_CCR
= AT91C_TC_CLKEN
| AT91C_TC_SWTRG
;
2108 // Add transmitted frame to total count
2112 // Store the frame in the trace
2113 if (!LogTraceHitag(tx
, txlen
, HITAG_T_WAIT_2
, 0, true)) {
2114 if (bQuitTraceFull
) {
2115 DbpString("Trace full");
2124 // Reset values for receiving frames
2125 memset(rx
, 0x00, sizeof(rx
));
2130 hitag_receive_frame(rx
, &rxlen
, &response
);
2135 AT91C_BASE_TC1
->TC_CCR
= AT91C_TC_CLKDIS
;
2136 AT91C_BASE_TC0
->TC_CCR
= AT91C_TC_CLKDIS
;
2137 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF
);
2138 cmd_send(CMD_ACK
, bSuccessful
, 0, 0, 0, 0);
2143 * Tries to authenticate to a Hitag S Transponder with the given challenges from a .cc file.
2144 * Displays all Challenges that failed.
2145 * When collecting Challenges to break the key it is possible that some data
2146 * is not received correctly due to Antenna problems. This function
2147 * detects these challenges.
2149 void check_challenges_cmd(bool file_given
, byte_t
* data
, uint64_t tagMode
) {
2154 byte_t rx
[HITAG_FRAME_LEN
];
2155 byte_t unlocker
[60][8];
2158 byte_t txbuf
[HITAG_FRAME_LEN
];
2162 int t_wait
= HITAG_T_WAIT_MAX
;
2165 bool bQuitTraceFull
= false;
2166 int response_bit
[200];
2167 unsigned char mask
= 1;
2168 unsigned char uid
[32];
2172 Dbprintf("check_challenges in mode=ADVANCED");
2173 tag
.mode
= ADVANCED
;
2174 } else if (tagMode
== 2) {
2175 Dbprintf("check_challenges in mode=FAST_ADVANCED");
2176 tag
.mode
= FAST_ADVANCED
;
2178 Dbprintf("check_challenges in mode=STANDARD");
2179 tag
.mode
= STANDARD
;
2183 FpgaDownloadAndGo(FPGA_BITSTREAM_LF
);
2184 // Reset the return status
2185 bSuccessful
= false;
2187 // Clean up trace and prepare it for storing frames
2195 // Configure output and enable pin that is connected to the FPGA (for modulating)
2196 AT91C_BASE_PIOA
->PIO_OER
= GPIO_SSC_DOUT
;
2197 AT91C_BASE_PIOA
->PIO_PER
= GPIO_SSC_DOUT
;
2199 // Set fpga in edge detect with reader field, we can modulate as reader now
2201 FPGA_MAJOR_MODE_LF_EDGE_DETECT
| FPGA_LF_EDGE_DETECT_READER_FIELD
);
2203 // Set Frequency divisor which will drive the FPGA and analog mux selection
2204 FpgaSendCommand(FPGA_CMD_SET_DIVISOR
, 95); //125Khz
2205 SetAdcMuxFor(GPIO_MUXSEL_LOPKD
);
2208 // Disable modulation at default, which means enable the field
2211 // Give it a bit of time for the resonant antenna to settle.
2214 // Enable Peripheral Clock for TIMER_CLOCK0, used to measure exact timing before answering
2215 AT91C_BASE_PMC
->PMC_PCER
= (1 << AT91C_ID_TC0
);
2217 // Enable Peripheral Clock for TIMER_CLOCK1, used to capture edges of the tag frames
2218 AT91C_BASE_PMC
->PMC_PCER
= (1 << AT91C_ID_TC1
);
2219 AT91C_BASE_PIOA
->PIO_BSR
= GPIO_SSC_FRAME
;
2221 // Disable timer during configuration
2222 AT91C_BASE_TC1
->TC_CCR
= AT91C_TC_CLKDIS
;
2224 // Capture mode, defaul timer source = MCK/2 (TIMER_CLOCK1), TIOA is external trigger,
2225 // external trigger rising edge, load RA on falling edge of TIOA.
2226 AT91C_BASE_TC1
->TC_CMR
= AT91C_TC_CLKS_TIMER_DIV1_CLOCK
| AT91C_TC_ETRGEDG_FALLING
| AT91C_TC_ABETRG
| AT91C_TC_LDRA_FALLING
;
2228 // Enable and reset counters
2229 AT91C_BASE_TC0
->TC_CCR
= AT91C_TC_CLKEN
| AT91C_TC_SWTRG
;
2230 AT91C_BASE_TC1
->TC_CCR
= AT91C_TC_CLKEN
| AT91C_TC_SWTRG
;
2232 // Reset the received frame, frame count and timing info
2241 DbpString("Loading challenges...");
2242 memcpy((byte_t
*)unlocker
,data
,60*8);
2245 while (file_given
&& !bStop
&& !BUTTON_PRESS()) {
2249 // Check if frame was captured and store it
2253 if (!LogTraceHitag(rx
, rxlen
, response
, 0, false)) {
2254 DbpString("Trace full");
2255 if (bQuitTraceFull
) {
2269 Dbprintf("Challenge failed: %02X %02X %02X %02X %02X %02X %02X %02X",
2270 unlocker
[u1
- 1][0], unlocker
[u1
- 1][1],
2271 unlocker
[u1
- 1][2], unlocker
[u1
- 1][3],
2272 unlocker
[u1
- 1][4], unlocker
[u1
- 1][5],
2273 unlocker
[u1
- 1][6], unlocker
[u1
- 1][7]);
2276 hitag_start_auth(tx
, &txlen
);
2277 } else if (rxlen
>= 32 && STATE
== 0) {
2280 for (i
= 0; i
< 10; i
++) {
2281 for (j
= 0; j
< 8; j
++) {
2282 response_bit
[z
] = 0;
2283 if ((rx
[i
] & ((mask
<< 7) >> j
)) != 0)
2284 response_bit
[z
] = 1;
2288 for (i
= 0; i
< 32; i
++) {
2289 uid
[i
] = response_bit
[i
];
2292 uid_byte
[0] = (uid
[0] << 7) | (uid
[1] << 6) | (uid
[2] << 5)
2293 | (uid
[3] << 4) | (uid
[4] << 3) | (uid
[5] << 2)
2294 | (uid
[6] << 1) | uid
[7];
2295 uid_byte
[1] = (uid
[8] << 7) | (uid
[9] << 6) | (uid
[10] << 5)
2296 | (uid
[11] << 4) | (uid
[12] << 3) | (uid
[13] << 2)
2297 | (uid
[14] << 1) | uid
[15];
2298 uid_byte
[2] = (uid
[16] << 7) | (uid
[17] << 6) | (uid
[18] << 5)
2299 | (uid
[19] << 4) | (uid
[20] << 3) | (uid
[21] << 2)
2300 | (uid
[22] << 1) | uid
[23];
2301 uid_byte
[3] = (uid
[24] << 7) | (uid
[25] << 6) | (uid
[26] << 5)
2302 | (uid
[27] << 4) | (uid
[28] << 3) | (uid
[29] << 2)
2303 | (uid
[30] << 1) | uid
[31];
2304 //Dbhexdump(10, rx, rxlen);
2308 calc_crc(&crc
, 0x00, 5);
2309 calc_crc(&crc
, uid_byte
[0], 8);
2310 calc_crc(&crc
, uid_byte
[1], 8);
2311 calc_crc(&crc
, uid_byte
[2], 8);
2312 calc_crc(&crc
, uid_byte
[3], 8);
2313 for (i
= 0; i
< 100; i
++) {
2314 response_bit
[i
] = 0;
2316 for (i
= 0; i
< 5; i
++) {
2317 response_bit
[i
] = 0;
2319 for (i
= 5; i
< 37; i
++) {
2320 response_bit
[i
] = uid
[i
- 5];
2322 for (j
= 0; j
< 8; j
++) {
2323 response_bit
[i
] = 0;
2324 if ((crc
& ((mask
<< 7) >> j
)) != 0)
2325 response_bit
[i
] = 1;
2329 for (i
= 0; i
< 6; i
++) {
2330 tx
[i
] = (response_bit
[k
] << 7) | (response_bit
[k
+ 1] << 6)
2331 | (response_bit
[k
+ 2] << 5)
2332 | (response_bit
[k
+ 3] << 4)
2333 | (response_bit
[k
+ 4] << 3)
2334 | (response_bit
[k
+ 5] << 2)
2335 | (response_bit
[k
+ 6] << 1) | response_bit
[k
+ 7];
2341 } else if (STATE
== 1 && rxlen
> 24) {
2342 //received configuration
2345 for (i
= 0; i
< 6; i
++) {
2346 for (j
= 0; j
< 8; j
++) {
2347 response_bit
[z
] = 0;
2348 if ((rx
[i
] & ((mask
<< 7) >> j
)) != 0)
2349 response_bit
[z
] = 1;
2355 if (u1
>= (sizeof(unlocker
) / sizeof(unlocker
[0])))
2357 for (i
= 0; i
< 8; i
++)
2358 tx
[i
] = unlocker
[u1
][i
];
2361 tag
.pstate
= SELECTED
;
2362 } else if (STATE
== 2 && rxlen
>= 32) {
2366 // Send and store the reader command
2367 // Disable timer 1 with external trigger to avoid triggers during our own modulation
2368 AT91C_BASE_TC1
->TC_CCR
= AT91C_TC_CLKDIS
;
2370 // Wait for HITAG_T_WAIT_2 carrier periods after the last tag bit before transmitting,
2371 // Since the clock counts since the last falling edge, a 'one' means that the
2372 // falling edge occured halfway the period. with respect to this falling edge,
2373 // we need to wait (T_Wait2 + half_tag_period) when the last was a 'one'.
2374 // All timer values are in terms of T0 units
2375 while (AT91C_BASE_TC0
->TC_CV
< T0
* (t_wait
+ (HITAG_T_TAG_HALF_PERIOD
* lastbit
))) { }
2377 // Transmit the reader frame
2378 hitag_reader_send_frame(tx
, txlen
);
2380 // Enable and reset external trigger in timer for capturing future frames
2381 AT91C_BASE_TC1
->TC_CCR
= AT91C_TC_CLKEN
| AT91C_TC_SWTRG
;
2383 // Add transmitted frame to total count
2387 // Store the frame in the trace
2388 if (!LogTraceHitag(tx
, txlen
, HITAG_T_WAIT_2
, 0, true)) {
2389 if (bQuitTraceFull
) {
2390 DbpString("Trace full");
2399 // Reset values for receiving frames
2400 memset(rx
, 0x00, sizeof(rx
));
2405 hitag_receive_frame(rx
, &rxlen
, &response
);
2409 AT91C_BASE_TC1
->TC_CCR
= AT91C_TC_CLKDIS
;
2410 AT91C_BASE_TC0
->TC_CCR
= AT91C_TC_CLKDIS
;
2411 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF
);
2412 cmd_send(CMD_ACK
, bSuccessful
, 0, 0, 0, 0);
2416 Backward compatibility
2418 void check_challenges(bool file_given
, byte_t
* data
) {
2419 check_challenges_cmd(file_given
, data
, 1);
2422 void ReadHitagS(hitag_function htf
, hitag_data
* htd
) {
2423 ReadHitagSintern(htf
, htd
, ADVANCED
, 0, false);