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[proxmark3-svn] / armsrc / iso14443a.c
1 //-----------------------------------------------------------------------------
2 // Merlok - June 2011, 2012
3 // Gerhard de Koning Gans - May 2008
4 // Hagen Fritsch - June 2010
5 //
6 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
7 // at your option, any later version. See the LICENSE.txt file for the text of
8 // the license.
9 //-----------------------------------------------------------------------------
10 // Routines to support ISO 14443 type A.
11 //-----------------------------------------------------------------------------
12
13 #include "proxmark3.h"
14 #include "apps.h"
15 #include "util.h"
16 #include "string.h"
17 #include "cmd.h"
18
19 #include "iso14443crc.h"
20 #include "iso14443a.h"
21 #include "crapto1.h"
22 #include "mifareutil.h"
23 #include "BigBuf.h"
24 static uint32_t iso14a_timeout;
25 int rsamples = 0;
26 uint8_t trigger = 0;
27 // the block number for the ISO14443-4 PCB
28 static uint8_t iso14_pcb_blocknum = 0;
29
30 //
31 // ISO14443 timing:
32 //
33 // minimum time between the start bits of consecutive transfers from reader to tag: 7000 carrier (13.56Mhz) cycles
34 #define REQUEST_GUARD_TIME (7000/16 + 1)
35 // minimum time between last modulation of tag and next start bit from reader to tag: 1172 carrier cycles
36 #define FRAME_DELAY_TIME_PICC_TO_PCD (1172/16 + 1)
37 // bool LastCommandWasRequest = FALSE;
38
39 //
40 // Total delays including SSC-Transfers between ARM and FPGA. These are in carrier clock cycles (1/13,56MHz)
41 //
42 // When the PM acts as reader and is receiving tag data, it takes
43 // 3 ticks delay in the AD converter
44 // 16 ticks until the modulation detector completes and sets curbit
45 // 8 ticks until bit_to_arm is assigned from curbit
46 // 8*16 ticks for the transfer from FPGA to ARM
47 // 4*16 ticks until we measure the time
48 // - 8*16 ticks because we measure the time of the previous transfer
49 #define DELAY_AIR2ARM_AS_READER (3 + 16 + 8 + 8*16 + 4*16 - 8*16)
50
51 // When the PM acts as a reader and is sending, it takes
52 // 4*16 ticks until we can write data to the sending hold register
53 // 8*16 ticks until the SHR is transferred to the Sending Shift Register
54 // 8 ticks until the first transfer starts
55 // 8 ticks later the FPGA samples the data
56 // 1 tick to assign mod_sig_coil
57 #define DELAY_ARM2AIR_AS_READER (4*16 + 8*16 + 8 + 8 + 1)
58
59 // When the PM acts as tag and is receiving it takes
60 // 2 ticks delay in the RF part (for the first falling edge),
61 // 3 ticks for the A/D conversion,
62 // 8 ticks on average until the start of the SSC transfer,
63 // 8 ticks until the SSC samples the first data
64 // 7*16 ticks to complete the transfer from FPGA to ARM
65 // 8 ticks until the next ssp_clk rising edge
66 // 4*16 ticks until we measure the time
67 // - 8*16 ticks because we measure the time of the previous transfer
68 #define DELAY_AIR2ARM_AS_TAG (2 + 3 + 8 + 8 + 7*16 + 8 + 4*16 - 8*16)
69
70 // The FPGA will report its internal sending delay in
71 uint16_t FpgaSendQueueDelay;
72 // the 5 first bits are the number of bits buffered in mod_sig_buf
73 // the last three bits are the remaining ticks/2 after the mod_sig_buf shift
74 #define DELAY_FPGA_QUEUE (FpgaSendQueueDelay<<1)
75
76 // When the PM acts as tag and is sending, it takes
77 // 4*16 ticks until we can write data to the sending hold register
78 // 8*16 ticks until the SHR is transferred to the Sending Shift Register
79 // 8 ticks until the first transfer starts
80 // 8 ticks later the FPGA samples the data
81 // + a varying number of ticks in the FPGA Delay Queue (mod_sig_buf)
82 // + 1 tick to assign mod_sig_coil
83 #define DELAY_ARM2AIR_AS_TAG (4*16 + 8*16 + 8 + 8 + DELAY_FPGA_QUEUE + 1)
84
85 // When the PM acts as sniffer and is receiving tag data, it takes
86 // 3 ticks A/D conversion
87 // 14 ticks to complete the modulation detection
88 // 8 ticks (on average) until the result is stored in to_arm
89 // + the delays in transferring data - which is the same for
90 // sniffing reader and tag data and therefore not relevant
91 #define DELAY_TAG_AIR2ARM_AS_SNIFFER (3 + 14 + 8)
92
93 // When the PM acts as sniffer and is receiving reader data, it takes
94 // 2 ticks delay in analogue RF receiver (for the falling edge of the
95 // start bit, which marks the start of the communication)
96 // 3 ticks A/D conversion
97 // 8 ticks on average until the data is stored in to_arm.
98 // + the delays in transferring data - which is the same for
99 // sniffing reader and tag data and therefore not relevant
100 #define DELAY_READER_AIR2ARM_AS_SNIFFER (2 + 3 + 8)
101
102 //variables used for timing purposes:
103 //these are in ssp_clk cycles:
104 static uint32_t NextTransferTime;
105 static uint32_t LastTimeProxToAirStart;
106 static uint32_t LastProxToAirDuration;
107
108
109
110 // CARD TO READER - manchester
111 // Sequence D: 11110000 modulation with subcarrier during first half
112 // Sequence E: 00001111 modulation with subcarrier during second half
113 // Sequence F: 00000000 no modulation with subcarrier
114 // READER TO CARD - miller
115 // Sequence X: 00001100 drop after half a period
116 // Sequence Y: 00000000 no drop
117 // Sequence Z: 11000000 drop at start
118 #define SEC_D 0xf0
119 #define SEC_E 0x0f
120 #define SEC_F 0x00
121 #define SEC_X 0x0c
122 #define SEC_Y 0x00
123 #define SEC_Z 0xc0
124
125 const uint8_t OddByteParity[256] = {
126 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
127 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
128 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
129 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
130 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
131 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
132 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
133 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
134 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
135 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
136 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
137 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
138 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
139 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
140 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
141 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1
142 };
143
144
145 void iso14a_set_trigger(bool enable) {
146 trigger = enable;
147 }
148
149
150 void iso14a_set_timeout(uint32_t timeout) {
151 iso14a_timeout = timeout;
152 if(MF_DBGLEVEL >= 3) Dbprintf("ISO14443A Timeout set to %ld (%dms)", iso14a_timeout, iso14a_timeout / 106);
153 }
154
155
156 void iso14a_set_ATS_timeout(uint8_t *ats) {
157
158 uint8_t tb1;
159 uint8_t fwi;
160 uint32_t fwt;
161
162 if (ats[0] > 1) { // there is a format byte T0
163 if ((ats[1] & 0x20) == 0x20) { // there is an interface byte TB(1)
164 if ((ats[1] & 0x10) == 0x10) { // there is an interface byte TA(1) preceding TB(1)
165 tb1 = ats[3];
166 } else {
167 tb1 = ats[2];
168 }
169 fwi = (tb1 & 0xf0) >> 4; // frame waiting indicator (FWI)
170 fwt = 256 * 16 * (1 << fwi); // frame waiting time (FWT) in 1/fc
171
172 iso14a_set_timeout(fwt/(8*16));
173 }
174 }
175 }
176
177
178 //-----------------------------------------------------------------------------
179 // Generate the parity value for a byte sequence
180 //
181 //-----------------------------------------------------------------------------
182 byte_t oddparity (const byte_t bt)
183 {
184 return OddByteParity[bt];
185 }
186
187 void GetParity(const uint8_t *pbtCmd, uint16_t iLen, uint8_t *par)
188 {
189 uint16_t paritybit_cnt = 0;
190 uint16_t paritybyte_cnt = 0;
191 uint8_t parityBits = 0;
192
193 for (uint16_t i = 0; i < iLen; i++) {
194 // Generate the parity bits
195 parityBits |= ((OddByteParity[pbtCmd[i]]) << (7-paritybit_cnt));
196 if (paritybit_cnt == 7) {
197 par[paritybyte_cnt] = parityBits; // save 8 Bits parity
198 parityBits = 0; // and advance to next Parity Byte
199 paritybyte_cnt++;
200 paritybit_cnt = 0;
201 } else {
202 paritybit_cnt++;
203 }
204 }
205
206 // save remaining parity bits
207 par[paritybyte_cnt] = parityBits;
208
209 }
210
211 void AppendCrc14443a(uint8_t* data, int len)
212 {
213 ComputeCrc14443(CRC_14443_A,data,len,data+len,data+len+1);
214 }
215
216 //=============================================================================
217 // ISO 14443 Type A - Miller decoder
218 //=============================================================================
219 // Basics:
220 // This decoder is used when the PM3 acts as a tag.
221 // The reader will generate "pauses" by temporarily switching of the field.
222 // At the PM3 antenna we will therefore measure a modulated antenna voltage.
223 // The FPGA does a comparison with a threshold and would deliver e.g.:
224 // ........ 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 .......
225 // The Miller decoder needs to identify the following sequences:
226 // 2 (or 3) ticks pause followed by 6 (or 5) ticks unmodulated: pause at beginning - Sequence Z ("start of communication" or a "0")
227 // 8 ticks without a modulation: no pause - Sequence Y (a "0" or "end of communication" or "no information")
228 // 4 ticks unmodulated followed by 2 (or 3) ticks pause: pause in second half - Sequence X (a "1")
229 // Note 1: the bitstream may start at any time. We therefore need to sync.
230 // Note 2: the interpretation of Sequence Y and Z depends on the preceding sequence.
231 //-----------------------------------------------------------------------------
232 static tUart Uart;
233
234 // Lookup-Table to decide if 4 raw bits are a modulation.
235 // We accept two or three consecutive "0" in any position with the rest "1"
236 const bool Mod_Miller_LUT[] = {
237 TRUE, TRUE, FALSE, TRUE, FALSE, FALSE, FALSE, FALSE,
238 TRUE, TRUE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE
239 };
240 #define IsMillerModulationNibble1(b) (Mod_Miller_LUT[(b & 0x00F0) >> 4])
241 #define IsMillerModulationNibble2(b) (Mod_Miller_LUT[(b & 0x000F)])
242
243 void UartReset()
244 {
245 Uart.state = STATE_UNSYNCD;
246 Uart.bitCount = 0;
247 Uart.len = 0; // number of decoded data bytes
248 Uart.parityLen = 0; // number of decoded parity bytes
249 Uart.shiftReg = 0; // shiftreg to hold decoded data bits
250 Uart.parityBits = 0; // holds 8 parity bits
251 Uart.fourBits = 0x00000000; // buffer for 4 Bits
252 Uart.startTime = 0;
253 Uart.endTime = 0;
254 }
255
256 void UartInit(uint8_t *data, uint8_t *parity)
257 {
258 Uart.output = data;
259 Uart.parity = parity;
260 UartReset();
261 }
262
263 // use parameter non_real_time to provide a timestamp. Set to 0 if the decoder should measure real time
264 static RAMFUNC bool MillerDecoding(uint8_t bit, uint32_t non_real_time)
265 {
266
267 Uart.fourBits = (Uart.fourBits << 8) | bit;
268
269 if (Uart.state == STATE_UNSYNCD) { // not yet synced
270
271 Uart.syncBit = 9999; // not set
272 // we look for a ...xxxx1111111100x11111xxxxxx pattern
273 // (unmodulated, followed by the start bit = 8 '1's followed by 2 '0's, eventually followed by another '0', followed by 5 '1's)
274 #define ISO14443A_STARTBIT_MASK 0x007FEF80 // mask is 00000000 01111111 11101111 10000000
275 #define ISO14443A_STARTBIT_PATTERN 0x007F8F80 // pattern is 00000000 01111111 10001111 10000000
276 if ((Uart.fourBits & ISO14443A_STARTBIT_MASK) >> 0 == ISO14443A_STARTBIT_PATTERN >> 0) Uart.syncBit = 7;
277 else if ((Uart.fourBits & ISO14443A_STARTBIT_MASK) >> 1 == ISO14443A_STARTBIT_PATTERN >> 1) Uart.syncBit = 6;
278 else if ((Uart.fourBits & ISO14443A_STARTBIT_MASK) >> 2 == ISO14443A_STARTBIT_PATTERN >> 2) Uart.syncBit = 5;
279 else if ((Uart.fourBits & ISO14443A_STARTBIT_MASK) >> 3 == ISO14443A_STARTBIT_PATTERN >> 3) Uart.syncBit = 4;
280 else if ((Uart.fourBits & ISO14443A_STARTBIT_MASK) >> 4 == ISO14443A_STARTBIT_PATTERN >> 4) Uart.syncBit = 3;
281 else if ((Uart.fourBits & ISO14443A_STARTBIT_MASK) >> 5 == ISO14443A_STARTBIT_PATTERN >> 5) Uart.syncBit = 2;
282 else if ((Uart.fourBits & ISO14443A_STARTBIT_MASK) >> 6 == ISO14443A_STARTBIT_PATTERN >> 6) Uart.syncBit = 1;
283 else if ((Uart.fourBits & ISO14443A_STARTBIT_MASK) >> 7 == ISO14443A_STARTBIT_PATTERN >> 7) Uart.syncBit = 0;
284 if (Uart.syncBit != 9999) { // found a sync bit
285 Uart.startTime = non_real_time?non_real_time:(GetCountSspClk() & 0xfffffff8);
286 Uart.startTime -= Uart.syncBit;
287 Uart.endTime = Uart.startTime;
288 Uart.state = STATE_START_OF_COMMUNICATION;
289 }
290
291 } else {
292
293 if (IsMillerModulationNibble1(Uart.fourBits >> Uart.syncBit)) {
294 if (IsMillerModulationNibble2(Uart.fourBits >> Uart.syncBit)) { // Modulation in both halves - error
295 UartReset();
296 } else { // Modulation in first half = Sequence Z = logic "0"
297 if (Uart.state == STATE_MILLER_X) { // error - must not follow after X
298 UartReset();
299 } else {
300 Uart.bitCount++;
301 Uart.shiftReg = (Uart.shiftReg >> 1); // add a 0 to the shiftreg
302 Uart.state = STATE_MILLER_Z;
303 Uart.endTime = Uart.startTime + 8*(9*Uart.len + Uart.bitCount + 1) - 6;
304 if(Uart.bitCount >= 9) { // if we decoded a full byte (including parity)
305 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff);
306 Uart.parityBits <<= 1; // make room for the parity bit
307 Uart.parityBits |= ((Uart.shiftReg >> 8) & 0x01); // store parity bit
308 Uart.bitCount = 0;
309 Uart.shiftReg = 0;
310 if((Uart.len&0x0007) == 0) { // every 8 data bytes
311 Uart.parity[Uart.parityLen++] = Uart.parityBits; // store 8 parity bits
312 Uart.parityBits = 0;
313 }
314 }
315 }
316 }
317 } else {
318 if (IsMillerModulationNibble2(Uart.fourBits >> Uart.syncBit)) { // Modulation second half = Sequence X = logic "1"
319 Uart.bitCount++;
320 Uart.shiftReg = (Uart.shiftReg >> 1) | 0x100; // add a 1 to the shiftreg
321 Uart.state = STATE_MILLER_X;
322 Uart.endTime = Uart.startTime + 8*(9*Uart.len + Uart.bitCount + 1) - 2;
323 if(Uart.bitCount >= 9) { // if we decoded a full byte (including parity)
324 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff);
325 Uart.parityBits <<= 1; // make room for the new parity bit
326 Uart.parityBits |= ((Uart.shiftReg >> 8) & 0x01); // store parity bit
327 Uart.bitCount = 0;
328 Uart.shiftReg = 0;
329 if ((Uart.len&0x0007) == 0) { // every 8 data bytes
330 Uart.parity[Uart.parityLen++] = Uart.parityBits; // store 8 parity bits
331 Uart.parityBits = 0;
332 }
333 }
334 } else { // no modulation in both halves - Sequence Y
335 if (Uart.state == STATE_MILLER_Z || Uart.state == STATE_MILLER_Y) { // Y after logic "0" - End of Communication
336 Uart.state = STATE_UNSYNCD;
337 Uart.bitCount--; // last "0" was part of EOC sequence
338 Uart.shiftReg <<= 1; // drop it
339 if(Uart.bitCount > 0) { // if we decoded some bits
340 Uart.shiftReg >>= (9 - Uart.bitCount); // right align them
341 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff); // add last byte to the output
342 Uart.parityBits <<= 1; // add a (void) parity bit
343 Uart.parityBits <<= (8 - (Uart.len&0x0007)); // left align parity bits
344 Uart.parity[Uart.parityLen++] = Uart.parityBits; // and store it
345 return TRUE;
346 } else if (Uart.len & 0x0007) { // there are some parity bits to store
347 Uart.parityBits <<= (8 - (Uart.len&0x0007)); // left align remaining parity bits
348 Uart.parity[Uart.parityLen++] = Uart.parityBits; // and store them
349 }
350 if (Uart.len) {
351 return TRUE; // we are finished with decoding the raw data sequence
352 } else {
353 UartReset(); // Nothing received - start over
354 }
355 }
356 if (Uart.state == STATE_START_OF_COMMUNICATION) { // error - must not follow directly after SOC
357 UartReset();
358 } else { // a logic "0"
359 Uart.bitCount++;
360 Uart.shiftReg = (Uart.shiftReg >> 1); // add a 0 to the shiftreg
361 Uart.state = STATE_MILLER_Y;
362 if(Uart.bitCount >= 9) { // if we decoded a full byte (including parity)
363 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff);
364 Uart.parityBits <<= 1; // make room for the parity bit
365 Uart.parityBits |= ((Uart.shiftReg >> 8) & 0x01); // store parity bit
366 Uart.bitCount = 0;
367 Uart.shiftReg = 0;
368 if ((Uart.len&0x0007) == 0) { // every 8 data bytes
369 Uart.parity[Uart.parityLen++] = Uart.parityBits; // store 8 parity bits
370 Uart.parityBits = 0;
371 }
372 }
373 }
374 }
375 }
376
377 }
378
379 return FALSE; // not finished yet, need more data
380 }
381
382
383
384 //=============================================================================
385 // ISO 14443 Type A - Manchester decoder
386 //=============================================================================
387 // Basics:
388 // This decoder is used when the PM3 acts as a reader.
389 // The tag will modulate the reader field by asserting different loads to it. As a consequence, the voltage
390 // at the reader antenna will be modulated as well. The FPGA detects the modulation for us and would deliver e.g. the following:
391 // ........ 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 .......
392 // The Manchester decoder needs to identify the following sequences:
393 // 4 ticks modulated followed by 4 ticks unmodulated: Sequence D = 1 (also used as "start of communication")
394 // 4 ticks unmodulated followed by 4 ticks modulated: Sequence E = 0
395 // 8 ticks unmodulated: Sequence F = end of communication
396 // 8 ticks modulated: A collision. Save the collision position and treat as Sequence D
397 // Note 1: the bitstream may start at any time. We therefore need to sync.
398 // Note 2: parameter offset is used to determine the position of the parity bits (required for the anticollision command only)
399 static tDemod Demod;
400
401 // Lookup-Table to decide if 4 raw bits are a modulation.
402 // We accept three or four "1" in any position
403 const bool Mod_Manchester_LUT[] = {
404 FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, TRUE,
405 FALSE, FALSE, FALSE, TRUE, FALSE, TRUE, TRUE, TRUE
406 };
407
408 #define IsManchesterModulationNibble1(b) (Mod_Manchester_LUT[(b & 0x00F0) >> 4])
409 #define IsManchesterModulationNibble2(b) (Mod_Manchester_LUT[(b & 0x000F)])
410
411
412 void DemodReset()
413 {
414 Demod.state = DEMOD_UNSYNCD;
415 Demod.len = 0; // number of decoded data bytes
416 Demod.parityLen = 0;
417 Demod.shiftReg = 0; // shiftreg to hold decoded data bits
418 Demod.parityBits = 0; //
419 Demod.collisionPos = 0; // Position of collision bit
420 Demod.twoBits = 0xffff; // buffer for 2 Bits
421 Demod.highCnt = 0;
422 Demod.startTime = 0;
423 Demod.endTime = 0;
424 }
425
426 void DemodInit(uint8_t *data, uint8_t *parity)
427 {
428 Demod.output = data;
429 Demod.parity = parity;
430 DemodReset();
431 }
432
433 // use parameter non_real_time to provide a timestamp. Set to 0 if the decoder should measure real time
434 static RAMFUNC int ManchesterDecoding(uint8_t bit, uint16_t offset, uint32_t non_real_time)
435 {
436
437 Demod.twoBits = (Demod.twoBits << 8) | bit;
438
439 if (Demod.state == DEMOD_UNSYNCD) {
440
441 if (Demod.highCnt < 2) { // wait for a stable unmodulated signal
442 if (Demod.twoBits == 0x0000) {
443 Demod.highCnt++;
444 } else {
445 Demod.highCnt = 0;
446 }
447 } else {
448 Demod.syncBit = 0xFFFF; // not set
449 if ((Demod.twoBits & 0x7700) == 0x7000) Demod.syncBit = 7;
450 else if ((Demod.twoBits & 0x3B80) == 0x3800) Demod.syncBit = 6;
451 else if ((Demod.twoBits & 0x1DC0) == 0x1C00) Demod.syncBit = 5;
452 else if ((Demod.twoBits & 0x0EE0) == 0x0E00) Demod.syncBit = 4;
453 else if ((Demod.twoBits & 0x0770) == 0x0700) Demod.syncBit = 3;
454 else if ((Demod.twoBits & 0x03B8) == 0x0380) Demod.syncBit = 2;
455 else if ((Demod.twoBits & 0x01DC) == 0x01C0) Demod.syncBit = 1;
456 else if ((Demod.twoBits & 0x00EE) == 0x00E0) Demod.syncBit = 0;
457 if (Demod.syncBit != 0xFFFF) {
458 Demod.startTime = non_real_time?non_real_time:(GetCountSspClk() & 0xfffffff8);
459 Demod.startTime -= Demod.syncBit;
460 Demod.bitCount = offset; // number of decoded data bits
461 Demod.state = DEMOD_MANCHESTER_DATA;
462 }
463 }
464
465 } else {
466
467 if (IsManchesterModulationNibble1(Demod.twoBits >> Demod.syncBit)) { // modulation in first half
468 if (IsManchesterModulationNibble2(Demod.twoBits >> Demod.syncBit)) { // ... and in second half = collision
469 if (!Demod.collisionPos) {
470 Demod.collisionPos = (Demod.len << 3) + Demod.bitCount;
471 }
472 } // modulation in first half only - Sequence D = 1
473 Demod.bitCount++;
474 Demod.shiftReg = (Demod.shiftReg >> 1) | 0x100; // in both cases, add a 1 to the shiftreg
475 if(Demod.bitCount == 9) { // if we decoded a full byte (including parity)
476 Demod.output[Demod.len++] = (Demod.shiftReg & 0xff);
477 Demod.parityBits <<= 1; // make room for the parity bit
478 Demod.parityBits |= ((Demod.shiftReg >> 8) & 0x01); // store parity bit
479 Demod.bitCount = 0;
480 Demod.shiftReg = 0;
481 if((Demod.len&0x0007) == 0) { // every 8 data bytes
482 Demod.parity[Demod.parityLen++] = Demod.parityBits; // store 8 parity bits
483 Demod.parityBits = 0;
484 }
485 }
486 Demod.endTime = Demod.startTime + 8*(9*Demod.len + Demod.bitCount + 1) - 4;
487 } else { // no modulation in first half
488 if (IsManchesterModulationNibble2(Demod.twoBits >> Demod.syncBit)) { // and modulation in second half = Sequence E = 0
489 Demod.bitCount++;
490 Demod.shiftReg = (Demod.shiftReg >> 1); // add a 0 to the shiftreg
491 if(Demod.bitCount >= 9) { // if we decoded a full byte (including parity)
492 Demod.output[Demod.len++] = (Demod.shiftReg & 0xff);
493 Demod.parityBits <<= 1; // make room for the new parity bit
494 Demod.parityBits |= ((Demod.shiftReg >> 8) & 0x01); // store parity bit
495 Demod.bitCount = 0;
496 Demod.shiftReg = 0;
497 if ((Demod.len&0x0007) == 0) { // every 8 data bytes
498 Demod.parity[Demod.parityLen++] = Demod.parityBits; // store 8 parity bits1
499 Demod.parityBits = 0;
500 }
501 }
502 Demod.endTime = Demod.startTime + 8*(9*Demod.len + Demod.bitCount + 1);
503 } else { // no modulation in both halves - End of communication
504 if(Demod.bitCount > 0) { // there are some remaining data bits
505 Demod.shiftReg >>= (9 - Demod.bitCount); // right align the decoded bits
506 Demod.output[Demod.len++] = Demod.shiftReg & 0xff; // and add them to the output
507 Demod.parityBits <<= 1; // add a (void) parity bit
508 Demod.parityBits <<= (8 - (Demod.len&0x0007)); // left align remaining parity bits
509 Demod.parity[Demod.parityLen++] = Demod.parityBits; // and store them
510 return TRUE;
511 } else if (Demod.len & 0x0007) { // there are some parity bits to store
512 Demod.parityBits <<= (8 - (Demod.len&0x0007)); // left align remaining parity bits
513 Demod.parity[Demod.parityLen++] = Demod.parityBits; // and store them
514 }
515 if (Demod.len) {
516 return TRUE; // we are finished with decoding the raw data sequence
517 } else { // nothing received. Start over
518 DemodReset();
519 }
520 }
521 }
522
523 }
524
525 return FALSE; // not finished yet, need more data
526 }
527
528 //=============================================================================
529 // Finally, a `sniffer' for ISO 14443 Type A
530 // Both sides of communication!
531 //=============================================================================
532
533 //-----------------------------------------------------------------------------
534 // Record the sequence of commands sent by the reader to the tag, with
535 // triggering so that we start recording at the point that the tag is moved
536 // near the reader.
537 //-----------------------------------------------------------------------------
538 void RAMFUNC SnoopIso14443a(uint8_t param) {
539 // param:
540 // bit 0 - trigger from first card answer
541 // bit 1 - trigger from first reader 7-bit request
542
543 LEDsoff();
544
545 // We won't start recording the frames that we acquire until we trigger;
546 // a good trigger condition to get started is probably when we see a
547 // response from the tag.
548 // triggered == FALSE -- to wait first for card
549 bool triggered = !(param & 0x03);
550
551 // Allocate memory from BigBuf for some buffers
552 // free all previous allocations first
553 BigBuf_free();
554
555 // The command (reader -> tag) that we're receiving.
556 uint8_t *receivedCmd = BigBuf_malloc(MAX_FRAME_SIZE);
557 uint8_t *receivedCmdPar = BigBuf_malloc(MAX_PARITY_SIZE);
558
559 // The response (tag -> reader) that we're receiving.
560 uint8_t *receivedResponse = BigBuf_malloc(MAX_FRAME_SIZE);
561 uint8_t *receivedResponsePar = BigBuf_malloc(MAX_PARITY_SIZE);
562
563 // The DMA buffer, used to stream samples from the FPGA
564 uint8_t *dmaBuf = BigBuf_malloc(DMA_BUFFER_SIZE);
565
566 // init trace buffer
567 clear_trace();
568 set_tracing(TRUE);
569
570 uint8_t *data = dmaBuf;
571 uint8_t previous_data = 0;
572 int maxDataLen = 0;
573 int dataLen = 0;
574 bool TagIsActive = FALSE;
575 bool ReaderIsActive = FALSE;
576
577 iso14443a_setup(FPGA_HF_ISO14443A_SNIFFER);
578
579 // Set up the demodulator for tag -> reader responses.
580 DemodInit(receivedResponse, receivedResponsePar);
581
582 // Set up the demodulator for the reader -> tag commands
583 UartInit(receivedCmd, receivedCmdPar);
584
585 // Setup and start DMA.
586 FpgaSetupSscDma((uint8_t *)dmaBuf, DMA_BUFFER_SIZE);
587
588 // And now we loop, receiving samples.
589 for(uint32_t rsamples = 0; TRUE; ) {
590
591 if(BUTTON_PRESS()) {
592 DbpString("cancelled by button");
593 break;
594 }
595
596 LED_A_ON();
597 WDT_HIT();
598
599 int register readBufDataP = data - dmaBuf;
600 int register dmaBufDataP = DMA_BUFFER_SIZE - AT91C_BASE_PDC_SSC->PDC_RCR;
601 if (readBufDataP <= dmaBufDataP){
602 dataLen = dmaBufDataP - readBufDataP;
603 } else {
604 dataLen = DMA_BUFFER_SIZE - readBufDataP + dmaBufDataP;
605 }
606 // test for length of buffer
607 if(dataLen > maxDataLen) {
608 maxDataLen = dataLen;
609 if(dataLen > (9 * DMA_BUFFER_SIZE / 10)) {
610 Dbprintf("blew circular buffer! dataLen=%d", dataLen);
611 break;
612 }
613 }
614 if(dataLen < 1) continue;
615
616 // primary buffer was stopped( <-- we lost data!
617 if (!AT91C_BASE_PDC_SSC->PDC_RCR) {
618 AT91C_BASE_PDC_SSC->PDC_RPR = (uint32_t) dmaBuf;
619 AT91C_BASE_PDC_SSC->PDC_RCR = DMA_BUFFER_SIZE;
620 Dbprintf("RxEmpty ERROR!!! data length:%d", dataLen); // temporary
621 }
622 // secondary buffer sets as primary, secondary buffer was stopped
623 if (!AT91C_BASE_PDC_SSC->PDC_RNCR) {
624 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) dmaBuf;
625 AT91C_BASE_PDC_SSC->PDC_RNCR = DMA_BUFFER_SIZE;
626 }
627
628 LED_A_OFF();
629
630 if (rsamples & 0x01) { // Need two samples to feed Miller and Manchester-Decoder
631
632 if(!TagIsActive) { // no need to try decoding reader data if the tag is sending
633 uint8_t readerdata = (previous_data & 0xF0) | (*data >> 4);
634 if (MillerDecoding(readerdata, (rsamples-1)*4)) {
635 LED_C_ON();
636
637 // check - if there is a short 7bit request from reader
638 if ((!triggered) && (param & 0x02) && (Uart.len == 1) && (Uart.bitCount == 7)) triggered = TRUE;
639
640 if(triggered) {
641 if (!LogTrace(receivedCmd,
642 Uart.len,
643 Uart.startTime*16 - DELAY_READER_AIR2ARM_AS_SNIFFER,
644 Uart.endTime*16 - DELAY_READER_AIR2ARM_AS_SNIFFER,
645 Uart.parity,
646 TRUE)) break;
647 }
648 /* And ready to receive another command. */
649 UartReset();
650 /* And also reset the demod code, which might have been */
651 /* false-triggered by the commands from the reader. */
652 DemodReset();
653 LED_B_OFF();
654 }
655 ReaderIsActive = (Uart.state != STATE_UNSYNCD);
656 }
657
658 if(!ReaderIsActive) { // no need to try decoding tag data if the reader is sending - and we cannot afford the time
659 uint8_t tagdata = (previous_data << 4) | (*data & 0x0F);
660 if(ManchesterDecoding(tagdata, 0, (rsamples-1)*4)) {
661 LED_B_ON();
662
663 if (!LogTrace(receivedResponse,
664 Demod.len,
665 Demod.startTime*16 - DELAY_TAG_AIR2ARM_AS_SNIFFER,
666 Demod.endTime*16 - DELAY_TAG_AIR2ARM_AS_SNIFFER,
667 Demod.parity,
668 FALSE)) break;
669
670 if ((!triggered) && (param & 0x01)) triggered = TRUE;
671
672 // And ready to receive another response.
673 DemodReset();
674 LED_C_OFF();
675 }
676 TagIsActive = (Demod.state != DEMOD_UNSYNCD);
677 }
678 }
679
680 previous_data = *data;
681 rsamples++;
682 data++;
683 if(data == dmaBuf + DMA_BUFFER_SIZE) {
684 data = dmaBuf;
685 }
686 } // main cycle
687
688 DbpString("COMMAND FINISHED");
689
690 FpgaDisableSscDma();
691 Dbprintf("maxDataLen=%d, Uart.state=%x, Uart.len=%d", maxDataLen, Uart.state, Uart.len);
692 Dbprintf("traceLen=%d, Uart.output[0]=%08x", BigBuf_get_traceLen(), (uint32_t)Uart.output[0]);
693 LEDsoff();
694 }
695
696 //-----------------------------------------------------------------------------
697 // Prepare tag messages
698 //-----------------------------------------------------------------------------
699 static void CodeIso14443aAsTagPar(const uint8_t *cmd, uint16_t len, uint8_t *parity)
700 {
701 ToSendReset();
702
703 // Correction bit, might be removed when not needed
704 ToSendStuffBit(0);
705 ToSendStuffBit(0);
706 ToSendStuffBit(0);
707 ToSendStuffBit(0);
708 ToSendStuffBit(1); // 1
709 ToSendStuffBit(0);
710 ToSendStuffBit(0);
711 ToSendStuffBit(0);
712
713 // Send startbit
714 ToSend[++ToSendMax] = SEC_D;
715 LastProxToAirDuration = 8 * ToSendMax - 4;
716
717 for(uint16_t i = 0; i < len; i++) {
718 uint8_t b = cmd[i];
719
720 // Data bits
721 for(uint16_t j = 0; j < 8; j++) {
722 if(b & 1) {
723 ToSend[++ToSendMax] = SEC_D;
724 } else {
725 ToSend[++ToSendMax] = SEC_E;
726 }
727 b >>= 1;
728 }
729
730 // Get the parity bit
731 if (parity[i>>3] & (0x80>>(i&0x0007))) {
732 ToSend[++ToSendMax] = SEC_D;
733 LastProxToAirDuration = 8 * ToSendMax - 4;
734 } else {
735 ToSend[++ToSendMax] = SEC_E;
736 LastProxToAirDuration = 8 * ToSendMax;
737 }
738 }
739
740 // Send stopbit
741 ToSend[++ToSendMax] = SEC_F;
742
743 // Convert from last byte pos to length
744 ToSendMax++;
745 }
746
747 static void CodeIso14443aAsTag(const uint8_t *cmd, uint16_t len)
748 {
749 uint8_t par[MAX_PARITY_SIZE];
750
751 GetParity(cmd, len, par);
752 CodeIso14443aAsTagPar(cmd, len, par);
753 }
754
755
756 static void Code4bitAnswerAsTag(uint8_t cmd)
757 {
758 int i;
759
760 ToSendReset();
761
762 // Correction bit, might be removed when not needed
763 ToSendStuffBit(0);
764 ToSendStuffBit(0);
765 ToSendStuffBit(0);
766 ToSendStuffBit(0);
767 ToSendStuffBit(1); // 1
768 ToSendStuffBit(0);
769 ToSendStuffBit(0);
770 ToSendStuffBit(0);
771
772 // Send startbit
773 ToSend[++ToSendMax] = SEC_D;
774
775 uint8_t b = cmd;
776 for(i = 0; i < 4; i++) {
777 if(b & 1) {
778 ToSend[++ToSendMax] = SEC_D;
779 LastProxToAirDuration = 8 * ToSendMax - 4;
780 } else {
781 ToSend[++ToSendMax] = SEC_E;
782 LastProxToAirDuration = 8 * ToSendMax;
783 }
784 b >>= 1;
785 }
786
787 // Send stopbit
788 ToSend[++ToSendMax] = SEC_F;
789
790 // Convert from last byte pos to length
791 ToSendMax++;
792 }
793
794 //-----------------------------------------------------------------------------
795 // Wait for commands from reader
796 // Stop when button is pressed
797 // Or return TRUE when command is captured
798 //-----------------------------------------------------------------------------
799 static int GetIso14443aCommandFromReader(uint8_t *received, uint8_t *parity, int *len)
800 {
801 // Set FPGA mode to "simulated ISO 14443 tag", no modulation (listen
802 // only, since we are receiving, not transmitting).
803 // Signal field is off with the appropriate LED
804 LED_D_OFF();
805 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_LISTEN);
806
807 // Now run a `software UART' on the stream of incoming samples.
808 UartInit(received, parity);
809
810 // clear RXRDY:
811 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
812
813 for(;;) {
814 WDT_HIT();
815
816 if(BUTTON_PRESS()) return FALSE;
817
818 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
819 b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
820 if(MillerDecoding(b, 0)) {
821 *len = Uart.len;
822 return TRUE;
823 }
824 }
825 }
826 }
827
828 static int EmSendCmd14443aRaw(uint8_t *resp, uint16_t respLen, bool correctionNeeded);
829 int EmSend4bitEx(uint8_t resp, bool correctionNeeded);
830 int EmSend4bit(uint8_t resp);
831 int EmSendCmdExPar(uint8_t *resp, uint16_t respLen, bool correctionNeeded, uint8_t *par);
832 int EmSendCmdEx(uint8_t *resp, uint16_t respLen, bool correctionNeeded);
833 int EmSendCmd(uint8_t *resp, uint16_t respLen);
834 int EmSendCmdPar(uint8_t *resp, uint16_t respLen, uint8_t *par);
835 bool EmLogTrace(uint8_t *reader_data, uint16_t reader_len, uint32_t reader_StartTime, uint32_t reader_EndTime, uint8_t *reader_Parity,
836 uint8_t *tag_data, uint16_t tag_len, uint32_t tag_StartTime, uint32_t tag_EndTime, uint8_t *tag_Parity);
837
838 static uint8_t* free_buffer_pointer;
839
840 typedef struct {
841 uint8_t* response;
842 size_t response_n;
843 uint8_t* modulation;
844 size_t modulation_n;
845 uint32_t ProxToAirDuration;
846 } tag_response_info_t;
847
848 bool prepare_tag_modulation(tag_response_info_t* response_info, size_t max_buffer_size) {
849 // Example response, answer to MIFARE Classic read block will be 16 bytes + 2 CRC = 18 bytes
850 // This will need the following byte array for a modulation sequence
851 // 144 data bits (18 * 8)
852 // 18 parity bits
853 // 2 Start and stop
854 // 1 Correction bit (Answer in 1172 or 1236 periods, see FPGA)
855 // 1 just for the case
856 // ----------- +
857 // 166 bytes, since every bit that needs to be send costs us a byte
858 //
859
860
861 // Prepare the tag modulation bits from the message
862 CodeIso14443aAsTag(response_info->response,response_info->response_n);
863
864 // Make sure we do not exceed the free buffer space
865 if (ToSendMax > max_buffer_size) {
866 Dbprintf("Out of memory, when modulating bits for tag answer:");
867 Dbhexdump(response_info->response_n,response_info->response,false);
868 return false;
869 }
870
871 // Copy the byte array, used for this modulation to the buffer position
872 memcpy(response_info->modulation,ToSend,ToSendMax);
873
874 // Store the number of bytes that were used for encoding/modulation and the time needed to transfer them
875 response_info->modulation_n = ToSendMax;
876 response_info->ProxToAirDuration = LastProxToAirDuration;
877
878 return true;
879 }
880
881
882 // "precompile" responses. There are 7 predefined responses with a total of 28 bytes data to transmit.
883 // Coded responses need one byte per bit to transfer (data, parity, start, stop, correction)
884 // 28 * 8 data bits, 28 * 1 parity bits, 7 start bits, 7 stop bits, 7 correction bits
885 // -> need 273 bytes buffer
886 #define ALLOCATED_TAG_MODULATION_BUFFER_SIZE 273
887
888 bool prepare_allocated_tag_modulation(tag_response_info_t* response_info) {
889 // Retrieve and store the current buffer index
890 response_info->modulation = free_buffer_pointer;
891
892 // Determine the maximum size we can use from our buffer
893 size_t max_buffer_size = ALLOCATED_TAG_MODULATION_BUFFER_SIZE;
894
895 // Forward the prepare tag modulation function to the inner function
896 if (prepare_tag_modulation(response_info, max_buffer_size)) {
897 // Update the free buffer offset
898 free_buffer_pointer += ToSendMax;
899 return true;
900 } else {
901 return false;
902 }
903 }
904
905 //-----------------------------------------------------------------------------
906 // Main loop of simulated tag: receive commands from reader, decide what
907 // response to send, and send it.
908 //-----------------------------------------------------------------------------
909 void SimulateIso14443aTag(int tagType, int uid_1st, int uid_2nd, byte_t* data)
910 {
911 uint8_t sak;
912
913 // The first response contains the ATQA (note: bytes are transmitted in reverse order).
914 uint8_t response1[2];
915
916 switch (tagType) {
917 case 1: { // MIFARE Classic
918 // Says: I am Mifare 1k - original line
919 response1[0] = 0x04;
920 response1[1] = 0x00;
921 sak = 0x08;
922 } break;
923 case 2: { // MIFARE Ultralight
924 // Says: I am a stupid memory tag, no crypto
925 response1[0] = 0x04;
926 response1[1] = 0x00;
927 sak = 0x00;
928 } break;
929 case 3: { // MIFARE DESFire
930 // Says: I am a DESFire tag, ph33r me
931 response1[0] = 0x04;
932 response1[1] = 0x03;
933 sak = 0x20;
934 } break;
935 case 4: { // ISO/IEC 14443-4
936 // Says: I am a javacard (JCOP)
937 response1[0] = 0x04;
938 response1[1] = 0x00;
939 sak = 0x28;
940 } break;
941 case 5: { // MIFARE TNP3XXX
942 // Says: I am a toy
943 response1[0] = 0x01;
944 response1[1] = 0x0f;
945 sak = 0x01;
946 } break;
947 default: {
948 Dbprintf("Error: unkown tagtype (%d)",tagType);
949 return;
950 } break;
951 }
952
953 // The second response contains the (mandatory) first 24 bits of the UID
954 uint8_t response2[5] = {0x00};
955
956 // Check if the uid uses the (optional) part
957 uint8_t response2a[5] = {0x00};
958
959 if (uid_2nd) {
960 response2[0] = 0x88;
961 num_to_bytes(uid_1st,3,response2+1);
962 num_to_bytes(uid_2nd,4,response2a);
963 response2a[4] = response2a[0] ^ response2a[1] ^ response2a[2] ^ response2a[3];
964
965 // Configure the ATQA and SAK accordingly
966 response1[0] |= 0x40;
967 sak |= 0x04;
968 } else {
969 num_to_bytes(uid_1st,4,response2);
970 // Configure the ATQA and SAK accordingly
971 response1[0] &= 0xBF;
972 sak &= 0xFB;
973 }
974
975 // Calculate the BitCountCheck (BCC) for the first 4 bytes of the UID.
976 response2[4] = response2[0] ^ response2[1] ^ response2[2] ^ response2[3];
977
978 // Prepare the mandatory SAK (for 4 and 7 byte UID)
979 uint8_t response3[3] = {0x00};
980 response3[0] = sak;
981 ComputeCrc14443(CRC_14443_A, response3, 1, &response3[1], &response3[2]);
982
983 // Prepare the optional second SAK (for 7 byte UID), drop the cascade bit
984 uint8_t response3a[3] = {0x00};
985 response3a[0] = sak & 0xFB;
986 ComputeCrc14443(CRC_14443_A, response3a, 1, &response3a[1], &response3a[2]);
987
988 uint8_t response5[] = { 0x00, 0x00, 0x00, 0x00 }; // Very random tag nonce
989 uint8_t response6[] = { 0x04, 0x58, 0x80, 0x02, 0x00, 0x00 }; // dummy ATS (pseudo-ATR), answer to RATS:
990 // Format byte = 0x58: FSCI=0x08 (FSC=256), TA(1) and TC(1) present,
991 // TA(1) = 0x80: different divisors not supported, DR = 1, DS = 1
992 // TB(1) = not present. Defaults: FWI = 4 (FWT = 256 * 16 * 2^4 * 1/fc = 4833us), SFGI = 0 (SFG = 256 * 16 * 2^0 * 1/fc = 302us)
993 // TC(1) = 0x02: CID supported, NAD not supported
994 ComputeCrc14443(CRC_14443_A, response6, 4, &response6[4], &response6[5]);
995
996 #define TAG_RESPONSE_COUNT 7
997 tag_response_info_t responses[TAG_RESPONSE_COUNT] = {
998 { .response = response1, .response_n = sizeof(response1) }, // Answer to request - respond with card type
999 { .response = response2, .response_n = sizeof(response2) }, // Anticollision cascade1 - respond with uid
1000 { .response = response2a, .response_n = sizeof(response2a) }, // Anticollision cascade2 - respond with 2nd half of uid if asked
1001 { .response = response3, .response_n = sizeof(response3) }, // Acknowledge select - cascade 1
1002 { .response = response3a, .response_n = sizeof(response3a) }, // Acknowledge select - cascade 2
1003 { .response = response5, .response_n = sizeof(response5) }, // Authentication answer (random nonce)
1004 { .response = response6, .response_n = sizeof(response6) }, // dummy ATS (pseudo-ATR), answer to RATS
1005 };
1006
1007 // Allocate 512 bytes for the dynamic modulation, created when the reader queries for it
1008 // Such a response is less time critical, so we can prepare them on the fly
1009 #define DYNAMIC_RESPONSE_BUFFER_SIZE 64
1010 #define DYNAMIC_MODULATION_BUFFER_SIZE 512
1011 uint8_t dynamic_response_buffer[DYNAMIC_RESPONSE_BUFFER_SIZE];
1012 uint8_t dynamic_modulation_buffer[DYNAMIC_MODULATION_BUFFER_SIZE];
1013 tag_response_info_t dynamic_response_info = {
1014 .response = dynamic_response_buffer,
1015 .response_n = 0,
1016 .modulation = dynamic_modulation_buffer,
1017 .modulation_n = 0
1018 };
1019
1020 BigBuf_free_keep_EM();
1021
1022 // allocate buffers:
1023 uint8_t *receivedCmd = BigBuf_malloc(MAX_FRAME_SIZE);
1024 uint8_t *receivedCmdPar = BigBuf_malloc(MAX_PARITY_SIZE);
1025 free_buffer_pointer = BigBuf_malloc(ALLOCATED_TAG_MODULATION_BUFFER_SIZE);
1026
1027 // clear trace
1028 clear_trace();
1029 set_tracing(TRUE);
1030
1031 // Prepare the responses of the anticollision phase
1032 // there will be not enough time to do this at the moment the reader sends it REQA
1033 for (size_t i=0; i<TAG_RESPONSE_COUNT; i++) {
1034 prepare_allocated_tag_modulation(&responses[i]);
1035 }
1036
1037 int len = 0;
1038
1039 // To control where we are in the protocol
1040 int order = 0;
1041 int lastorder;
1042
1043 // Just to allow some checks
1044 int happened = 0;
1045 int happened2 = 0;
1046 int cmdsRecvd = 0;
1047
1048 // We need to listen to the high-frequency, peak-detected path.
1049 iso14443a_setup(FPGA_HF_ISO14443A_TAGSIM_LISTEN);
1050
1051 cmdsRecvd = 0;
1052 tag_response_info_t* p_response;
1053
1054 LED_A_ON();
1055 for(;;) {
1056 // Clean receive command buffer
1057
1058 if(!GetIso14443aCommandFromReader(receivedCmd, receivedCmdPar, &len)) {
1059 DbpString("Button press");
1060 break;
1061 }
1062
1063 p_response = NULL;
1064
1065 // Okay, look at the command now.
1066 lastorder = order;
1067 if(receivedCmd[0] == 0x26) { // Received a REQUEST
1068 p_response = &responses[0]; order = 1;
1069 } else if(receivedCmd[0] == 0x52) { // Received a WAKEUP
1070 p_response = &responses[0]; order = 6;
1071 } else if(receivedCmd[1] == 0x20 && receivedCmd[0] == 0x93) { // Received request for UID (cascade 1)
1072 p_response = &responses[1]; order = 2;
1073 } else if(receivedCmd[1] == 0x20 && receivedCmd[0] == 0x95) { // Received request for UID (cascade 2)
1074 p_response = &responses[2]; order = 20;
1075 } else if(receivedCmd[1] == 0x70 && receivedCmd[0] == 0x93) { // Received a SELECT (cascade 1)
1076 p_response = &responses[3]; order = 3;
1077 } else if(receivedCmd[1] == 0x70 && receivedCmd[0] == 0x95) { // Received a SELECT (cascade 2)
1078 p_response = &responses[4]; order = 30;
1079 } else if(receivedCmd[0] == 0x30) { // Received a (plain) READ
1080 EmSendCmdEx(data+(4*receivedCmd[1]),16,false);
1081 // Dbprintf("Read request from reader: %x %x",receivedCmd[0],receivedCmd[1]);
1082 // We already responded, do not send anything with the EmSendCmd14443aRaw() that is called below
1083 p_response = NULL;
1084 } else if(receivedCmd[0] == 0x50) { // Received a HALT
1085
1086 if (tracing) {
1087 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
1088 }
1089 p_response = NULL;
1090 } else if(receivedCmd[0] == 0x60 || receivedCmd[0] == 0x61) { // Received an authentication request
1091 p_response = &responses[5]; order = 7;
1092 } else if(receivedCmd[0] == 0xE0) { // Received a RATS request
1093 if (tagType == 1 || tagType == 2) { // RATS not supported
1094 EmSend4bit(CARD_NACK_NA);
1095 p_response = NULL;
1096 } else {
1097 p_response = &responses[6]; order = 70;
1098 }
1099 } else if (order == 7 && len == 8) { // Received {nr] and {ar} (part of authentication)
1100 if (tracing) {
1101 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
1102 }
1103 uint32_t nr = bytes_to_num(receivedCmd,4);
1104 uint32_t ar = bytes_to_num(receivedCmd+4,4);
1105 Dbprintf("Auth attempt {nr}{ar}: %08x %08x",nr,ar);
1106 } else {
1107 // Check for ISO 14443A-4 compliant commands, look at left nibble
1108 switch (receivedCmd[0]) {
1109
1110 case 0x0B:
1111 case 0x0A: { // IBlock (command)
1112 dynamic_response_info.response[0] = receivedCmd[0];
1113 dynamic_response_info.response[1] = 0x00;
1114 dynamic_response_info.response[2] = 0x90;
1115 dynamic_response_info.response[3] = 0x00;
1116 dynamic_response_info.response_n = 4;
1117 } break;
1118
1119 case 0x1A:
1120 case 0x1B: { // Chaining command
1121 dynamic_response_info.response[0] = 0xaa | ((receivedCmd[0]) & 1);
1122 dynamic_response_info.response_n = 2;
1123 } break;
1124
1125 case 0xaa:
1126 case 0xbb: {
1127 dynamic_response_info.response[0] = receivedCmd[0] ^ 0x11;
1128 dynamic_response_info.response_n = 2;
1129 } break;
1130
1131 case 0xBA: { //
1132 memcpy(dynamic_response_info.response,"\xAB\x00",2);
1133 dynamic_response_info.response_n = 2;
1134 } break;
1135
1136 case 0xCA:
1137 case 0xC2: { // Readers sends deselect command
1138 memcpy(dynamic_response_info.response,"\xCA\x00",2);
1139 dynamic_response_info.response_n = 2;
1140 } break;
1141
1142 default: {
1143 // Never seen this command before
1144 if (tracing) {
1145 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
1146 }
1147 Dbprintf("Received unknown command (len=%d):",len);
1148 Dbhexdump(len,receivedCmd,false);
1149 // Do not respond
1150 dynamic_response_info.response_n = 0;
1151 } break;
1152 }
1153
1154 if (dynamic_response_info.response_n > 0) {
1155 // Copy the CID from the reader query
1156 dynamic_response_info.response[1] = receivedCmd[1];
1157
1158 // Add CRC bytes, always used in ISO 14443A-4 compliant cards
1159 AppendCrc14443a(dynamic_response_info.response,dynamic_response_info.response_n);
1160 dynamic_response_info.response_n += 2;
1161
1162 if (prepare_tag_modulation(&dynamic_response_info,DYNAMIC_MODULATION_BUFFER_SIZE) == false) {
1163 Dbprintf("Error preparing tag response");
1164 if (tracing) {
1165 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
1166 }
1167 break;
1168 }
1169 p_response = &dynamic_response_info;
1170 }
1171 }
1172
1173 // Count number of wakeups received after a halt
1174 if(order == 6 && lastorder == 5) { happened++; }
1175
1176 // Count number of other messages after a halt
1177 if(order != 6 && lastorder == 5) { happened2++; }
1178
1179 if(cmdsRecvd > 999) {
1180 DbpString("1000 commands later...");
1181 break;
1182 }
1183 cmdsRecvd++;
1184
1185 if (p_response != NULL) {
1186 EmSendCmd14443aRaw(p_response->modulation, p_response->modulation_n, receivedCmd[0] == 0x52);
1187 // do the tracing for the previous reader request and this tag answer:
1188 uint8_t par[MAX_PARITY_SIZE];
1189 GetParity(p_response->response, p_response->response_n, par);
1190
1191 EmLogTrace(Uart.output,
1192 Uart.len,
1193 Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG,
1194 Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG,
1195 Uart.parity,
1196 p_response->response,
1197 p_response->response_n,
1198 LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_TAG,
1199 (LastTimeProxToAirStart + p_response->ProxToAirDuration)*16 + DELAY_ARM2AIR_AS_TAG,
1200 par);
1201 }
1202
1203 if (!tracing) {
1204 Dbprintf("Trace Full. Simulation stopped.");
1205 break;
1206 }
1207 }
1208
1209 Dbprintf("%x %x %x", happened, happened2, cmdsRecvd);
1210 LED_A_OFF();
1211 BigBuf_free_keep_EM();
1212 }
1213
1214
1215 // prepare a delayed transfer. This simply shifts ToSend[] by a number
1216 // of bits specified in the delay parameter.
1217 void PrepareDelayedTransfer(uint16_t delay)
1218 {
1219 uint8_t bitmask = 0;
1220 uint8_t bits_to_shift = 0;
1221 uint8_t bits_shifted = 0;
1222
1223 delay &= 0x07;
1224 if (delay) {
1225 for (uint16_t i = 0; i < delay; i++) {
1226 bitmask |= (0x01 << i);
1227 }
1228 ToSend[ToSendMax++] = 0x00;
1229 for (uint16_t i = 0; i < ToSendMax; i++) {
1230 bits_to_shift = ToSend[i] & bitmask;
1231 ToSend[i] = ToSend[i] >> delay;
1232 ToSend[i] = ToSend[i] | (bits_shifted << (8 - delay));
1233 bits_shifted = bits_to_shift;
1234 }
1235 }
1236 }
1237
1238
1239 //-------------------------------------------------------------------------------------
1240 // Transmit the command (to the tag) that was placed in ToSend[].
1241 // Parameter timing:
1242 // if NULL: transfer at next possible time, taking into account
1243 // request guard time and frame delay time
1244 // if == 0: transfer immediately and return time of transfer
1245 // if != 0: delay transfer until time specified
1246 //-------------------------------------------------------------------------------------
1247 static void TransmitFor14443a(const uint8_t *cmd, uint16_t len, uint32_t *timing)
1248 {
1249
1250 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_MOD);
1251
1252 uint32_t ThisTransferTime = 0;
1253
1254 if (timing) {
1255 if(*timing == 0) { // Measure time
1256 *timing = (GetCountSspClk() + 8) & 0xfffffff8;
1257 } else {
1258 PrepareDelayedTransfer(*timing & 0x00000007); // Delay transfer (fine tuning - up to 7 MF clock ticks)
1259 }
1260 if(MF_DBGLEVEL >= 4 && GetCountSspClk() >= (*timing & 0xfffffff8)) Dbprintf("TransmitFor14443a: Missed timing");
1261 while(GetCountSspClk() < (*timing & 0xfffffff8)); // Delay transfer (multiple of 8 MF clock ticks)
1262 LastTimeProxToAirStart = *timing;
1263 } else {
1264 ThisTransferTime = ((MAX(NextTransferTime, GetCountSspClk()) & 0xfffffff8) + 8);
1265 while(GetCountSspClk() < ThisTransferTime);
1266 LastTimeProxToAirStart = ThisTransferTime;
1267 }
1268
1269 // clear TXRDY
1270 AT91C_BASE_SSC->SSC_THR = SEC_Y;
1271
1272 uint16_t c = 0;
1273 for(;;) {
1274 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1275 AT91C_BASE_SSC->SSC_THR = cmd[c];
1276 c++;
1277 if(c >= len) {
1278 break;
1279 }
1280 }
1281 }
1282
1283 NextTransferTime = MAX(NextTransferTime, LastTimeProxToAirStart + REQUEST_GUARD_TIME);
1284 }
1285
1286
1287 //-----------------------------------------------------------------------------
1288 // Prepare reader command (in bits, support short frames) to send to FPGA
1289 //-----------------------------------------------------------------------------
1290 void CodeIso14443aBitsAsReaderPar(const uint8_t *cmd, uint16_t bits, const uint8_t *parity)
1291 {
1292 int i, j;
1293 int last;
1294 uint8_t b;
1295
1296 ToSendReset();
1297
1298 // Start of Communication (Seq. Z)
1299 ToSend[++ToSendMax] = SEC_Z;
1300 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1301 last = 0;
1302
1303 size_t bytecount = nbytes(bits);
1304 // Generate send structure for the data bits
1305 for (i = 0; i < bytecount; i++) {
1306 // Get the current byte to send
1307 b = cmd[i];
1308 size_t bitsleft = MIN((bits-(i*8)),8);
1309
1310 for (j = 0; j < bitsleft; j++) {
1311 if (b & 1) {
1312 // Sequence X
1313 ToSend[++ToSendMax] = SEC_X;
1314 LastProxToAirDuration = 8 * (ToSendMax+1) - 2;
1315 last = 1;
1316 } else {
1317 if (last == 0) {
1318 // Sequence Z
1319 ToSend[++ToSendMax] = SEC_Z;
1320 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1321 } else {
1322 // Sequence Y
1323 ToSend[++ToSendMax] = SEC_Y;
1324 last = 0;
1325 }
1326 }
1327 b >>= 1;
1328 }
1329
1330 // Only transmit parity bit if we transmitted a complete byte
1331 if (j == 8) {
1332 // Get the parity bit
1333 if (parity[i>>3] & (0x80 >> (i&0x0007))) {
1334 // Sequence X
1335 ToSend[++ToSendMax] = SEC_X;
1336 LastProxToAirDuration = 8 * (ToSendMax+1) - 2;
1337 last = 1;
1338 } else {
1339 if (last == 0) {
1340 // Sequence Z
1341 ToSend[++ToSendMax] = SEC_Z;
1342 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1343 } else {
1344 // Sequence Y
1345 ToSend[++ToSendMax] = SEC_Y;
1346 last = 0;
1347 }
1348 }
1349 }
1350 }
1351
1352 // End of Communication: Logic 0 followed by Sequence Y
1353 if (last == 0) {
1354 // Sequence Z
1355 ToSend[++ToSendMax] = SEC_Z;
1356 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1357 } else {
1358 // Sequence Y
1359 ToSend[++ToSendMax] = SEC_Y;
1360 last = 0;
1361 }
1362 ToSend[++ToSendMax] = SEC_Y;
1363
1364 // Convert to length of command:
1365 ToSendMax++;
1366 }
1367
1368 //-----------------------------------------------------------------------------
1369 // Prepare reader command to send to FPGA
1370 //-----------------------------------------------------------------------------
1371 void CodeIso14443aAsReaderPar(const uint8_t *cmd, uint16_t len, const uint8_t *parity)
1372 {
1373 CodeIso14443aBitsAsReaderPar(cmd, len*8, parity);
1374 }
1375
1376
1377 //-----------------------------------------------------------------------------
1378 // Wait for commands from reader
1379 // Stop when button is pressed (return 1) or field was gone (return 2)
1380 // Or return 0 when command is captured
1381 //-----------------------------------------------------------------------------
1382 static int EmGetCmd(uint8_t *received, uint16_t *len, uint8_t *parity)
1383 {
1384 *len = 0;
1385
1386 uint32_t timer = 0, vtime = 0;
1387 int analogCnt = 0;
1388 int analogAVG = 0;
1389
1390 // Set FPGA mode to "simulated ISO 14443 tag", no modulation (listen
1391 // only, since we are receiving, not transmitting).
1392 // Signal field is off with the appropriate LED
1393 LED_D_OFF();
1394 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_LISTEN);
1395
1396 // Set ADC to read field strength
1397 AT91C_BASE_ADC->ADC_CR = AT91C_ADC_SWRST;
1398 AT91C_BASE_ADC->ADC_MR =
1399 ADC_MODE_PRESCALE(63) |
1400 ADC_MODE_STARTUP_TIME(1) |
1401 ADC_MODE_SAMPLE_HOLD_TIME(15);
1402 AT91C_BASE_ADC->ADC_CHER = ADC_CHANNEL(ADC_CHAN_HF);
1403 // start ADC
1404 AT91C_BASE_ADC->ADC_CR = AT91C_ADC_START;
1405
1406 // Now run a 'software UART' on the stream of incoming samples.
1407 UartInit(received, parity);
1408
1409 // Clear RXRDY:
1410 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1411
1412 for(;;) {
1413 WDT_HIT();
1414
1415 if (BUTTON_PRESS()) return 1;
1416
1417 // test if the field exists
1418 if (AT91C_BASE_ADC->ADC_SR & ADC_END_OF_CONVERSION(ADC_CHAN_HF)) {
1419 analogCnt++;
1420 analogAVG += AT91C_BASE_ADC->ADC_CDR[ADC_CHAN_HF];
1421 AT91C_BASE_ADC->ADC_CR = AT91C_ADC_START;
1422 if (analogCnt >= 32) {
1423 if ((MAX_ADC_HF_VOLTAGE * (analogAVG / analogCnt) >> 10) < MF_MINFIELDV) {
1424 vtime = GetTickCount();
1425 if (!timer) timer = vtime;
1426 // 50ms no field --> card to idle state
1427 if (vtime - timer > 50) return 2;
1428 } else
1429 if (timer) timer = 0;
1430 analogCnt = 0;
1431 analogAVG = 0;
1432 }
1433 }
1434
1435 // receive and test the miller decoding
1436 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
1437 b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1438 if(MillerDecoding(b, 0)) {
1439 *len = Uart.len;
1440 return 0;
1441 }
1442 }
1443
1444 }
1445 }
1446
1447
1448 static int EmSendCmd14443aRaw(uint8_t *resp, uint16_t respLen, bool correctionNeeded)
1449 {
1450 uint8_t b;
1451 uint16_t i = 0;
1452 uint32_t ThisTransferTime;
1453
1454 // Modulate Manchester
1455 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_MOD);
1456
1457 // include correction bit if necessary
1458 if (Uart.parityBits & 0x01) {
1459 correctionNeeded = TRUE;
1460 }
1461 if(correctionNeeded) {
1462 // 1236, so correction bit needed
1463 i = 0;
1464 } else {
1465 i = 1;
1466 }
1467
1468 // clear receiving shift register and holding register
1469 while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
1470 b = AT91C_BASE_SSC->SSC_RHR; (void) b;
1471 while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
1472 b = AT91C_BASE_SSC->SSC_RHR; (void) b;
1473
1474 // wait for the FPGA to signal fdt_indicator == 1 (the FPGA is ready to queue new data in its delay line)
1475 for (uint16_t j = 0; j < 5; j++) { // allow timeout - better late than never
1476 while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
1477 if (AT91C_BASE_SSC->SSC_RHR) break;
1478 }
1479
1480 while ((ThisTransferTime = GetCountSspClk()) & 0x00000007);
1481
1482 // Clear TXRDY:
1483 AT91C_BASE_SSC->SSC_THR = SEC_F;
1484
1485 // send cycle
1486 for(; i < respLen; ) {
1487 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1488 AT91C_BASE_SSC->SSC_THR = resp[i++];
1489 FpgaSendQueueDelay = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1490 }
1491
1492 if(BUTTON_PRESS()) {
1493 break;
1494 }
1495 }
1496
1497 // Ensure that the FPGA Delay Queue is empty before we switch to TAGSIM_LISTEN again:
1498 uint8_t fpga_queued_bits = FpgaSendQueueDelay >> 3;
1499 for (i = 0; i <= fpga_queued_bits/8 + 1; ) {
1500 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1501 AT91C_BASE_SSC->SSC_THR = SEC_F;
1502 FpgaSendQueueDelay = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1503 i++;
1504 }
1505 }
1506
1507 LastTimeProxToAirStart = ThisTransferTime + (correctionNeeded?8:0);
1508
1509 return 0;
1510 }
1511
1512 int EmSend4bitEx(uint8_t resp, bool correctionNeeded){
1513 Code4bitAnswerAsTag(resp);
1514 int res = EmSendCmd14443aRaw(ToSend, ToSendMax, correctionNeeded);
1515 // do the tracing for the previous reader request and this tag answer:
1516 uint8_t par[1];
1517 GetParity(&resp, 1, par);
1518 EmLogTrace(Uart.output,
1519 Uart.len,
1520 Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG,
1521 Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG,
1522 Uart.parity,
1523 &resp,
1524 1,
1525 LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_TAG,
1526 (LastTimeProxToAirStart + LastProxToAirDuration)*16 + DELAY_ARM2AIR_AS_TAG,
1527 par);
1528 return res;
1529 }
1530
1531 int EmSend4bit(uint8_t resp){
1532 return EmSend4bitEx(resp, false);
1533 }
1534
1535 int EmSendCmdExPar(uint8_t *resp, uint16_t respLen, bool correctionNeeded, uint8_t *par){
1536 CodeIso14443aAsTagPar(resp, respLen, par);
1537 int res = EmSendCmd14443aRaw(ToSend, ToSendMax, correctionNeeded);
1538 // do the tracing for the previous reader request and this tag answer:
1539 EmLogTrace(Uart.output,
1540 Uart.len,
1541 Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG,
1542 Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG,
1543 Uart.parity,
1544 resp,
1545 respLen,
1546 LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_TAG,
1547 (LastTimeProxToAirStart + LastProxToAirDuration)*16 + DELAY_ARM2AIR_AS_TAG,
1548 par);
1549 return res;
1550 }
1551
1552 int EmSendCmdEx(uint8_t *resp, uint16_t respLen, bool correctionNeeded){
1553 uint8_t par[MAX_PARITY_SIZE];
1554 GetParity(resp, respLen, par);
1555 return EmSendCmdExPar(resp, respLen, correctionNeeded, par);
1556 }
1557
1558 int EmSendCmd(uint8_t *resp, uint16_t respLen){
1559 uint8_t par[MAX_PARITY_SIZE];
1560 GetParity(resp, respLen, par);
1561 return EmSendCmdExPar(resp, respLen, false, par);
1562 }
1563
1564 int EmSendCmdPar(uint8_t *resp, uint16_t respLen, uint8_t *par){
1565 return EmSendCmdExPar(resp, respLen, false, par);
1566 }
1567
1568 bool EmLogTrace(uint8_t *reader_data, uint16_t reader_len, uint32_t reader_StartTime, uint32_t reader_EndTime, uint8_t *reader_Parity,
1569 uint8_t *tag_data, uint16_t tag_len, uint32_t tag_StartTime, uint32_t tag_EndTime, uint8_t *tag_Parity)
1570 {
1571 if (tracing) {
1572 // we cannot exactly measure the end and start of a received command from reader. However we know that the delay from
1573 // end of the received command to start of the tag's (simulated by us) answer is n*128+20 or n*128+84 resp.
1574 // with n >= 9. The start of the tags answer can be measured and therefore the end of the received command be calculated:
1575 uint16_t reader_modlen = reader_EndTime - reader_StartTime;
1576 uint16_t approx_fdt = tag_StartTime - reader_EndTime;
1577 uint16_t exact_fdt = (approx_fdt - 20 + 32)/64 * 64 + 20;
1578 reader_EndTime = tag_StartTime - exact_fdt;
1579 reader_StartTime = reader_EndTime - reader_modlen;
1580 if (!LogTrace(reader_data, reader_len, reader_StartTime, reader_EndTime, reader_Parity, TRUE)) {
1581 return FALSE;
1582 } else return(!LogTrace(tag_data, tag_len, tag_StartTime, tag_EndTime, tag_Parity, FALSE));
1583 } else {
1584 return TRUE;
1585 }
1586 }
1587
1588 //-----------------------------------------------------------------------------
1589 // Wait a certain time for tag response
1590 // If a response is captured return TRUE
1591 // If it takes too long return FALSE
1592 //-----------------------------------------------------------------------------
1593 static int GetIso14443aAnswerFromTag(uint8_t *receivedResponse, uint8_t *receivedResponsePar, uint16_t offset)
1594 {
1595 uint32_t c;
1596
1597 // Set FPGA mode to "reader listen mode", no modulation (listen
1598 // only, since we are receiving, not transmitting).
1599 // Signal field is on with the appropriate LED
1600 LED_D_ON();
1601 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_LISTEN);
1602
1603 // Now get the answer from the card
1604 DemodInit(receivedResponse, receivedResponsePar);
1605
1606 // clear RXRDY:
1607 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1608
1609 c = 0;
1610 for(;;) {
1611 WDT_HIT();
1612
1613 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
1614 b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1615 if(ManchesterDecoding(b, offset, 0)) {
1616 NextTransferTime = MAX(NextTransferTime, Demod.endTime - (DELAY_AIR2ARM_AS_READER + DELAY_ARM2AIR_AS_READER)/16 + FRAME_DELAY_TIME_PICC_TO_PCD);
1617 return TRUE;
1618 } else if (c++ > iso14a_timeout && Demod.state == DEMOD_UNSYNCD) {
1619 return FALSE;
1620 }
1621 }
1622 }
1623 }
1624
1625 void ReaderTransmitBitsPar(uint8_t* frame, uint16_t bits, uint8_t *par, uint32_t *timing)
1626 {
1627 CodeIso14443aBitsAsReaderPar(frame, bits, par);
1628
1629 // Send command to tag
1630 TransmitFor14443a(ToSend, ToSendMax, timing);
1631 if(trigger)
1632 LED_A_ON();
1633
1634 // Log reader command in trace buffer
1635 if (tracing) {
1636 LogTrace(frame, nbytes(bits), LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_READER, (LastTimeProxToAirStart + LastProxToAirDuration)*16 + DELAY_ARM2AIR_AS_READER, par, TRUE);
1637 }
1638 }
1639
1640 void ReaderTransmitPar(uint8_t* frame, uint16_t len, uint8_t *par, uint32_t *timing)
1641 {
1642 ReaderTransmitBitsPar(frame, len*8, par, timing);
1643 }
1644
1645 void ReaderTransmitBits(uint8_t* frame, uint16_t len, uint32_t *timing)
1646 {
1647 // Generate parity and redirect
1648 uint8_t par[MAX_PARITY_SIZE];
1649 GetParity(frame, len/8, par);
1650 ReaderTransmitBitsPar(frame, len, par, timing);
1651 }
1652
1653 void ReaderTransmit(uint8_t* frame, uint16_t len, uint32_t *timing)
1654 {
1655 // Generate parity and redirect
1656 uint8_t par[MAX_PARITY_SIZE];
1657 GetParity(frame, len, par);
1658 ReaderTransmitBitsPar(frame, len*8, par, timing);
1659 }
1660
1661 int ReaderReceiveOffset(uint8_t* receivedAnswer, uint16_t offset, uint8_t *parity)
1662 {
1663 if (!GetIso14443aAnswerFromTag(receivedAnswer, parity, offset)) return FALSE;
1664 if (tracing) {
1665 LogTrace(receivedAnswer, Demod.len, Demod.startTime*16 - DELAY_AIR2ARM_AS_READER, Demod.endTime*16 - DELAY_AIR2ARM_AS_READER, parity, FALSE);
1666 }
1667 return Demod.len;
1668 }
1669
1670 int ReaderReceive(uint8_t *receivedAnswer, uint8_t *parity)
1671 {
1672 if (!GetIso14443aAnswerFromTag(receivedAnswer, parity, 0)) return FALSE;
1673 if (tracing) {
1674 LogTrace(receivedAnswer, Demod.len, Demod.startTime*16 - DELAY_AIR2ARM_AS_READER, Demod.endTime*16 - DELAY_AIR2ARM_AS_READER, parity, FALSE);
1675 }
1676 return Demod.len;
1677 }
1678
1679 /* performs iso14443a anticollision procedure
1680 * fills the uid pointer unless NULL
1681 * fills resp_data unless NULL */
1682 int iso14443a_select_card(byte_t *uid_ptr, iso14a_card_select_t *p_hi14a_card, uint32_t *cuid_ptr) {
1683 uint8_t wupa[] = { 0x52 }; // 0x26 - REQA 0x52 - WAKE-UP
1684 uint8_t sel_all[] = { 0x93,0x20 };
1685 uint8_t sel_uid[] = { 0x93,0x70,0x00,0x00,0x00,0x00,0x00,0x00,0x00};
1686 uint8_t rats[] = { 0xE0,0x80,0x00,0x00 }; // FSD=256, FSDI=8, CID=0
1687 uint8_t resp[MAX_FRAME_SIZE]; // theoretically. A usual RATS will be much smaller
1688 uint8_t resp_par[MAX_PARITY_SIZE];
1689 byte_t uid_resp[4];
1690 size_t uid_resp_len;
1691
1692 uint8_t sak = 0x04; // cascade uid
1693 int cascade_level = 0;
1694 int len;
1695
1696 // Broadcast for a card, WUPA (0x52) will force response from all cards in the field
1697 ReaderTransmitBitsPar(wupa,7,0, NULL);
1698
1699 // Receive the ATQA
1700 if(!ReaderReceive(resp, resp_par)) return 0;
1701
1702 if(p_hi14a_card) {
1703 memcpy(p_hi14a_card->atqa, resp, 2);
1704 p_hi14a_card->uidlen = 0;
1705 memset(p_hi14a_card->uid,0,10);
1706 }
1707
1708 // clear uid
1709 if (uid_ptr) {
1710 memset(uid_ptr,0,10);
1711 }
1712
1713 // check for proprietary anticollision:
1714 if ((resp[0] & 0x1F) == 0) {
1715 return 3;
1716 }
1717
1718 // OK we will select at least at cascade 1, lets see if first byte of UID was 0x88 in
1719 // which case we need to make a cascade 2 request and select - this is a long UID
1720 // While the UID is not complete, the 3nd bit (from the right) is set in the SAK.
1721 for(; sak & 0x04; cascade_level++) {
1722 // SELECT_* (L1: 0x93, L2: 0x95, L3: 0x97)
1723 sel_uid[0] = sel_all[0] = 0x93 + cascade_level * 2;
1724
1725 // SELECT_ALL
1726 ReaderTransmit(sel_all, sizeof(sel_all), NULL);
1727 if (!ReaderReceive(resp, resp_par)) return 0;
1728
1729 if (Demod.collisionPos) { // we had a collision and need to construct the UID bit by bit
1730 memset(uid_resp, 0, 4);
1731 uint16_t uid_resp_bits = 0;
1732 uint16_t collision_answer_offset = 0;
1733 // anti-collision-loop:
1734 while (Demod.collisionPos) {
1735 Dbprintf("Multiple tags detected. Collision after Bit %d", Demod.collisionPos);
1736 for (uint16_t i = collision_answer_offset; i < Demod.collisionPos; i++, uid_resp_bits++) { // add valid UID bits before collision point
1737 uint16_t UIDbit = (resp[i/8] >> (i % 8)) & 0x01;
1738 uid_resp[uid_resp_bits / 8] |= UIDbit << (uid_resp_bits % 8);
1739 }
1740 uid_resp[uid_resp_bits/8] |= 1 << (uid_resp_bits % 8); // next time select the card(s) with a 1 in the collision position
1741 uid_resp_bits++;
1742 // construct anticollosion command:
1743 sel_uid[1] = ((2 + uid_resp_bits/8) << 4) | (uid_resp_bits & 0x07); // length of data in bytes and bits
1744 for (uint16_t i = 0; i <= uid_resp_bits/8; i++) {
1745 sel_uid[2+i] = uid_resp[i];
1746 }
1747 collision_answer_offset = uid_resp_bits%8;
1748 ReaderTransmitBits(sel_uid, 16 + uid_resp_bits, NULL);
1749 if (!ReaderReceiveOffset(resp, collision_answer_offset, resp_par)) return 0;
1750 }
1751 // finally, add the last bits and BCC of the UID
1752 for (uint16_t i = collision_answer_offset; i < (Demod.len-1)*8; i++, uid_resp_bits++) {
1753 uint16_t UIDbit = (resp[i/8] >> (i%8)) & 0x01;
1754 uid_resp[uid_resp_bits/8] |= UIDbit << (uid_resp_bits % 8);
1755 }
1756
1757 } else { // no collision, use the response to SELECT_ALL as current uid
1758 memcpy(uid_resp, resp, 4);
1759 }
1760 uid_resp_len = 4;
1761
1762 // calculate crypto UID. Always use last 4 Bytes.
1763 if(cuid_ptr) {
1764 *cuid_ptr = bytes_to_num(uid_resp, 4);
1765 }
1766
1767 // Construct SELECT UID command
1768 sel_uid[1] = 0x70; // transmitting a full UID (1 Byte cmd, 1 Byte NVB, 4 Byte UID, 1 Byte BCC, 2 Bytes CRC)
1769 memcpy(sel_uid+2, uid_resp, 4); // the UID
1770 sel_uid[6] = sel_uid[2] ^ sel_uid[3] ^ sel_uid[4] ^ sel_uid[5]; // calculate and add BCC
1771 AppendCrc14443a(sel_uid, 7); // calculate and add CRC
1772 ReaderTransmit(sel_uid, sizeof(sel_uid), NULL);
1773
1774 // Receive the SAK
1775 if (!ReaderReceive(resp, resp_par)) return 0;
1776 sak = resp[0];
1777
1778 // Test if more parts of the uid are coming
1779 if ((sak & 0x04) /* && uid_resp[0] == 0x88 */) {
1780 // Remove first byte, 0x88 is not an UID byte, it CT, see page 3 of:
1781 // http://www.nxp.com/documents/application_note/AN10927.pdf
1782 uid_resp[0] = uid_resp[1];
1783 uid_resp[1] = uid_resp[2];
1784 uid_resp[2] = uid_resp[3];
1785
1786 uid_resp_len = 3;
1787 }
1788
1789 if(uid_ptr) {
1790 memcpy(uid_ptr + (cascade_level*3), uid_resp, uid_resp_len);
1791 }
1792
1793 if(p_hi14a_card) {
1794 memcpy(p_hi14a_card->uid + (cascade_level*3), uid_resp, uid_resp_len);
1795 p_hi14a_card->uidlen += uid_resp_len;
1796 }
1797 }
1798
1799 if(p_hi14a_card) {
1800 p_hi14a_card->sak = sak;
1801 p_hi14a_card->ats_len = 0;
1802 }
1803
1804 // non iso14443a compliant tag
1805 if( (sak & 0x20) == 0) return 2;
1806
1807 // Request for answer to select
1808 AppendCrc14443a(rats, 2);
1809 ReaderTransmit(rats, sizeof(rats), NULL);
1810
1811 if (!(len = ReaderReceive(resp, resp_par))) return 0;
1812
1813
1814 if(p_hi14a_card) {
1815 memcpy(p_hi14a_card->ats, resp, sizeof(p_hi14a_card->ats));
1816 p_hi14a_card->ats_len = len;
1817 }
1818
1819 // reset the PCB block number
1820 iso14_pcb_blocknum = 0;
1821
1822 // set default timeout based on ATS
1823 iso14a_set_ATS_timeout(resp);
1824
1825 return 1;
1826 }
1827
1828 void iso14443a_setup(uint8_t fpga_minor_mode) {
1829 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
1830 // Set up the synchronous serial port
1831 FpgaSetupSsc();
1832 // connect Demodulated Signal to ADC:
1833 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
1834
1835 // Signal field is on with the appropriate LED
1836 if (fpga_minor_mode == FPGA_HF_ISO14443A_READER_MOD
1837 || fpga_minor_mode == FPGA_HF_ISO14443A_READER_LISTEN) {
1838 LED_D_ON();
1839 } else {
1840 LED_D_OFF();
1841 }
1842 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | fpga_minor_mode);
1843
1844 // Start the timer
1845 StartCountSspClk();
1846
1847 DemodReset();
1848 UartReset();
1849 NextTransferTime = 2*DELAY_ARM2AIR_AS_READER;
1850 iso14a_set_timeout(1050); // 10ms default
1851 }
1852
1853 int iso14_apdu(uint8_t *cmd, uint16_t cmd_len, void *data) {
1854 uint8_t parity[MAX_PARITY_SIZE];
1855 uint8_t real_cmd[cmd_len+4];
1856 real_cmd[0] = 0x0a; //I-Block
1857 // put block number into the PCB
1858 real_cmd[0] |= iso14_pcb_blocknum;
1859 real_cmd[1] = 0x00; //CID: 0 //FIXME: allow multiple selected cards
1860 memcpy(real_cmd+2, cmd, cmd_len);
1861 AppendCrc14443a(real_cmd,cmd_len+2);
1862
1863 ReaderTransmit(real_cmd, cmd_len+4, NULL);
1864 size_t len = ReaderReceive(data, parity);
1865 uint8_t *data_bytes = (uint8_t *) data;
1866 if (!len)
1867 return 0; //DATA LINK ERROR
1868 // if we received an I- or R(ACK)-Block with a block number equal to the
1869 // current block number, toggle the current block number
1870 else if (len >= 4 // PCB+CID+CRC = 4 bytes
1871 && ((data_bytes[0] & 0xC0) == 0 // I-Block
1872 || (data_bytes[0] & 0xD0) == 0x80) // R-Block with ACK bit set to 0
1873 && (data_bytes[0] & 0x01) == iso14_pcb_blocknum) // equal block numbers
1874 {
1875 iso14_pcb_blocknum ^= 1;
1876 }
1877
1878 return len;
1879 }
1880
1881 //-----------------------------------------------------------------------------
1882 // Read an ISO 14443a tag. Send out commands and store answers.
1883 //
1884 //-----------------------------------------------------------------------------
1885 void ReaderIso14443a(UsbCommand *c)
1886 {
1887 iso14a_command_t param = c->arg[0];
1888 uint8_t *cmd = c->d.asBytes;
1889 size_t len = c->arg[1] & 0xffff;
1890 size_t lenbits = c->arg[1] >> 16;
1891 uint32_t timeout = c->arg[2];
1892 uint32_t arg0 = 0;
1893 byte_t buf[USB_CMD_DATA_SIZE];
1894 uint8_t par[MAX_PARITY_SIZE];
1895
1896 if(param & ISO14A_CONNECT) {
1897 clear_trace();
1898 }
1899
1900 set_tracing(TRUE);
1901
1902 if(param & ISO14A_REQUEST_TRIGGER) {
1903 iso14a_set_trigger(TRUE);
1904 }
1905
1906 if(param & ISO14A_CONNECT) {
1907 iso14443a_setup(FPGA_HF_ISO14443A_READER_LISTEN);
1908 if(!(param & ISO14A_NO_SELECT)) {
1909 iso14a_card_select_t *card = (iso14a_card_select_t*)buf;
1910 arg0 = iso14443a_select_card(NULL,card,NULL);
1911 cmd_send(CMD_ACK,arg0,card->uidlen,0,buf,sizeof(iso14a_card_select_t));
1912 }
1913 }
1914
1915 if(param & ISO14A_SET_TIMEOUT) {
1916 iso14a_set_timeout(timeout);
1917 }
1918
1919 if(param & ISO14A_APDU) {
1920 arg0 = iso14_apdu(cmd, len, buf);
1921 cmd_send(CMD_ACK,arg0,0,0,buf,sizeof(buf));
1922 }
1923
1924 if(param & ISO14A_RAW) {
1925 if(param & ISO14A_APPEND_CRC) {
1926 AppendCrc14443a(cmd,len);
1927 len += 2;
1928 if (lenbits) lenbits += 16;
1929 }
1930 if(lenbits>0) {
1931 GetParity(cmd, lenbits/8, par);
1932 ReaderTransmitBitsPar(cmd, lenbits, par, NULL);
1933 } else {
1934 ReaderTransmit(cmd,len, NULL);
1935 }
1936 arg0 = ReaderReceive(buf, par);
1937 cmd_send(CMD_ACK,arg0,0,0,buf,sizeof(buf));
1938 }
1939
1940 if(param & ISO14A_REQUEST_TRIGGER) {
1941 iso14a_set_trigger(FALSE);
1942 }
1943
1944 if(param & ISO14A_NO_DISCONNECT) {
1945 return;
1946 }
1947
1948 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1949 LEDsoff();
1950 }
1951
1952
1953 // Determine the distance between two nonces.
1954 // Assume that the difference is small, but we don't know which is first.
1955 // Therefore try in alternating directions.
1956 int32_t dist_nt(uint32_t nt1, uint32_t nt2) {
1957
1958 uint16_t i;
1959 uint32_t nttmp1, nttmp2;
1960
1961 if (nt1 == nt2) return 0;
1962
1963 nttmp1 = nt1;
1964 nttmp2 = nt2;
1965
1966 for (i = 1; i < 32768; i++) {
1967 nttmp1 = prng_successor(nttmp1, 1);
1968 if (nttmp1 == nt2) return i;
1969 nttmp2 = prng_successor(nttmp2, 1);
1970 if (nttmp2 == nt1) return -i;
1971 }
1972
1973 return(-99999); // either nt1 or nt2 are invalid nonces
1974 }
1975
1976
1977 //-----------------------------------------------------------------------------
1978 // Recover several bits of the cypher stream. This implements (first stages of)
1979 // the algorithm described in "The Dark Side of Security by Obscurity and
1980 // Cloning MiFare Classic Rail and Building Passes, Anywhere, Anytime"
1981 // (article by Nicolas T. Courtois, 2009)
1982 //-----------------------------------------------------------------------------
1983 void ReaderMifare(bool first_try)
1984 {
1985 // Mifare AUTH
1986 uint8_t mf_auth[] = { 0x60,0x00,0xf5,0x7b };
1987 uint8_t mf_nr_ar[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 };
1988 static uint8_t mf_nr_ar3;
1989
1990 uint8_t receivedAnswer[MAX_MIFARE_FRAME_SIZE];
1991 uint8_t receivedAnswerPar[MAX_MIFARE_PARITY_SIZE];
1992
1993 // free eventually allocated BigBuf memory. We want all for tracing.
1994 BigBuf_free();
1995
1996 clear_trace();
1997 set_tracing(TRUE);
1998
1999 byte_t nt_diff = 0;
2000 uint8_t par[1] = {0}; // maximum 8 Bytes to be sent here, 1 byte parity is therefore enough
2001 static byte_t par_low = 0;
2002 bool led_on = TRUE;
2003 uint8_t uid[10] ={0};
2004 uint32_t cuid;
2005
2006 uint32_t nt = 0;
2007 uint32_t previous_nt = 0;
2008 static uint32_t nt_attacked = 0;
2009 byte_t par_list[8] = {0x00};
2010 byte_t ks_list[8] = {0x00};
2011
2012 static uint32_t sync_time;
2013 static uint32_t sync_cycles;
2014 int catch_up_cycles = 0;
2015 int last_catch_up = 0;
2016 uint16_t consecutive_resyncs = 0;
2017 int isOK = 0;
2018
2019 if (first_try) {
2020 mf_nr_ar3 = 0;
2021 iso14443a_setup(FPGA_HF_ISO14443A_READER_MOD);
2022 sync_time = GetCountSspClk() & 0xfffffff8;
2023 sync_cycles = 65536; // theory: Mifare Classic's random generator repeats every 2^16 cycles (and so do the nonces).
2024 nt_attacked = 0;
2025 nt = 0;
2026 par[0] = 0;
2027 }
2028 else {
2029 // we were unsuccessful on a previous call. Try another READER nonce (first 3 parity bits remain the same)
2030 mf_nr_ar3++;
2031 mf_nr_ar[3] = mf_nr_ar3;
2032 par[0] = par_low;
2033 }
2034
2035 LED_A_ON();
2036 LED_B_OFF();
2037 LED_C_OFF();
2038
2039
2040 for(uint16_t i = 0; TRUE; i++) {
2041
2042 WDT_HIT();
2043
2044 // Test if the action was cancelled
2045 if(BUTTON_PRESS()) {
2046 break;
2047 }
2048
2049 LED_C_ON();
2050
2051 if(!iso14443a_select_card(uid, NULL, &cuid)) {
2052 if (MF_DBGLEVEL >= 1) Dbprintf("Mifare: Can't select card");
2053 continue;
2054 }
2055
2056 sync_time = (sync_time & 0xfffffff8) + sync_cycles + catch_up_cycles;
2057 catch_up_cycles = 0;
2058
2059 // if we missed the sync time already, advance to the next nonce repeat
2060 while(GetCountSspClk() > sync_time) {
2061 sync_time = (sync_time & 0xfffffff8) + sync_cycles;
2062 }
2063
2064 // Transmit MIFARE_CLASSIC_AUTH at synctime. Should result in returning the same tag nonce (== nt_attacked)
2065 ReaderTransmit(mf_auth, sizeof(mf_auth), &sync_time);
2066
2067 // Receive the (4 Byte) "random" nonce
2068 if (!ReaderReceive(receivedAnswer, receivedAnswerPar)) {
2069 if (MF_DBGLEVEL >= 1) Dbprintf("Mifare: Couldn't receive tag nonce");
2070 continue;
2071 }
2072
2073 previous_nt = nt;
2074 nt = bytes_to_num(receivedAnswer, 4);
2075
2076 // Transmit reader nonce with fake par
2077 ReaderTransmitPar(mf_nr_ar, sizeof(mf_nr_ar), par, NULL);
2078
2079 if (first_try && previous_nt && !nt_attacked) { // we didn't calibrate our clock yet
2080 int nt_distance = dist_nt(previous_nt, nt);
2081 if (nt_distance == 0) {
2082 nt_attacked = nt;
2083 }
2084 else {
2085 if (nt_distance == -99999) { // invalid nonce received, try again
2086 continue;
2087 }
2088 sync_cycles = (sync_cycles - nt_distance);
2089 if (MF_DBGLEVEL >= 3) Dbprintf("calibrating in cycle %d. nt_distance=%d, Sync_cycles: %d\n", i, nt_distance, sync_cycles);
2090 continue;
2091 }
2092 }
2093
2094 if ((nt != nt_attacked) && nt_attacked) { // we somehow lost sync. Try to catch up again...
2095 catch_up_cycles = -dist_nt(nt_attacked, nt);
2096 if (catch_up_cycles == 99999) { // invalid nonce received. Don't resync on that one.
2097 catch_up_cycles = 0;
2098 continue;
2099 }
2100 if (catch_up_cycles == last_catch_up) {
2101 consecutive_resyncs++;
2102 }
2103 else {
2104 last_catch_up = catch_up_cycles;
2105 consecutive_resyncs = 0;
2106 }
2107 if (consecutive_resyncs < 3) {
2108 if (MF_DBGLEVEL >= 3) Dbprintf("Lost sync in cycle %d. nt_distance=%d. Consecutive Resyncs = %d. Trying one time catch up...\n", i, -catch_up_cycles, consecutive_resyncs);
2109 }
2110 else {
2111 sync_cycles = sync_cycles + catch_up_cycles;
2112 if (MF_DBGLEVEL >= 3) Dbprintf("Lost sync in cycle %d for the fourth time consecutively (nt_distance = %d). Adjusting sync_cycles to %d.\n", i, -catch_up_cycles, sync_cycles);
2113 }
2114 continue;
2115 }
2116
2117 consecutive_resyncs = 0;
2118
2119 // Receive answer. This will be a 4 Bit NACK when the 8 parity bits are OK after decoding
2120 if (ReaderReceive(receivedAnswer, receivedAnswerPar))
2121 {
2122 catch_up_cycles = 8; // the PRNG is delayed by 8 cycles due to the NAC (4Bits = 0x05 encrypted) transfer
2123
2124 if (nt_diff == 0)
2125 {
2126 par_low = par[0] & 0xE0; // there is no need to check all parities for other nt_diff. Parity Bits for mf_nr_ar[0..2] won't change
2127 }
2128
2129 led_on = !led_on;
2130 if(led_on) LED_B_ON(); else LED_B_OFF();
2131
2132 par_list[nt_diff] = SwapBits(par[0], 8);
2133 ks_list[nt_diff] = receivedAnswer[0] ^ 0x05;
2134
2135 // Test if the information is complete
2136 if (nt_diff == 0x07) {
2137 isOK = 1;
2138 break;
2139 }
2140
2141 nt_diff = (nt_diff + 1) & 0x07;
2142 mf_nr_ar[3] = (mf_nr_ar[3] & 0x1F) | (nt_diff << 5);
2143 par[0] = par_low;
2144 } else {
2145 if (nt_diff == 0 && first_try)
2146 {
2147 par[0]++;
2148 } else {
2149 par[0] = ((par[0] & 0x1F) + 1) | par_low;
2150 }
2151 }
2152 }
2153
2154
2155 mf_nr_ar[3] &= 0x1F;
2156
2157 byte_t buf[28];
2158 memcpy(buf + 0, uid, 4);
2159 num_to_bytes(nt, 4, buf + 4);
2160 memcpy(buf + 8, par_list, 8);
2161 memcpy(buf + 16, ks_list, 8);
2162 memcpy(buf + 24, mf_nr_ar, 4);
2163
2164 cmd_send(CMD_ACK,isOK,0,0,buf,28);
2165
2166 // Thats it...
2167 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
2168 LEDsoff();
2169
2170 set_tracing(FALSE);
2171 }
2172
2173 /**
2174 *MIFARE 1K simulate.
2175 *
2176 *@param flags :
2177 * FLAG_INTERACTIVE - In interactive mode, we are expected to finish the operation with an ACK
2178 * 4B_FLAG_UID_IN_DATA - means that there is a 4-byte UID in the data-section, we're expected to use that
2179 * 7B_FLAG_UID_IN_DATA - means that there is a 7-byte UID in the data-section, we're expected to use that
2180 * FLAG_NR_AR_ATTACK - means we should collect NR_AR responses for bruteforcing later
2181 *@param exitAfterNReads, exit simulation after n blocks have been read, 0 is inifite
2182 */
2183 void Mifare1ksim(uint8_t flags, uint8_t exitAfterNReads, uint8_t arg2, uint8_t *datain)
2184 {
2185 int cardSTATE = MFEMUL_NOFIELD;
2186 int _7BUID = 0;
2187 int vHf = 0; // in mV
2188 int res;
2189 uint32_t selTimer = 0;
2190 uint32_t authTimer = 0;
2191 uint16_t len = 0;
2192 uint8_t cardWRBL = 0;
2193 uint8_t cardAUTHSC = 0;
2194 uint8_t cardAUTHKEY = 0xff; // no authentication
2195 uint32_t cardRr = 0;
2196 uint32_t cuid = 0;
2197 //uint32_t rn_enc = 0;
2198 uint32_t ans = 0;
2199 uint32_t cardINTREG = 0;
2200 uint8_t cardINTBLOCK = 0;
2201 struct Crypto1State mpcs = {0, 0};
2202 struct Crypto1State *pcs;
2203 pcs = &mpcs;
2204 uint32_t numReads = 0;//Counts numer of times reader read a block
2205 uint8_t receivedCmd[MAX_MIFARE_FRAME_SIZE];
2206 uint8_t receivedCmd_par[MAX_MIFARE_PARITY_SIZE];
2207 uint8_t response[MAX_MIFARE_FRAME_SIZE];
2208 uint8_t response_par[MAX_MIFARE_PARITY_SIZE];
2209
2210 uint8_t rATQA[] = {0x04, 0x00}; // Mifare classic 1k 4BUID
2211 uint8_t rUIDBCC1[] = {0xde, 0xad, 0xbe, 0xaf, 0x62};
2212 uint8_t rUIDBCC2[] = {0xde, 0xad, 0xbe, 0xaf, 0x62}; // !!!
2213 uint8_t rSAK[] = {0x08, 0xb6, 0xdd};
2214 uint8_t rSAK1[] = {0x04, 0xda, 0x17};
2215
2216 uint8_t rAUTH_NT[] = {0x01, 0x02, 0x03, 0x04};
2217 uint8_t rAUTH_AT[] = {0x00, 0x00, 0x00, 0x00};
2218
2219 //Here, we collect UID,NT,AR,NR,UID2,NT2,AR2,NR2
2220 // This can be used in a reader-only attack.
2221 // (it can also be retrieved via 'hf 14a list', but hey...
2222 uint32_t ar_nr_responses[] = {0,0,0,0,0,0,0,0};
2223 uint8_t ar_nr_collected = 0;
2224
2225 // free eventually allocated BigBuf memory but keep Emulator Memory
2226 BigBuf_free_keep_EM();
2227
2228 // clear trace
2229 clear_trace();
2230 set_tracing(TRUE);
2231
2232 // Authenticate response - nonce
2233 uint32_t nonce = bytes_to_num(rAUTH_NT, 4);
2234
2235 //-- Determine the UID
2236 // Can be set from emulator memory, incoming data
2237 // and can be 7 or 4 bytes long
2238 if (flags & FLAG_4B_UID_IN_DATA)
2239 {
2240 // 4B uid comes from data-portion of packet
2241 memcpy(rUIDBCC1,datain,4);
2242 rUIDBCC1[4] = rUIDBCC1[0] ^ rUIDBCC1[1] ^ rUIDBCC1[2] ^ rUIDBCC1[3];
2243
2244 } else if (flags & FLAG_7B_UID_IN_DATA) {
2245 // 7B uid comes from data-portion of packet
2246 memcpy(&rUIDBCC1[1],datain,3);
2247 memcpy(rUIDBCC2, datain+3, 4);
2248 _7BUID = true;
2249 } else {
2250 // get UID from emul memory
2251 emlGetMemBt(receivedCmd, 7, 1);
2252 _7BUID = !(receivedCmd[0] == 0x00);
2253 if (!_7BUID) { // ---------- 4BUID
2254 emlGetMemBt(rUIDBCC1, 0, 4);
2255 } else { // ---------- 7BUID
2256 emlGetMemBt(&rUIDBCC1[1], 0, 3);
2257 emlGetMemBt(rUIDBCC2, 3, 4);
2258 }
2259 }
2260
2261 /*
2262 * Regardless of what method was used to set the UID, set fifth byte and modify
2263 * the ATQA for 4 or 7-byte UID
2264 */
2265 rUIDBCC1[4] = rUIDBCC1[0] ^ rUIDBCC1[1] ^ rUIDBCC1[2] ^ rUIDBCC1[3];
2266 if (_7BUID) {
2267 rATQA[0] = 0x44;
2268 rUIDBCC1[0] = 0x88;
2269 rUIDBCC2[4] = rUIDBCC2[0] ^ rUIDBCC2[1] ^ rUIDBCC2[2] ^ rUIDBCC2[3];
2270 }
2271
2272 // We need to listen to the high-frequency, peak-detected path.
2273 iso14443a_setup(FPGA_HF_ISO14443A_TAGSIM_LISTEN);
2274
2275
2276 if (MF_DBGLEVEL >= 1) {
2277 if (!_7BUID) {
2278 Dbprintf("4B UID: %02x%02x%02x%02x",
2279 rUIDBCC1[0], rUIDBCC1[1], rUIDBCC1[2], rUIDBCC1[3]);
2280 } else {
2281 Dbprintf("7B UID: (%02x)%02x%02x%02x%02x%02x%02x%02x",
2282 rUIDBCC1[0], rUIDBCC1[1], rUIDBCC1[2], rUIDBCC1[3],
2283 rUIDBCC2[0], rUIDBCC2[1] ,rUIDBCC2[2], rUIDBCC2[3]);
2284 }
2285 }
2286
2287 bool finished = FALSE;
2288 while (!BUTTON_PRESS() && !finished) {
2289 WDT_HIT();
2290
2291 // find reader field
2292 if (cardSTATE == MFEMUL_NOFIELD) {
2293 vHf = (MAX_ADC_HF_VOLTAGE * AvgAdc(ADC_CHAN_HF)) >> 10;
2294 if (vHf > MF_MINFIELDV) {
2295 cardSTATE_TO_IDLE();
2296 LED_A_ON();
2297 }
2298 }
2299 if(cardSTATE == MFEMUL_NOFIELD) continue;
2300
2301 //Now, get data
2302
2303 res = EmGetCmd(receivedCmd, &len, receivedCmd_par);
2304 if (res == 2) { //Field is off!
2305 cardSTATE = MFEMUL_NOFIELD;
2306 LEDsoff();
2307 continue;
2308 } else if (res == 1) {
2309 break; //return value 1 means button press
2310 }
2311
2312 // REQ or WUP request in ANY state and WUP in HALTED state
2313 if (len == 1 && ((receivedCmd[0] == 0x26 && cardSTATE != MFEMUL_HALTED) || receivedCmd[0] == 0x52)) {
2314 selTimer = GetTickCount();
2315 EmSendCmdEx(rATQA, sizeof(rATQA), (receivedCmd[0] == 0x52));
2316 cardSTATE = MFEMUL_SELECT1;
2317
2318 // init crypto block
2319 LED_B_OFF();
2320 LED_C_OFF();
2321 crypto1_destroy(pcs);
2322 cardAUTHKEY = 0xff;
2323 continue;
2324 }
2325
2326 switch (cardSTATE) {
2327 case MFEMUL_NOFIELD:
2328 case MFEMUL_HALTED:
2329 case MFEMUL_IDLE:{
2330 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2331 break;
2332 }
2333 case MFEMUL_SELECT1:{
2334 // select all
2335 if (len == 2 && (receivedCmd[0] == 0x93 && receivedCmd[1] == 0x20)) {
2336 if (MF_DBGLEVEL >= 4) Dbprintf("SELECT ALL received");
2337 EmSendCmd(rUIDBCC1, sizeof(rUIDBCC1));
2338 break;
2339 }
2340
2341 if (MF_DBGLEVEL >= 4 && len == 9 && receivedCmd[0] == 0x93 && receivedCmd[1] == 0x70 )
2342 {
2343 Dbprintf("SELECT %02x%02x%02x%02x received",receivedCmd[2],receivedCmd[3],receivedCmd[4],receivedCmd[5]);
2344 }
2345 // select card
2346 if (len == 9 &&
2347 (receivedCmd[0] == 0x93 && receivedCmd[1] == 0x70 && memcmp(&receivedCmd[2], rUIDBCC1, 4) == 0)) {
2348 EmSendCmd(_7BUID?rSAK1:rSAK, _7BUID?sizeof(rSAK1):sizeof(rSAK));
2349 cuid = bytes_to_num(rUIDBCC1, 4);
2350 if (!_7BUID) {
2351 cardSTATE = MFEMUL_WORK;
2352 LED_B_ON();
2353 if (MF_DBGLEVEL >= 4) Dbprintf("--> WORK. anticol1 time: %d", GetTickCount() - selTimer);
2354 break;
2355 } else {
2356 cardSTATE = MFEMUL_SELECT2;
2357 }
2358 }
2359 break;
2360 }
2361 case MFEMUL_AUTH1:{
2362 if( len != 8)
2363 {
2364 cardSTATE_TO_IDLE();
2365 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2366 break;
2367 }
2368
2369 uint32_t ar = bytes_to_num(receivedCmd, 4);
2370 uint32_t nr = bytes_to_num(&receivedCmd[4], 4);
2371
2372 //Collect AR/NR
2373 if(ar_nr_collected < 2){
2374 if(ar_nr_responses[2] != ar)
2375 {// Avoid duplicates... probably not necessary, ar should vary.
2376 ar_nr_responses[ar_nr_collected*4] = cuid;
2377 ar_nr_responses[ar_nr_collected*4+1] = nonce;
2378 ar_nr_responses[ar_nr_collected*4+2] = ar;
2379 ar_nr_responses[ar_nr_collected*4+3] = nr;
2380 ar_nr_collected++;
2381 }
2382 }
2383
2384 // --- crypto
2385 crypto1_word(pcs, ar , 1);
2386 cardRr = nr ^ crypto1_word(pcs, 0, 0);
2387
2388 // test if auth OK
2389 if (cardRr != prng_successor(nonce, 64)){
2390 if (MF_DBGLEVEL >= 2) Dbprintf("AUTH FAILED for sector %d with key %c. cardRr=%08x, succ=%08x",
2391 cardAUTHSC, cardAUTHKEY == 0 ? 'A' : 'B',
2392 cardRr, prng_successor(nonce, 64));
2393 // Shouldn't we respond anything here?
2394 // Right now, we don't nack or anything, which causes the
2395 // reader to do a WUPA after a while. /Martin
2396 // -- which is the correct response. /piwi
2397 cardSTATE_TO_IDLE();
2398 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2399 break;
2400 }
2401
2402 ans = prng_successor(nonce, 96) ^ crypto1_word(pcs, 0, 0);
2403
2404 num_to_bytes(ans, 4, rAUTH_AT);
2405 // --- crypto
2406 EmSendCmd(rAUTH_AT, sizeof(rAUTH_AT));
2407 LED_C_ON();
2408 cardSTATE = MFEMUL_WORK;
2409 if (MF_DBGLEVEL >= 4) Dbprintf("AUTH COMPLETED for sector %d with key %c. time=%d",
2410 cardAUTHSC, cardAUTHKEY == 0 ? 'A' : 'B',
2411 GetTickCount() - authTimer);
2412 break;
2413 }
2414 case MFEMUL_SELECT2:{
2415 if (!len) {
2416 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2417 break;
2418 }
2419 if (len == 2 && (receivedCmd[0] == 0x95 && receivedCmd[1] == 0x20)) {
2420 EmSendCmd(rUIDBCC2, sizeof(rUIDBCC2));
2421 break;
2422 }
2423
2424 // select 2 card
2425 if (len == 9 &&
2426 (receivedCmd[0] == 0x95 && receivedCmd[1] == 0x70 && memcmp(&receivedCmd[2], rUIDBCC2, 4) == 0)) {
2427 EmSendCmd(rSAK, sizeof(rSAK));
2428 cuid = bytes_to_num(rUIDBCC2, 4);
2429 cardSTATE = MFEMUL_WORK;
2430 LED_B_ON();
2431 if (MF_DBGLEVEL >= 4) Dbprintf("--> WORK. anticol2 time: %d", GetTickCount() - selTimer);
2432 break;
2433 }
2434
2435 // i guess there is a command). go into the work state.
2436 if (len != 4) {
2437 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2438 break;
2439 }
2440 cardSTATE = MFEMUL_WORK;
2441 //goto lbWORK;
2442 //intentional fall-through to the next case-stmt
2443 }
2444
2445 case MFEMUL_WORK:{
2446 if (len == 0) {
2447 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2448 break;
2449 }
2450
2451 bool encrypted_data = (cardAUTHKEY != 0xFF) ;
2452
2453 if(encrypted_data) {
2454 // decrypt seqence
2455 mf_crypto1_decrypt(pcs, receivedCmd, len);
2456 }
2457
2458 if (len == 4 && (receivedCmd[0] == 0x60 || receivedCmd[0] == 0x61)) {
2459 authTimer = GetTickCount();
2460 cardAUTHSC = receivedCmd[1] / 4; // received block num
2461 cardAUTHKEY = receivedCmd[0] - 0x60;
2462 crypto1_destroy(pcs);//Added by martin
2463 crypto1_create(pcs, emlGetKey(cardAUTHSC, cardAUTHKEY));
2464
2465 if (!encrypted_data) { // first authentication
2466 if (MF_DBGLEVEL >= 4) Dbprintf("Reader authenticating for block %d (0x%02x) with key %d",receivedCmd[1] ,receivedCmd[1],cardAUTHKEY );
2467
2468 crypto1_word(pcs, cuid ^ nonce, 0);//Update crypto state
2469 num_to_bytes(nonce, 4, rAUTH_AT); // Send nonce
2470 } else { // nested authentication
2471 if (MF_DBGLEVEL >= 4) Dbprintf("Reader doing nested authentication for block %d (0x%02x) with key %d",receivedCmd[1] ,receivedCmd[1],cardAUTHKEY );
2472 ans = nonce ^ crypto1_word(pcs, cuid ^ nonce, 0);
2473 num_to_bytes(ans, 4, rAUTH_AT);
2474 }
2475
2476 EmSendCmd(rAUTH_AT, sizeof(rAUTH_AT));
2477 //Dbprintf("Sending rAUTH %02x%02x%02x%02x", rAUTH_AT[0],rAUTH_AT[1],rAUTH_AT[2],rAUTH_AT[3]);
2478 cardSTATE = MFEMUL_AUTH1;
2479 break;
2480 }
2481
2482 // rule 13 of 7.5.3. in ISO 14443-4. chaining shall be continued
2483 // BUT... ACK --> NACK
2484 if (len == 1 && receivedCmd[0] == CARD_ACK) {
2485 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2486 break;
2487 }
2488
2489 // rule 12 of 7.5.3. in ISO 14443-4. R(NAK) --> R(ACK)
2490 if (len == 1 && receivedCmd[0] == CARD_NACK_NA) {
2491 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2492 break;
2493 }
2494
2495 if(len != 4) {
2496 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2497 break;
2498 }
2499
2500 if(receivedCmd[0] == 0x30 // read block
2501 || receivedCmd[0] == 0xA0 // write block
2502 || receivedCmd[0] == 0xC0 // inc
2503 || receivedCmd[0] == 0xC1 // dec
2504 || receivedCmd[0] == 0xC2 // restore
2505 || receivedCmd[0] == 0xB0) { // transfer
2506 if (receivedCmd[1] >= 16 * 4) {
2507 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2508 if (MF_DBGLEVEL >= 2) Dbprintf("Reader tried to operate (0x%02) on out of range block: %d (0x%02x), nacking",receivedCmd[0],receivedCmd[1],receivedCmd[1]);
2509 break;
2510 }
2511
2512 if (receivedCmd[1] / 4 != cardAUTHSC) {
2513 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2514 if (MF_DBGLEVEL >= 2) Dbprintf("Reader tried to operate (0x%02) on block (0x%02x) not authenticated for (0x%02x), nacking",receivedCmd[0],receivedCmd[1],cardAUTHSC);
2515 break;
2516 }
2517 }
2518 // read block
2519 if (receivedCmd[0] == 0x30) {
2520 if (MF_DBGLEVEL >= 4) {
2521 Dbprintf("Reader reading block %d (0x%02x)",receivedCmd[1],receivedCmd[1]);
2522 }
2523 emlGetMem(response, receivedCmd[1], 1);
2524 AppendCrc14443a(response, 16);
2525 mf_crypto1_encrypt(pcs, response, 18, response_par);
2526 EmSendCmdPar(response, 18, response_par);
2527 numReads++;
2528 if(exitAfterNReads > 0 && numReads == exitAfterNReads) {
2529 Dbprintf("%d reads done, exiting", numReads);
2530 finished = true;
2531 }
2532 break;
2533 }
2534 // write block
2535 if (receivedCmd[0] == 0xA0) {
2536 if (MF_DBGLEVEL >= 4) Dbprintf("RECV 0xA0 write block %d (%02x)",receivedCmd[1],receivedCmd[1]);
2537 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2538 cardSTATE = MFEMUL_WRITEBL2;
2539 cardWRBL = receivedCmd[1];
2540 break;
2541 }
2542 // increment, decrement, restore
2543 if (receivedCmd[0] == 0xC0 || receivedCmd[0] == 0xC1 || receivedCmd[0] == 0xC2) {
2544 if (MF_DBGLEVEL >= 4) Dbprintf("RECV 0x%02x inc(0xC1)/dec(0xC0)/restore(0xC2) block %d (%02x)",receivedCmd[0],receivedCmd[1],receivedCmd[1]);
2545 if (emlCheckValBl(receivedCmd[1])) {
2546 if (MF_DBGLEVEL >= 2) Dbprintf("Reader tried to operate on block, but emlCheckValBl failed, nacking");
2547 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2548 break;
2549 }
2550 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2551 if (receivedCmd[0] == 0xC1)
2552 cardSTATE = MFEMUL_INTREG_INC;
2553 if (receivedCmd[0] == 0xC0)
2554 cardSTATE = MFEMUL_INTREG_DEC;
2555 if (receivedCmd[0] == 0xC2)
2556 cardSTATE = MFEMUL_INTREG_REST;
2557 cardWRBL = receivedCmd[1];
2558 break;
2559 }
2560 // transfer
2561 if (receivedCmd[0] == 0xB0) {
2562 if (MF_DBGLEVEL >= 4) Dbprintf("RECV 0x%02x transfer block %d (%02x)",receivedCmd[0],receivedCmd[1],receivedCmd[1]);
2563 if (emlSetValBl(cardINTREG, cardINTBLOCK, receivedCmd[1]))
2564 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2565 else
2566 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2567 break;
2568 }
2569 // halt
2570 if (receivedCmd[0] == 0x50 && receivedCmd[1] == 0x00) {
2571 LED_B_OFF();
2572 LED_C_OFF();
2573 cardSTATE = MFEMUL_HALTED;
2574 if (MF_DBGLEVEL >= 4) Dbprintf("--> HALTED. Selected time: %d ms", GetTickCount() - selTimer);
2575 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2576 break;
2577 }
2578 // RATS
2579 if (receivedCmd[0] == 0xe0) {//RATS
2580 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2581 break;
2582 }
2583 // command not allowed
2584 if (MF_DBGLEVEL >= 4) Dbprintf("Received command not allowed, nacking");
2585 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2586 break;
2587 }
2588 case MFEMUL_WRITEBL2:{
2589 if (len == 18){
2590 mf_crypto1_decrypt(pcs, receivedCmd, len);
2591 emlSetMem(receivedCmd, cardWRBL, 1);
2592 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2593 cardSTATE = MFEMUL_WORK;
2594 } else {
2595 cardSTATE_TO_IDLE();
2596 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2597 }
2598 break;
2599 }
2600
2601 case MFEMUL_INTREG_INC:{
2602 mf_crypto1_decrypt(pcs, receivedCmd, len);
2603 memcpy(&ans, receivedCmd, 4);
2604 if (emlGetValBl(&cardINTREG, &cardINTBLOCK, cardWRBL)) {
2605 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2606 cardSTATE_TO_IDLE();
2607 break;
2608 }
2609 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2610 cardINTREG = cardINTREG + ans;
2611 cardSTATE = MFEMUL_WORK;
2612 break;
2613 }
2614 case MFEMUL_INTREG_DEC:{
2615 mf_crypto1_decrypt(pcs, receivedCmd, len);
2616 memcpy(&ans, receivedCmd, 4);
2617 if (emlGetValBl(&cardINTREG, &cardINTBLOCK, cardWRBL)) {
2618 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2619 cardSTATE_TO_IDLE();
2620 break;
2621 }
2622 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2623 cardINTREG = cardINTREG - ans;
2624 cardSTATE = MFEMUL_WORK;
2625 break;
2626 }
2627 case MFEMUL_INTREG_REST:{
2628 mf_crypto1_decrypt(pcs, receivedCmd, len);
2629 memcpy(&ans, receivedCmd, 4);
2630 if (emlGetValBl(&cardINTREG, &cardINTBLOCK, cardWRBL)) {
2631 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2632 cardSTATE_TO_IDLE();
2633 break;
2634 }
2635 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2636 cardSTATE = MFEMUL_WORK;
2637 break;
2638 }
2639 }
2640 }
2641
2642 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
2643 LEDsoff();
2644
2645 if(flags & FLAG_INTERACTIVE)// Interactive mode flag, means we need to send ACK
2646 {
2647 //May just aswell send the collected ar_nr in the response aswell
2648 cmd_send(CMD_ACK,CMD_SIMULATE_MIFARE_CARD,0,0,&ar_nr_responses,ar_nr_collected*4*4);
2649 }
2650
2651 if(flags & FLAG_NR_AR_ATTACK)
2652 {
2653 if(ar_nr_collected > 1) {
2654 Dbprintf("Collected two pairs of AR/NR which can be used to extract keys from reader:");
2655 Dbprintf("../tools/mfkey/mfkey32 %08x %08x %08x %08x %08x %08x",
2656 ar_nr_responses[0], // UID
2657 ar_nr_responses[1], //NT
2658 ar_nr_responses[2], //AR1
2659 ar_nr_responses[3], //NR1
2660 ar_nr_responses[6], //AR2
2661 ar_nr_responses[7] //NR2
2662 );
2663 } else {
2664 Dbprintf("Failed to obtain two AR/NR pairs!");
2665 if(ar_nr_collected >0) {
2666 Dbprintf("Only got these: UID=%08x, nonce=%08x, AR1=%08x, NR1=%08x",
2667 ar_nr_responses[0], // UID
2668 ar_nr_responses[1], //NT
2669 ar_nr_responses[2], //AR1
2670 ar_nr_responses[3] //NR1
2671 );
2672 }
2673 }
2674 }
2675 if (MF_DBGLEVEL >= 1) Dbprintf("Emulator stopped. Tracing: %d trace length: %d ", tracing, BigBuf_get_traceLen());
2676
2677 }
2678
2679
2680
2681 //-----------------------------------------------------------------------------
2682 // MIFARE sniffer.
2683 //
2684 //-----------------------------------------------------------------------------
2685 void RAMFUNC SniffMifare(uint8_t param) {
2686 // param:
2687 // bit 0 - trigger from first card answer
2688 // bit 1 - trigger from first reader 7-bit request
2689
2690 // C(red) A(yellow) B(green)
2691 LEDsoff();
2692 // init trace buffer
2693 clear_trace();
2694 set_tracing(TRUE);
2695
2696 // The command (reader -> tag) that we're receiving.
2697 // The length of a received command will in most cases be no more than 18 bytes.
2698 // So 32 should be enough!
2699 uint8_t receivedCmd[MAX_MIFARE_FRAME_SIZE];
2700 uint8_t receivedCmdPar[MAX_MIFARE_PARITY_SIZE];
2701 // The response (tag -> reader) that we're receiving.
2702 uint8_t receivedResponse[MAX_MIFARE_FRAME_SIZE];
2703 uint8_t receivedResponsePar[MAX_MIFARE_PARITY_SIZE];
2704
2705 // As we receive stuff, we copy it from receivedCmd or receivedResponse
2706 // into trace, along with its length and other annotations.
2707 //uint8_t *trace = (uint8_t *)BigBuf;
2708
2709 // free eventually allocated BigBuf memory
2710 BigBuf_free();
2711 // allocate the DMA buffer, used to stream samples from the FPGA
2712 uint8_t *dmaBuf = BigBuf_malloc(DMA_BUFFER_SIZE);
2713 uint8_t *data = dmaBuf;
2714 uint8_t previous_data = 0;
2715 int maxDataLen = 0;
2716 int dataLen = 0;
2717 bool ReaderIsActive = FALSE;
2718 bool TagIsActive = FALSE;
2719
2720 iso14443a_setup(FPGA_HF_ISO14443A_SNIFFER);
2721
2722 // Set up the demodulator for tag -> reader responses.
2723 DemodInit(receivedResponse, receivedResponsePar);
2724
2725 // Set up the demodulator for the reader -> tag commands
2726 UartInit(receivedCmd, receivedCmdPar);
2727
2728 // Setup for the DMA.
2729 FpgaSetupSscDma((uint8_t *)dmaBuf, DMA_BUFFER_SIZE); // set transfer address and number of bytes. Start transfer.
2730
2731 LED_D_OFF();
2732
2733 // init sniffer
2734 MfSniffInit();
2735
2736 // And now we loop, receiving samples.
2737 for(uint32_t sniffCounter = 0; TRUE; ) {
2738
2739 if(BUTTON_PRESS()) {
2740 DbpString("cancelled by button");
2741 break;
2742 }
2743
2744 LED_A_ON();
2745 WDT_HIT();
2746
2747 if ((sniffCounter & 0x0000FFFF) == 0) { // from time to time
2748 // check if a transaction is completed (timeout after 2000ms).
2749 // if yes, stop the DMA transfer and send what we have so far to the client
2750 if (MfSniffSend(2000)) {
2751 // Reset everything - we missed some sniffed data anyway while the DMA was stopped
2752 sniffCounter = 0;
2753 data = dmaBuf;
2754 maxDataLen = 0;
2755 ReaderIsActive = FALSE;
2756 TagIsActive = FALSE;
2757 FpgaSetupSscDma((uint8_t *)dmaBuf, DMA_BUFFER_SIZE); // set transfer address and number of bytes. Start transfer.
2758 }
2759 }
2760
2761 int register readBufDataP = data - dmaBuf; // number of bytes we have processed so far
2762 int register dmaBufDataP = DMA_BUFFER_SIZE - AT91C_BASE_PDC_SSC->PDC_RCR; // number of bytes already transferred
2763 if (readBufDataP <= dmaBufDataP){ // we are processing the same block of data which is currently being transferred
2764 dataLen = dmaBufDataP - readBufDataP; // number of bytes still to be processed
2765 } else {
2766 dataLen = DMA_BUFFER_SIZE - readBufDataP + dmaBufDataP; // number of bytes still to be processed
2767 }
2768 // test for length of buffer
2769 if(dataLen > maxDataLen) { // we are more behind than ever...
2770 maxDataLen = dataLen;
2771 if(dataLen > (9 * DMA_BUFFER_SIZE / 10)) {
2772 Dbprintf("blew circular buffer! dataLen=0x%x", dataLen);
2773 break;
2774 }
2775 }
2776 if(dataLen < 1) continue;
2777
2778 // primary buffer was stopped ( <-- we lost data!
2779 if (!AT91C_BASE_PDC_SSC->PDC_RCR) {
2780 AT91C_BASE_PDC_SSC->PDC_RPR = (uint32_t) dmaBuf;
2781 AT91C_BASE_PDC_SSC->PDC_RCR = DMA_BUFFER_SIZE;
2782 Dbprintf("RxEmpty ERROR!!! data length:%d", dataLen); // temporary
2783 }
2784 // secondary buffer sets as primary, secondary buffer was stopped
2785 if (!AT91C_BASE_PDC_SSC->PDC_RNCR) {
2786 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) dmaBuf;
2787 AT91C_BASE_PDC_SSC->PDC_RNCR = DMA_BUFFER_SIZE;
2788 }
2789
2790 LED_A_OFF();
2791
2792 if (sniffCounter & 0x01) {
2793
2794 if(!TagIsActive) { // no need to try decoding tag data if the reader is sending
2795 uint8_t readerdata = (previous_data & 0xF0) | (*data >> 4);
2796 if(MillerDecoding(readerdata, (sniffCounter-1)*4)) {
2797 LED_C_INV();
2798 if (MfSniffLogic(receivedCmd, Uart.len, Uart.parity, Uart.bitCount, TRUE)) break;
2799
2800 /* And ready to receive another command. */
2801 UartReset();
2802
2803 /* And also reset the demod code */
2804 DemodReset();
2805 }
2806 ReaderIsActive = (Uart.state != STATE_UNSYNCD);
2807 }
2808
2809 if(!ReaderIsActive) { // no need to try decoding tag data if the reader is sending
2810 uint8_t tagdata = (previous_data << 4) | (*data & 0x0F);
2811 if(ManchesterDecoding(tagdata, 0, (sniffCounter-1)*4)) {
2812 LED_C_INV();
2813
2814 if (MfSniffLogic(receivedResponse, Demod.len, Demod.parity, Demod.bitCount, FALSE)) break;
2815
2816 // And ready to receive another response.
2817 DemodReset();
2818 }
2819 TagIsActive = (Demod.state != DEMOD_UNSYNCD);
2820 }
2821 }
2822
2823 previous_data = *data;
2824 sniffCounter++;
2825 data++;
2826 if(data == dmaBuf + DMA_BUFFER_SIZE) {
2827 data = dmaBuf;
2828 }
2829
2830 } // main cycle
2831
2832 DbpString("COMMAND FINISHED");
2833
2834 FpgaDisableSscDma();
2835 MfSniffEnd();
2836
2837 Dbprintf("maxDataLen=%x, Uart.state=%x, Uart.len=%x", maxDataLen, Uart.state, Uart.len);
2838 LEDsoff();
2839 }
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