+ fc_div <= fc_div + 1;
+
+(* clock_signal = "yes" *) reg adc_clk; // sample frequency, always 16 * fc
+always @(ck_1356megb, xcorr_is_848, xcorr_quarter_freq, fc_div)
+ if (xcorr_is_848 & ~xcorr_quarter_freq) // fc = 847.5 kHz
+ adc_clk <= ck_1356megb;
+ else if (~xcorr_is_848 & ~xcorr_quarter_freq) // fc = 424.25 kHz
+ adc_clk <= fc_div[0];
+ else if (xcorr_is_848 & xcorr_quarter_freq) // fc = 212.125 kHz
+ adc_clk <= fc_div[1];
+ else // fc = 106.0625 kHz
+ adc_clk <= fc_div[2];
+