-//-----------------------------------------------------------------------------
-// Wait for commands from reader
-// Stop when button is pressed
-// Or return TRUE when command is captured
-//-----------------------------------------------------------------------------
-static int GetIClassCommandFromReader(uint8_t *received, int *len, int maxLen)
-{
- // Set FPGA mode to "simulated ISO 14443 tag", no modulation (listen
- // only, since we are receiving, not transmitting).
- // Signal field is off with the appropriate LED
- LED_D_OFF();
- FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_LISTEN);
-
- // Now run a `software UART' on the stream of incoming samples.
- Uart.output = received;
- Uart.byteCntMax = maxLen;
- Uart.state = STATE_UNSYNCD;
-
- for(;;) {
- WDT_HIT();
-
- if(BUTTON_PRESS()) return FALSE;
-
- if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
- AT91C_BASE_SSC->SSC_THR = 0x00;
- }
- if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
- uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
-
- if(OutOfNDecoding(b & 0x0f)) {
- *len = Uart.byteCnt;
- return TRUE;
- }
- }
- }
-}
-
-static uint8_t encode4Bits(const uint8_t b)
-{
- uint8_t c = b & 0xF;
- // OTA, the least significant bits first
- // The columns are
- // 1 - Bit value to send
- // 2 - Reversed (big-endian)
- // 3 - Encoded
- // 4 - Hex values
-
- switch(c){
- // 1 2 3 4
- case 15: return 0x55; // 1111 -> 1111 -> 01010101 -> 0x55
- case 14: return 0x95; // 1110 -> 0111 -> 10010101 -> 0x95
- case 13: return 0x65; // 1101 -> 1011 -> 01100101 -> 0x65
- case 12: return 0xa5; // 1100 -> 0011 -> 10100101 -> 0xa5
- case 11: return 0x59; // 1011 -> 1101 -> 01011001 -> 0x59
- case 10: return 0x99; // 1010 -> 0101 -> 10011001 -> 0x99
- case 9: return 0x69; // 1001 -> 1001 -> 01101001 -> 0x69
- case 8: return 0xa9; // 1000 -> 0001 -> 10101001 -> 0xa9
- case 7: return 0x56; // 0111 -> 1110 -> 01010110 -> 0x56
- case 6: return 0x96; // 0110 -> 0110 -> 10010110 -> 0x96
- case 5: return 0x66; // 0101 -> 1010 -> 01100110 -> 0x66
- case 4: return 0xa6; // 0100 -> 0010 -> 10100110 -> 0xa6
- case 3: return 0x5a; // 0011 -> 1100 -> 01011010 -> 0x5a
- case 2: return 0x9a; // 0010 -> 0100 -> 10011010 -> 0x9a
- case 1: return 0x6a; // 0001 -> 1000 -> 01101010 -> 0x6a
- default: return 0xaa; // 0000 -> 0000 -> 10101010 -> 0xaa
-
- }
-}
-
-//-----------------------------------------------------------------------------
-// Prepare tag messages
-//-----------------------------------------------------------------------------
-static void CodeIClassTagAnswer(const uint8_t *cmd, int len)
-{
-
- /*
- * SOF comprises 3 parts;
- * * An unmodulated time of 56.64 us
- * * 24 pulses of 423.75 KHz (fc/32)
- * * A logic 1, which starts with an unmodulated time of 18.88us
- * followed by 8 pulses of 423.75kHz (fc/32)
- *
- *
- * EOF comprises 3 parts:
- * - A logic 0 (which starts with 8 pulses of fc/32 followed by an unmodulated
- * time of 18.88us.
- * - 24 pulses of fc/32
- * - An unmodulated time of 56.64 us
- *
- *
- * A logic 0 starts with 8 pulses of fc/32
- * followed by an unmodulated time of 256/fc (~18,88us).
- *
- * A logic 0 starts with unmodulated time of 256/fc (~18,88us) followed by
- * 8 pulses of fc/32 (also 18.88us)
- *
- * The mode FPGA_HF_SIMULATOR_MODULATE_424K_8BIT which we use to simulate tag,
- * works like this.
- * - A 1-bit input to the FPGA becomes 8 pulses on 423.5kHz (fc/32) (18.88us).
- * - A 0-bit inptu to the FPGA becomes an unmodulated time of 18.88us
- *
- * In this mode the SOF can be written as 00011101 = 0x1D
- * The EOF can be written as 10111000 = 0xb8
- * A logic 1 is 01
- * A logic 0 is 10
- *
- * */
-
- int i;
-
projects / proxmark3-svn / blobdiff