]> git.zerfleddert.de Git - proxmark3-svn/blobdiff - armsrc/ldscript
fpga_compress: interleave (combine) fpga_lf.bit and fpga_hf.bit before compression.
[proxmark3-svn] / armsrc / ldscript
index 61eaa5d79c91ad46704bd4e98447d18020df4cc1..6175564dceff930950c4b272d3b60536cc1cbda2 100644 (file)
@@ -1,41 +1,66 @@
+/*
+-----------------------------------------------------------------------------
+ This code is licensed to you under the terms of the GNU GPL, version 2 or,
+ at your option, any later version. See the LICENSE.txt file for the text of
+ the license.
+-----------------------------------------------------------------------------
+ Linker script for the ARM binary
+-----------------------------------------------------------------------------
+*/
 INCLUDE ../common/ldscript.common
 
+PHDRS
+{
+       text PT_LOAD FLAGS(5);
+       data PT_LOAD;
+       bss PT_LOAD;
+}
+
 ENTRY(Vector)
 SECTIONS
 {
-       .fpgaimage : {
-               *(fpga_bit.data)
-       } >fpgaimage
-       .start : { *(.startos) } >osimage
-       .text : { 
+       .start : {
+               *(.startos)
+       } >osimage :text
+
+       .text : {
                *(.text)
                *(.text.*)
                *(.eh_frame)
                *(.glue_7)
                *(.glue_7t)
-               *(.rodata) 
-               *(.rodata*) 
-               *(.version_information)
-       } >osimage
-       __end_of_text__ = .;
-       
+       } >osimage :text
+
+       .rodata : {
+               *(.rodata)
+               *(.rodata.*)
+               *(fpga_all_bit.data)
+               KEEP(*(.version_information))
+       } >osimage :text
+
+       . = ALIGN(4);
+
        .data : {
-               __data_start__ = .;
-               __data_src_start__ = __end_of_text__; 
                *(.data)
                *(.data.*)
-               __data_end__ = .;
-       } >ram AT>osimage
+               *(.ramfunc)
+               . = ALIGN(4);
+       } >ram AT>osimage :data
+
+       __data_src_start__ = LOADADDR(.data);
+       __data_start__ = ADDR(.data);
+       __data_end__ = __data_start__ + SIZEOF(.data);
+       __os_size__ = SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.rodata);
        
        .bss : {
                __bss_start__ = .; 
                *(.bss)
                *(.bss.*) 
-       } >ram
-       . = ALIGN(32 / 8);
-       __bss_end__ = .;
+               . = ALIGN(4);
+               __bss_end__ = .;
+       } >ram AT>ram :bss
 
-       .commonarea (NOLOAD) : {
-               *(.commonarea)
-       } >commonarea
+       .commonarea (NOLOAD) : {
+               *(.commonarea)
+       } >commonarea :NONE
 }
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