// the license.
//-----------------------------------------------------------------------------
// Miscellaneous routines for low frequency tag operations.
-// Tags supported here so far are Texas Instruments (TI), HID
+// Tags supported here so far are Texas Instruments (TI), HID, EM4x05, EM410x
// Also routines for raw mode reading/simulating of LF waveform
//-----------------------------------------------------------------------------
#include "lfsampling.h"
#include "protocols.h"
#include "usb_cdc.h" // for usb_poll_validate_length
+#include "fpgaloader.h"
/**
* Function to do a modulation and then get samples.
*/
void ModThenAcquireRawAdcSamples125k(uint32_t delay_off, uint32_t period_0, uint32_t period_1, uint8_t *command)
{
+ // start timer
+ StartTicks();
- int divisor_used = 95; // 125 KHz
- // see if 'h' was specified
-
- if (command[strlen((char *) command) - 1] == 'h')
- divisor_used = 88; // 134.8 KHz
-
- sample_config sc = { 0,0,1, divisor_used, 0};
- setSamplingConfig(&sc);
- //clear read buffer
- BigBuf_Clear_keep_EM();
+ // use lf config settings
+ sample_config *sc = getSamplingConfig();
- /* Make sure the tag is reset */
+ // Make sure the tag is reset
FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
- SpinDelay(2500);
+ WaitMS(2500);
+
+ // clear read buffer (after fpga bitstream loaded...)
+ BigBuf_Clear_keep_EM();
- LFSetupFPGAForADC(sc.divisor, 1);
+ // power on
+ LFSetupFPGAForADC(sc->divisor, 1);
// And a little more time for the tag to fully power up
- SpinDelay(2000);
-
+ WaitMS(2000);
+ // if delay_off = 0 then just bitbang 1 = antenna on 0 = off for respective periods.
+ bool bitbang = delay_off == 0;
// now modulate the reader field
- while(*command != '\0' && *command != ' ') {
+
+ if (bitbang) {
+ // HACK it appears the loop and if statements take up about 7us so adjust waits accordingly...
+ uint8_t hack_cnt = 7;
+ if (period_0 < hack_cnt || period_1 < hack_cnt) {
+ DbpString("Warning periods cannot be less than 7us in bit bang mode");
+ FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
+ LED_D_OFF();
+ return;
+ }
+
+ // hack2 needed--- it appears to take about 8-16us to turn the antenna back on
+ // leading to ~ 1 to 2 125khz samples extra in every off period
+ // so we should test for last 0 before next 1 and reduce period_0 by this extra amount...
+ // but is this time different for every antenna or other hw builds??? more testing needed
+
+ // prime cmd_len to save time comparing strings while modulating
+ int cmd_len = 0;
+ while(command[cmd_len] != '\0' && command[cmd_len] != ' ')
+ cmd_len++;
+
+ int counter = 0;
+ bool off = false;
+ for (counter = 0; counter < cmd_len; counter++) {
+ // if cmd = 0 then turn field off
+ if (command[counter] == '0') {
+ // if field already off leave alone (affects timing otherwise)
+ if (off == false) {
+ FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
+ LED_D_OFF();
+ off = true;
+ }
+ // note we appear to take about 7us to switch over (or run the if statements/loop...)
+ WaitUS(period_0-hack_cnt);
+ // else if cmd = 1 then turn field on
+ } else {
+ // if field already on leave alone (affects timing otherwise)
+ if (off) {
+ FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
+ LED_D_ON();
+ off = false;
+ }
+ // note we appear to take about 7us to switch over (or run the if statements/loop...)
+ WaitUS(period_1-hack_cnt);
+ }
+ }
+ } else { // old mode of cmd read using delay as off period
+ while(*command != '\0' && *command != ' ') {
+ FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
+ LED_D_OFF();
+ WaitUS(delay_off);
+ FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc->divisor);
+ FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
+ LED_D_ON();
+ if(*(command++) == '0') {
+ WaitUS(period_0);
+ } else {
+ WaitUS(period_1);
+ }
+ }
FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
LED_D_OFF();
- SpinDelayUs(delay_off);
- FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc.divisor);
-
- FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
- LED_D_ON();
- if(*(command++) == '0')
- SpinDelayUs(period_0);
- else
- SpinDelayUs(period_1);
+ WaitUS(delay_off);
+ FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc->divisor);
}
- FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
- LED_D_OFF();
- SpinDelayUs(delay_off);
- FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc.divisor);
FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
// now do the read
DoAcquisition_config(false, 0);
+
+ // Turn off antenna
+ FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
+ // tell client we are done
+ cmd_send(CMD_ACK,0,0,0,0,0);
}
/* blank r/w tag data stream
int i;
uint8_t *tab = BigBuf_get_addr();
- //note this may destroy the bigbuf so be sure this is called before now...
- FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
+ //note FpgaDownloadAndGo destroys the bigbuf so be sure this is called before now...
+ //FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT);
AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK;
uint8_t wavesPerClock = clock/fc;
uint8_t mod = clock % fc; //modifier
uint8_t modAdj = fc/mod; //how often to apply modifier
- bool modAdjOk = !(fc % mod); //if (fc % mod==0) modAdjOk=TRUE;
+ bool modAdjOk = !(fc % mod); //if (fc % mod==0) modAdjOk=true;
// loop through clock - step field clock
for (uint8_t idx=0; idx < wavesPerClock; idx++){
// put 1/2 FC length 1's and 1/2 0's per field clock wave (to create the wave)
// prepare a waveform pattern in the buffer based on the ID given then
// simulate a HID tag until the button is pressed
-void CmdHIDsimTAG(int hi, int lo, int ledcontrol)
+void CmdHIDsimTAG(int hi2, int hi, int lo, int ledcontrol)
{
int n=0, i=0;
/*
nor 1 bits, they are special patterns (a = set of 12 fc8 and b = set of 10 fc10)
*/
- if (hi>0xFFF) {
- DbpString("Tags can only have 44 bits. - USE lf simfsk for larger tags");
+ if (hi2>0x0FFFFFFF) {
+ DbpString("Tags can only have 44 or 84 bits. - USE lf simfsk for larger tags");
return;
}
// set LF so we don't kill the bigbuf we are setting with simulation data.
fc(8, &n); fc(10, &n); // logical 0
WDT_HIT();
- // manchester encode bits 43 to 32
- for (i=11; i>=0; i--) {
- if ((i%4)==3) fc(0,&n);
- if ((hi>>i)&1) {
- fc(10, &n); fc(8, &n); // low-high transition
- } else {
- fc(8, &n); fc(10, &n); // high-low transition
+ if (hi2 > 0 || hi > 0xFFF){
+ // manchester encode bits 91 to 64 (91-84 are part of the header)
+ for (i=27; i>=0; i--) {
+ if ((i%4)==3) fc(0,&n);
+ if ((hi2>>i)&1) {
+ fc(10, &n); fc(8, &n); // low-high transition
+ } else {
+ fc(8, &n); fc(10, &n); // high-low transition
+ }
+ }
+ WDT_HIT();
+ // manchester encode bits 63 to 32
+ for (i=31; i>=0; i--) {
+ if ((i%4)==3) fc(0,&n);
+ if ((hi>>i)&1) {
+ fc(10, &n); fc(8, &n); // low-high transition
+ } else {
+ fc(8, &n); fc(10, &n); // high-low transition
+ }
+ }
+ } else {
+ // manchester encode bits 43 to 32
+ for (i=11; i>=0; i--) {
+ if ((i%4)==3) fc(0,&n);
+ if ((hi>>i)&1) {
+ fc(10, &n); fc(8, &n); // low-high transition
+ } else {
+ fc(8, &n); fc(10, &n); // high-low transition
+ }
}
}
for (i=0; i<size; i++){
if (BitStream[i] == curPhase){
- pskSimBit(carrier, &n, clk, &curPhase, FALSE);
+ pskSimBit(carrier, &n, clk, &curPhase, false);
} else {
- pskSimBit(carrier, &n, clk, &curPhase, TRUE);
+ pskSimBit(carrier, &n, clk, &curPhase, true);
}
}
Dbprintf("Simulating with Carrier: %d, clk: %d, invert: %d, n: %d",carrier, clk, invert, n);
}
// loop to get raw HID waveform then FSK demodulate the TAG ID from it
-void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
+void CmdHIDdemodFSK(int findone, int *high2, int *high, int *low, int ledcontrol)
{
uint8_t *dest = BigBuf_get_addr();
//const size_t sizeOfBigBuff = BigBuf_max_traceLen();
BigBuf_Clear_keep_EM();
while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
-
WDT_HIT();
if (ledcontrol) LED_A_ON();
idx = HIDdemodFSK(dest, &size, &hi2, &hi, &lo, &dummyIdx);
if (idx>0 && lo>0 && (size==96 || size==192)){
+ uint8_t bitlen = 0;
+ uint32_t fc = 0;
+ uint32_t cardnum = 0;
+ bool decoded = false;
+
// go over previously decoded manchester data and decode into usable tag ID
- if (hi2 != 0){ //extra large HID tags 88/192 bits
- Dbprintf("TAG ID: %x%08x%08x (%d)",
- (unsigned int) hi2, (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
- }else { //standard HID tags 44/96 bits
- //Dbprintf("TAG ID: %x%08x (%d)",(unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF); //old print cmd
- uint8_t bitlen = 0;
- uint32_t fc = 0;
- uint32_t cardnum = 0;
- if (((hi>>5)&1) == 1){//if bit 38 is set then < 37 bit format is used
- uint32_t lo2=0;
- lo2=(((hi & 31) << 12) | (lo>>20)); //get bits 21-37 to check for format len bit
- uint8_t idx3 = 1;
- while(lo2 > 1){ //find last bit set to 1 (format len bit)
- lo2=lo2 >> 1;
- idx3++;
- }
- bitlen = idx3+19;
- fc =0;
- cardnum=0;
- if(bitlen == 26){
- cardnum = (lo>>1)&0xFFFF;
- fc = (lo>>17)&0xFF;
- }
- if(bitlen == 37){
- cardnum = (lo>>1)&0x7FFFF;
- fc = ((hi&0xF)<<12)|(lo>>20);
- }
- if(bitlen == 34){
- cardnum = (lo>>1)&0xFFFF;
- fc= ((hi&1)<<15)|(lo>>17);
- }
- if(bitlen == 35){
- cardnum = (lo>>1)&0xFFFFF;
- fc = ((hi&1)<<11)|(lo>>21);
- }
+ if ((hi2 & 0x000FFFF) != 0){ //extra large HID tags 88/192 bits
+ uint32_t bp = hi2 & 0x000FFFFF;
+ bitlen = 63;
+ while (bp > 0) {
+ bp = bp >> 1;
+ bitlen++;
}
- else { //if bit 38 is not set then 37 bit format is used
- bitlen= 37;
- fc =0;
- cardnum=0;
- if(bitlen==37){
- cardnum = (lo>>1)&0x7FFFF;
- fc = ((hi&0xF)<<12)|(lo>>20);
- }
+ } else if ((hi >> 6) > 0) {
+ uint32_t bp = hi;
+ bitlen = 31;
+ while (bp > 0) {
+ bp = bp >> 1;
+ bitlen++;
+ }
+ } else if (((hi >> 5) & 1) == 0) {
+ bitlen = 37;
+ } else if ((hi & 0x0000001F) > 0 ) {
+ uint32_t bp = (hi & 0x0000001F);
+ bitlen = 31;
+ while (bp > 0) {
+ bp = bp >> 1;
+ bitlen++;
+ }
+ } else {
+ uint32_t bp = lo;
+ bitlen = 0;
+ while (bp > 0) {
+ bp = bp >> 1;
+ bitlen++;
}
- //Dbprintf("TAG ID: %x%08x (%d)",
- // (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
- Dbprintf("TAG ID: %x%08x (%d) - Format Len: %dbit - FC: %d - Card: %d",
- (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF,
- (unsigned int) bitlen, (unsigned int) fc, (unsigned int) cardnum);
}
+ switch (bitlen){
+ case 26:
+ cardnum = (lo>>1)&0xFFFF;
+ fc = (lo>>17)&0xFF;
+ decoded = true;
+ break;
+ case 35:
+ cardnum = (lo>>1)&0xFFFFF;
+ fc = ((hi&1)<<11)|(lo>>21);
+ decoded = true;
+ break;
+ }
+
+ if (hi2 != 0) //extra large HID tags 88/192 bits
+ Dbprintf("TAG ID: %x%08x%08x (%d)",
+ (unsigned int) hi2, (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
+ else
+ Dbprintf("TAG ID: %x%08x (%d)",
+ (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
+
+ if (decoded)
+ Dbprintf("Format Len: %dbits - FC: %d - Card: %d",
+ (unsigned int) bitlen, (unsigned int) fc, (unsigned int) cardnum);
+
if (findone){
if (ledcontrol) LED_A_OFF();
+ *high2 = hi2;
*high = hi;
*low = lo;
break;
#define WRITE_0 18*8 // was 144 // SPEC: 16*8 to 32*8 - typ 24*8 (or 24fc)
#define WRITE_1 50*8 // was 400 // SPEC: 48*8 to 64*8 - typ 56*8 (or 56fc) 432 for T55x7; 448 for E5550
#define READ_GAP 15*8
+// Long Leading Reference
+#define Reference_llr (136+18)*8 // Needs to be WRITR_0 + 136 clocks.
void TurnReadLFOn(int delay) {
FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
WaitUS(WRITE_GAP);
}
+void T55xxWrite_LLR (void)
+{
+ TurnReadLFOn (Reference_llr);
+ FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
+ WaitUS(WRITE_GAP);
+}
+
+#define START_GAPlz 31*8
+#define WRITE_GAPlz 20*8
+#define WRITElz_0 18*8
+#define WRITElz_1 40*8
+#define READ_GAP 15*8
+
+void T55xxWriteBit_Leading0(int bit) {
+ if (!bit)
+ TurnReadLFOn(WRITElz_0);
+ else
+ TurnReadLFOn(WRITElz_1);
+ FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
+ WaitUS(WRITE_GAPlz);
+// WaitUS(160);
+}
+
+#define START_GAP1of4 31*8 // SPEC: 1*8 to 50*8 - typ 10*8 (or 15fc)
+#define WRITE_GAP1of4 20*8 // SPEC: 1*8 to 20*8 - typ 10*8 (or 10fc)
+// 00 = reference // 8 * 8 - - 68 * 8
+#define WRITE1of4_00 18*8 // SPEC: 8*8 to 68*8 - typ 24*8 (or 24fc)
+#define WRITE1of4_01 34*8 // SPEC: dref+9 - dref+16 - dref+24
+#define WRITE1of4_10 50*8 // SPEC: dref+25 - dref+32 - dref+40
+#define WRITE1of4_11 66*8 // SPEC: dref+41 - dref+48 - dref+56
+#define READ1of4_GAP 15*8
+
+void T55xxWriteBit_1of4(int bits) {
+
+ switch (bits)
+ {
+ case 0 : TurnReadLFOn(WRITE1of4_00); break;
+ case 1 : TurnReadLFOn(WRITE1of4_01); break;
+ case 2 : TurnReadLFOn(WRITE1of4_10); break;
+ case 3 : TurnReadLFOn(WRITE1of4_11); break;
+ default:
+ TurnReadLFOn(WRITE1of4_00);
+ }
+
+ FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
+ WaitUS(WRITE_GAP1of4);
+// WaitUS(160);
+}
+
+void T55xxWriteBlockExt_Leading0 (uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t arg) {
+
+ LED_A_ON();
+ bool PwdMode = arg & 0x1;
+ uint8_t Page = (arg & 0x2)>>1;
+ bool testMode = arg & 0x4;
+ uint32_t i = 0;
+
+ // Set up FPGA, 125kHz
+ LFSetupFPGAForADC(95, true);
+ StartTicks();
+ // make sure tag is fully powered up...
+ WaitMS(5);
+ // Trigger T55x7 in mode.
+ FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
+
+ WaitUS(START_GAPlz);
+
+
+ /*
+ 0 : Leading Zero
+ 11 : Opcode
+ 00 : Fixed 00 if protected write (i.e. have password)
+ <32 bit Password>
+ 0 : Lock Bit
+ <32 bit data>
+ <3 bit addr>
+
+ Standard Write : 0 1p L <32 data bits> <3 bit addr>
+ 0 10 0 00000000000000000000000000000000 001
+ Protected Write: 0 1p 00 <32 pwd bits> L <32 data bits> <3 bit addr>
+ 0 10 00 00000000000000000000000000000000 0 00000000000000000000000000000000 001
+ Wake Up 0 10 00 <32 pwd bits>
+ Protected Read 0 1p 00 <32 pwd bits> 0 <3 bit addr>
+ Standard Read 0 1p 0 <3 bit addr>
+ Page 0/1 read 0 1p
+ Reset 0 00
+
+ */
+ T55xxWriteBit_Leading0 (0); //T55xxWriteBit(0);
+
+
+ if (testMode) Dbprintf("TestMODE");
+ // Std Opcode 10
+ T55xxWriteBit_Leading0 (testMode ? 0 : 1);
+ T55xxWriteBit_Leading0 (testMode ? 1 : Page); //Page 0
+
+
+ if (PwdMode) {
+ // Leading zero - insert two fixed 00 between opcode and password
+ T55xxWriteBit_Leading0 (0);
+ T55xxWriteBit_Leading0 (0);
+ // Send Pwd
+ for (i = 0x80000000; i != 0; i >>= 1)
+ T55xxWriteBit_Leading0 (Pwd & i);
+ }
+
+ // Send Lock bit
+ T55xxWriteBit_Leading0 (0);
+
+ // Send Data
+ for (i = 0x80000000; i != 0; i >>= 1)
+ T55xxWriteBit_Leading0(Data & i);
+
+ // Send Block number
+ for (i = 0x04; i != 0; i >>= 1)
+ T55xxWriteBit_Leading0 (Block & i);
+
+ // Perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550,
+ // so wait a little more)
+ // "there is a clock delay before programming"
+ // - programming takes ~5.6ms for t5577 ~18ms for E5550 or t5567
+ // so we should wait 1 clock + 5.6ms then read response?
+ // but we need to know we are dealing with t5577 vs t5567 vs e5550 (or q5) marshmellow...
+ if (testMode) {
+ //TESTMODE TIMING TESTS:
+ // <566us does nothing
+ // 566-568 switches between wiping to 0s and doing nothing
+ // 5184 wipes and allows 1 block to be programmed.
+ // indefinite power on wipes and then programs all blocks with bitshifted data sent.
+ TurnReadLFOn(5184);
+
+ } else {
+ TurnReadLFOn(20 * 1000);
+ //could attempt to do a read to confirm write took
+ // as the tag should repeat back the new block
+ // until it is reset, but to confirm it we would
+ // need to know the current block 0 config mode for
+ // modulation clock an other details to demod the response...
+ // response should be (for t55x7) a 0 bit then (ST if on)
+ // block data written in on repeat until reset.
+
+ //DoPartialAcquisition(20, true, 12000);
+ }
+
+ // turn field off
+ FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
+ LED_A_OFF();
+
+}
+void T55xxWriteBlockExt_1of4 (uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t arg) {
+
+ LED_A_ON();
+ bool PwdMode = arg & 0x1;
+ uint8_t Page = (arg & 0x2)>>1;
+ bool testMode = arg & 0x4;
+ int bitpos;
+ uint8_t bits;
+
+ // Set up FPGA, 125kHz
+ LFSetupFPGAForADC(95, true);
+ StartTicks();
+ // make sure tag is fully powered up...
+ WaitMS(5);
+ // Trigger T55x7 in mode.
+ FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
+
+
+ WaitUS(START_GAP1of4);
+
+
+ /*
+ 00 : 1 if 4
+ 11 : Opcode
+ 00 : Fixed 00 if protected write (i.e. have password)
+ <32 bit Password>
+ 0 : Lock Bit
+ <32 bit data>
+ <3 bit addr>
+
+ Standard Write : 00 1p L <32 data bits> <3 bit addr>
+ 00 10 0 00000000000000000000000000000000 001
+ Protected Write: 00 1p 00 <32 pwd bits> L <32 data bits> <3 bit addr>
+ 00 10 00 00000000000000000000000000000000 0 00000000000000000000000000000000 001
+ Wake Up 00 10 00 <32 pwd bits>
+ Protected Read 00 1p 00 <32 pwd bits> 0 <3 bit addr>
+ Standard Read 00 1p 0 <3 bit addr>
+ Page 0/1 read 00 1p
+ Reset 00 00
+
+ */
+ T55xxWriteBit_1of4 (0); //Send Reference 00
+
+ if (testMode) Dbprintf("TestMODE");
+ // Std Opcode 10
+ if (testMode) bits = 0; else bits = 2; // 0x or 1x
+ if (testMode) bits |= 1; else bits += (Page); // x0 or x1
+ T55xxWriteBit_1of4 (bits);
+
+ if (PwdMode) {
+ // 1 of 4 00 - insert two fixed 00 between opcode and password
+ T55xxWriteBit_1of4 (0); // 00
+
+ // Send Pwd
+ for (bitpos = 31; bitpos >= 1; bitpos -= 2) { // 2 bits at a time
+ bits = (((Pwd >> bitpos) & 1) << 1) + ((Pwd >> (bitpos-1)) & 1);
+ T55xxWriteBit_1of4 (bits);
+ }
+ }
+
+ // Send Lock bit
+ bits = 0; // Add lock bit (Not Set) to the next 2 bits
+
+ // Send Data - offset by 1 bit due to lock bit
+ // 2 bits at a time - Initilised with lock bit above
+ for (bitpos = 31; bitpos >= 1; bitpos -= 2) {
+ bits |= ((Data >> bitpos) & 1); // Add Low bit
+ T55xxWriteBit_1of4 (bits);
+ bits = ((Data >> (bitpos-1)) & 1) << 1; // Set next high bit
+ }
+
+ // Send Block number
+ bits |= ((Block >> 2) & 1);
+ T55xxWriteBit_1of4 (bits);
+ bits = (Block & 3);// 1) & 2) + (Block & 1);
+ T55xxWriteBit_1of4 (bits);
+
+ // Perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550,
+ // so wait a little more)
+ // "there is a clock delay before programming"
+ // - programming takes ~5.6ms for t5577 ~18ms for E5550 or t5567
+ // so we should wait 1 clock + 5.6ms then read response?
+ // but we need to know we are dealing with t5577 vs t5567 vs e5550 (or q5) marshmellow...
+ if (testMode) {
+ //TESTMODE TIMING TESTS:
+ // <566us does nothing
+ // 566-568 switches between wiping to 0s and doing nothing
+ // 5184 wipes and allows 1 block to be programmed.
+ // indefinite power on wipes and then programs all blocks with bitshifted data sent.
+ TurnReadLFOn(5184);
+
+ } else {
+ TurnReadLFOn(20 * 1000);
+ //could attempt to do a read to confirm write took
+ // as the tag should repeat back the new block
+ // until it is reset, but to confirm it we would
+ // need to know the current block 0 config mode for
+ // modulation clock an other details to demod the response...
+ // response should be (for t55x7) a 0 bit then (ST if on)
+ // block data written in on repeat until reset.
+
+ //DoPartialAcquisition(20, true, 12000);
+ }
+
+ // turn field off
+ FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
+ LED_A_OFF();
+
+}
+
// Send T5577 reset command then read stream (see if we can identify the start of the stream)
void T55xxResetRead(void) {
LED_A_ON();
TurnReadLFOn(READ_GAP);
// Acquisition
- DoPartialAcquisition(0, true, BigBuf_max_traceLen());
+ DoPartialAcquisition(0, true, BigBuf_max_traceLen(), 0);
// Turn the field off
FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
// Write one card block in page 0, no lock
void T55xxWriteBlock(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t arg) {
- T55xxWriteBlockExt(Data, Block, Pwd, arg);
+// arg 8 bit 00000000
+// 0000000x Password
+// 000000x0 Page
+// 00000x00 Test Mode
+// 000xx000 (0x18) where xx : 00 - Normal Write, 01 - Long Leading Reference
+// 10 - Leading 0, 11 - 1 of 4
+ uint8_t downlink_mode;
+
+ downlink_mode = (arg >> 3) & 0x03;
+
+ switch (downlink_mode)
+ {
+ case 0 : T55xxWriteBlockExt (Data, Block, Pwd, arg); break;
+ case 1 : T55xxWrite_LLR ();
+ T55xxWriteBlockExt (Data, Block, Pwd, arg);
+ break;
+ case 2 : T55xxWriteBlockExt_Leading0 (Data, Block, Pwd, arg); break;
+ case 3 : T55xxWriteBlockExt_1of4 (Data, Block, Pwd, arg); break;
+
+ default:
+ T55xxWriteBlockExt (Data, Block, Pwd, arg);
+ }
+
cmd_send(CMD_ACK,0,0,0,0,0);
}
// Read one card block in page [page]
-void T55xxReadBlock(uint16_t arg0, uint8_t Block, uint32_t Pwd) {
+void T55xxReadBlockExt (uint16_t arg0, uint8_t Block, uint32_t Pwd) {
LED_A_ON();
bool PwdMode = arg0 & 0x1;
uint8_t Page = (arg0 & 0x2) >> 1;
// Acquisition
// Now do the acquisition
- DoPartialAcquisition(0, true, 12000);
+ DoPartialAcquisition(0, true, 12000, 0);
// Turn the field off
FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
- cmd_send(CMD_ACK,0,0,0,0,0);
+// cmd_send(CMD_ACK,0,0,0,0,0);
+ LED_A_OFF();
+}
+
+void T55xxReadBlockExt_Leading0 (uint16_t arg0, uint8_t Block, uint32_t Pwd) {
+ LED_A_ON();
+ bool PwdMode = arg0 & 0x1;
+ uint8_t Page = (arg0 & 0x2) >> 1;
+ uint32_t i = 0;
+ bool RegReadMode = (Block == 0xFF);//regular read mode
+
+ //clear buffer now so it does not interfere with timing later
+ BigBuf_Clear_ext(false);
+
+ //make sure block is at max 7
+ Block &= 0x7;
+
+ // Set up FPGA, 125kHz to power up the tag
+ LFSetupFPGAForADC(95, true);
+ StartTicks();
+ // make sure tag is fully powered up...
+ WaitMS(5);
+ // Trigger T55x7 Direct Access Mode with start gap
+ FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
+ WaitUS(START_GAPlz);
+
+ T55xxWriteBit_Leading0 (0);
+
+ // Opcode 1[page]
+ T55xxWriteBit_Leading0 (1);
+ T55xxWriteBit_Leading0 (Page); //Page 0
+
+ if (PwdMode){
+ // Send Pwd
+ T55xxWriteBit_Leading0 (0);
+ T55xxWriteBit_Leading0 (0);
+
+ for (i = 0x80000000; i != 0; i >>= 1)
+ T55xxWriteBit_Leading0 (Pwd & i);
+ }
+ // Send a zero bit separation
+ T55xxWriteBit_Leading0(0);
+
+ // Send Block number (if direct access mode)
+ if (!RegReadMode)
+ for (i = 0x04; i != 0; i >>= 1)
+ T55xxWriteBit_Leading0(Block & i);
+
+ // Turn field on to read the response
+ // 137*8 seems to get to the start of data pretty well...
+ // but we want to go past the start and let the repeating data settle in...
+ TurnReadLFOn(210*8);
+
+ // Acquisition
+ // Now do the acquisition
+ DoPartialAcquisition(0, true, 12000, 0);
+
+ // Turn the field off
+ FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
+// cmd_send(CMD_ACK,0,0,0,0,0);
LED_A_OFF();
}
+void T55xxReadBlockExt_1of4 (uint16_t arg0, uint8_t Block, uint32_t Pwd) {
+ LED_A_ON();
+ bool PwdMode = arg0 & 0x1;
+ uint8_t Page = (arg0 & 0x2) >> 1;
+ //uint32_t i = 0;
+ bool RegReadMode = (Block == 0xFF);//regular read mode
+ uint8_t bits;
+ int bitpos;
+
+ //clear buffer now so it does not interfere with timing later
+ BigBuf_Clear_ext(false);
+
+ //make sure block is at max 7
+ Block &= 0x7;
+
+ // Set up FPGA, 125kHz to power up the tag
+ LFSetupFPGAForADC(95, true);
+ StartTicks();
+ // make sure tag is fully powered up...
+ WaitMS(5);
+ // Trigger T55x7 Direct Access Mode with start gap
+ FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
+ WaitUS(START_GAP1of4);
+
+ T55xxWriteBit_1of4 (0); // 2 Bit 00 leading reference
+
+ // Opcode 1[page]
+ bits = 2 + Page;
+ T55xxWriteBit_1of4 (bits);
+
+ if (PwdMode) {
+ // 1 of 4 00 - insert two fixed 00 between opcode and password
+ T55xxWriteBit_1of4 (0); // 00
+
+ // Send Pwd
+ for (bitpos = 31; bitpos >= 1; bitpos -= 2) { // 2 bits at a time
+ bits = (((Pwd >> bitpos) & 1) << 1) + ((Pwd >> (bitpos-1)) & 1);
+ T55xxWriteBit_1of4 (bits);
+ }
+ }
+
+ // Send Lock bit
+ bits = 0; // Add lock bit (Not Set) to the next 2 bits
+
+ // Send Block number (if direct access mode)
+ if (!RegReadMode){
+ // Send Block number
+ bits += ((Block >> 2) & 1);
+ T55xxWriteBit_1of4 (bits);
+ bits = (Block & 3); // + (Block & 1);
+ T55xxWriteBit_1of4 (bits);
+ }
+
+ // Turn field on to read the response
+ // 137*8 seems to get to the start of data pretty well...
+ // but we want to go past the start and let the repeating data settle in...
+ TurnReadLFOn(210*8);
+
+ // Acquisition
+ // Now do the acquisition
+ DoPartialAcquisition(0, true, 12000, 0);
+ FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
+// cmd_send(CMD_ACK,0,0,0,0,0);
+ LED_A_OFF();
+}
+
+void T55xxReadBlock (uint16_t arg0, uint8_t Block, uint32_t Pwd) {
+// arg0 16 bit 00000000
+// 0000000x Password
+// 000000x0 Page
+// 00000x00
+// 000xx000 (0x18) where xx : 00 - Normal Write, 01 - Long Leading Reference
+// 10 - Leading 0, 11 - 1 of 4
+ uint8_t downlink_mode;
+
+ downlink_mode = (arg0 >> 3) & 0x03;
+
+ // downlink mode id set to match the 2 bit as per Tech Sheet
+ switch (downlink_mode)
+ {
+ case 0 : T55xxReadBlockExt (arg0, Block, Pwd); break;
+ case 1 : T55xxWrite_LLR ();
+ T55xxReadBlockExt (arg0, Block, Pwd);
+ break;
+ case 2 : T55xxReadBlockExt_Leading0 (arg0, Block, Pwd); break;
+ case 3 : T55xxReadBlockExt_1of4 (arg0, Block, Pwd); break;
+ default:
+ T55xxReadBlockExt (arg0, Block, Pwd) ;
+ }
+
+// T55xxReadBlockExt (arg0, Block, Pwd) ;
+ cmd_send(CMD_ACK,0,0,0,0,0);
+}
+
void T55xxWakeUp(uint32_t Pwd){
LED_B_ON();
uint32_t i = 0;
}
}
-// Copy HID id to card and setup block 0 config
-void CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT) {
+// Copy a HID-like card (e.g. HID Proximity, Paradox) to a T55x7 compatible card
+void CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT, uint8_t preamble) {
uint32_t data[] = {0,0,0,0,0,0,0};
uint8_t last_block = 0;
}
// Build the 6 data blocks for supplied 84bit ID
last_block = 6;
- // load preamble (1D) & long format identifier (9E manchester encoded)
- data[1] = 0x1D96A900 | (manchesterEncode2Bytes((hi2 >> 16) & 0xF) & 0xFF);
+ // load preamble & long format identifier (9E manchester encoded)
+ data[1] = (preamble << 24) | 0x96A900 | (manchesterEncode2Bytes((hi2 >> 16) & 0xF) & 0xFF);
// load raw id from hi2, hi, lo to data blocks (manchester encoded)
data[2] = manchesterEncode2Bytes(hi2 & 0xFFFF);
data[3] = manchesterEncode2Bytes(hi >> 16);
data[4] = manchesterEncode2Bytes(hi & 0xFFFF);
data[5] = manchesterEncode2Bytes(lo >> 16);
data[6] = manchesterEncode2Bytes(lo & 0xFFFF);
- } else {
+ } else {
// Ensure no more than 44 bits supplied
if (hi>0xFFF) {
DbpString("Tags can only have 44 bits.");
// Build the 3 data blocks for supplied 44bit ID
last_block = 3;
// load preamble
- data[1] = 0x1D000000 | (manchesterEncode2Bytes(hi) & 0xFFFFFF);
+ data[1] = (preamble << 24) | (manchesterEncode2Bytes(hi) & 0xFFFFFF);
data[2] = manchesterEncode2Bytes(lo >> 16);
data[3] = manchesterEncode2Bytes(lo & 0xFFFF);
}
SendForward(fwd_bit_count);
WaitUS(400);
// Now do the acquisition
- DoPartialAcquisition(20, true, 6000);
+ DoPartialAcquisition(20, true, 6000, 1000);
FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
LED_A_OFF();
WaitUS(6500);
//Capture response if one exists
- DoPartialAcquisition(20, true, 6000);
+ DoPartialAcquisition(20, true, 6000, 1000);
FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
LED_A_OFF();
SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
// Now set up the SSC to get the ADC samples that are now streaming at us.
- FpgaSetupSsc();
+ FpgaSetupSsc(FPGA_MAJOR_MODE_LF_ADC);
// start clock - 1.5ticks is 1us
StartTicks();
projects / proxmark3-svn / blobdiff