Added em410xread, em410xsim, em410xread, bitstream, manmod, detectclock commands...

[proxmark3-svn] / armsrc / iso14443a.c

diff --git a/armsrc/iso14443a.c b/armsrc/iso14443a.c
index 0957d0514ab28f10574b51fcea703e1bab37291a..c5557d394ef1cb2e9f2c6fd00fd3004b1dd1e438 100644 (file)
--- a/armsrc/iso14443a.c
+++ b/armsrc/iso14443a.c
@@ -516,8 +516,8 @@ void SnoopIso14443a(void)
        #define RECV_RES_OFFSET         3096\r
        #define DMA_BUFFER_OFFSET       3160\r
        #define DMA_BUFFER_SIZE         4096\r
-       #define TRACE_LENGTH            3000    \r
-       \r
+       #define TRACE_LENGTH            3000\r
+\r
 //     #define RECV_CMD_OFFSET         2032    // original (working as of 21/2/09) values\r
 //     #define RECV_RES_OFFSET         2096    // original (working as of 21/2/09) values\r
 //     #define DMA_BUFFER_OFFSET       2160    // original (working as of 21/2/09) values\r
@@ -567,6 +567,8 @@ void SnoopIso14443a(void)
     Uart.state = STATE_UNSYNCD;\r
 \r
     // And put the FPGA in the appropriate mode\r
+    // Signal field is off with the appropriate LED\r
+    LED_D_OFF();\r
     FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_SNIFFER);\r
     SetAdcMuxFor(GPIO_MUXSEL_HIPKD);\r
 \r
@@ -841,6 +843,8 @@ static BOOL GetIso14443aCommandFromReader(BYTE *received, int *len, int maxLen)
 {\r
     // Set FPGA mode to "simulated ISO 14443 tag", no modulation (listen\r
     // only, since we are receiving, not transmitting).\r
+    // Signal field is off with the appropriate LED\r
+    LED_D_OFF();\r
     FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_LISTEN);\r
 \r
     // Now run a `software UART' on the stream of incoming samples.\r
@@ -893,8 +897,8 @@ void SimulateIso14443aTag(int tagType, int TagUid)
 \r
 // my desfire\r
     static const BYTE response2[] = { 0x88, 0x04, 0x21, 0x3f, 0x4d }; // known uid - note cascade (0x88), 2nd byte (0x04) = NXP/Phillips\r
-   \r
-       \r
+\r
+\r
 // When reader selects us during cascade1 it will send cmd3\r
 //BYTE response3[] = { 0x04, 0x00, 0x00 }; // SAK Select (cascade1) successful response (ULTRALITE)\r
 BYTE response3[] = { 0x24, 0x00, 0x00 }; // SAK Select (cascade1) successful response (DESFire)\r
@@ -909,7 +913,7 @@ static const BYTE response2a[] = { 0x51, 0x48, 0x1d, 0x80, 0x84 }; //  uid - cas
 //BYTE response3a[] = { 0x00, 0x00, 0x00 }; // SAK Select (cascade2) successful response (ULTRALITE)\r
 BYTE response3a[] = { 0x20, 0x00, 0x00 }; // SAK Select (cascade2) successful response (DESFire)\r
 ComputeCrc14443(CRC_14443_A, response3a, 1, &response3a[1], &response3a[2]);\r
-    \r
+\r
 // When reader tries to authenticate\r
        // static const BYTE cmd5[] = { 0x60, 0x00, 0xf5, 0x7b };\r
     static const BYTE response5[] = { 0x00, 0x00, 0x00, 0x00 }; // Very random tag nonce\r
@@ -1434,8 +1438,10 @@ static BOOL GetIso14443aAnswerFromTag(BYTE *receivedResponse, int maxLen, int *s
        // buffer needs to be 512 bytes\r
        int c;\r
 \r
-       // Set FPGA mode to "simulated ISO 14443 tag", no modulation (listen\r
+       // Set FPGA mode to "reader listen mode", no modulation (listen\r
     // only, since we are receiving, not transmitting).\r
+    // Signal field is on with the appropriate LED\r
+    LED_D_ON();\r
     FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_LISTEN);\r
 \r
     // Now get the answer from the card\r
@@ -1528,7 +1534,7 @@ void ReaderIso14443a(DWORD parameter)
        int traceLen = 0;\r
        int rsamples = 0;\r
 \r
-       memset(trace, 0x44, 2000);                              // was 2000 - tied to oter size chnages \r
+       memset(trace, 0x44, 2000);                              // was 2000 - tied to oter size chnages\r
        // setting it to 3000 causes no tag responses to be detected (2900 is ok)\r
        // setting it to 1000 causes no tag responses to be detected\r
 \r
@@ -1558,6 +1564,8 @@ void ReaderIso14443a(DWORD parameter)
        FpgaSetupSsc();\r
 \r
        // Start from off (no field generated)\r
+    // Signal field is off with the appropriate LED\r
+    LED_D_OFF();\r
     FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);\r
     SpinDelay(200);\r
 \r
@@ -1565,13 +1573,14 @@ void ReaderIso14443a(DWORD parameter)
     FpgaSetupSsc();\r
 \r
        // Now give it time to spin up.\r
+    // Signal field is on with the appropriate LED\r
+    LED_D_ON();\r
     FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_MOD);\r
        SpinDelay(200);\r
 \r
        LED_A_ON();\r
        LED_B_OFF();\r
        LED_C_OFF();\r
-       LED_D_OFF();\r
 \r
        int samples = 0;\r
        int tsamples = 0;\r
@@ -1684,7 +1693,7 @@ void ReaderIso14443a(DWORD parameter)
                traceLen += Demod.len;\r
                if(traceLen > TRACE_LENGTH) goto done;\r
 \r
-// OK we have selected at least at cascade 1, lets see if first byte of UID was 0x88 in \r
+// OK we have selected at least at cascade 1, lets see if first byte of UID was 0x88 in\r
 // which case we need to make a cascade 2 request and select - this is a long UID\r
                if (receivedAnswer[0] == 0x88)\r
                {\r
@@ -1759,14 +1768,7 @@ void ReaderIso14443a(DWORD parameter)
                traceLen += Demod.len;\r
                if(traceLen > TRACE_LENGTH) goto done;\r
 \r
-\r
-\r
-\r
-\r
-\r
-               }       \r
-\r
-               \r
+               }\r
 \r
                // Secondly compute the two CRC bytes at the end\r
                ComputeCrc14443(CRC_14443_A, cmd5, 2, &cmd5[2], &cmd5[3]);\r
@@ -1809,7 +1811,6 @@ done:
        LED_A_OFF();\r
        LED_B_OFF();\r
        LED_C_OFF();\r
-       LED_D_OFF();\r
        DbpIntegers(rsamples, 0xCC, 0xCC);\r
        DbpString("ready..");\r
 }\r