]> git.zerfleddert.de Git - proxmark3-svn/blobdiff - fpga/testbed_lo_read.v
new grid X offset calcs to fix some issues
[proxmark3-svn] / fpga / testbed_lo_read.v
index f7712832f13a0bce63ebcfb3f1540d7fa2a6e8bf..370ed389e392efe8c0cf4f39ddcdd576217bdf6b 100644 (file)
-`include "lo_read_org.v"\r
-`include "lo_read.v"\r
-/*\r
-       pck0                    - input main 24Mhz clock (PLL / 4)\r
-       [7:0] adc_d             - input data from A/D converter\r
-       lo_is_125khz    - input freq selector (1=125Khz, 0=136Khz)\r
-\r
-       pwr_lo                  - output to coil drivers (ssp_clk / 8)\r
-       adc_clk                 - output A/D clock signal\r
-       ssp_frame               - output SSS frame indicator (goes high while the 8 bits are shifted)\r
-       ssp_din                 - output SSP data to ARM (shifts 8 bit A/D value serially to ARM MSB first)\r
-       ssp_clk                 - output SSP clock signal 1Mhz/1.09Mhz (pck0 / 2*(11+lo_is_125khz) )\r
-\r
-       ck_1356meg              - input unused\r
-       ck_1356megb             - input unused\r
-       ssp_dout                - input unused\r
-       cross_hi                - input unused\r
-       cross_lo                - input unused\r
-\r
-       pwr_hi                  - output unused, tied low\r
-       pwr_oe1                 - output unused, undefined\r
-       pwr_oe2                 - output unused, undefined\r
-       pwr_oe3                 - output unused, undefined\r
-       pwr_oe4                 - output unused, undefined\r
-       dbg                             - output alias for adc_clk\r
-*/\r
-\r
-module testbed_lo_read;\r
-       reg  pck0;\r
-       reg  [7:0] adc_d;\r
-       reg  lo_is_125khz;\r
-       reg [15:0] divisor;\r
-\r
-       wire pwr_lo;\r
-       wire adc_clk;\r
-       wire ck_1356meg;\r
-       wire ck_1356megb;\r
-       wire ssp_frame;\r
-       wire ssp_din;\r
-       wire ssp_clk;\r
-       wire ssp_dout;\r
-       wire pwr_hi;\r
-       wire pwr_oe1;\r
-       wire pwr_oe2;\r
-       wire pwr_oe3;\r
-       wire pwr_oe4;\r
-       wire cross_lo;\r
-       wire cross_hi;\r
-       wire dbg;\r
-\r
-       lo_read_org #(5,10) dut1(\r
-       .pck0(pck0),\r
-       .ck_1356meg(ack_1356meg),\r
-       .ck_1356megb(ack_1356megb),\r
-       .pwr_lo(apwr_lo),\r
-       .pwr_hi(apwr_hi),\r
-       .pwr_oe1(apwr_oe1),\r
-       .pwr_oe2(apwr_oe2),\r
-       .pwr_oe3(apwr_oe3),\r
-       .pwr_oe4(apwr_oe4),\r
-       .adc_d(adc_d),\r
-       .adc_clk(adc_clk),\r
-       .ssp_frame(assp_frame),\r
-       .ssp_din(assp_din),\r
-       .ssp_dout(assp_dout),\r
-       .ssp_clk(assp_clk),\r
-       .cross_hi(across_hi),\r
-       .cross_lo(across_lo),\r
-       .dbg(adbg),\r
-       .lo_is_125khz(lo_is_125khz)\r
-       );\r
-\r
-       lo_read #(5,10) dut2(\r
-       .pck0(pck0),\r
-       .ck_1356meg(bck_1356meg),\r
-       .ck_1356megb(bck_1356megb),\r
-       .pwr_lo(bpwr_lo),\r
-       .pwr_hi(bpwr_hi),\r
-       .pwr_oe1(bpwr_oe1),\r
-       .pwr_oe2(bpwr_oe2),\r
-       .pwr_oe3(bpwr_oe3),\r
-       .pwr_oe4(bpwr_oe4),\r
-       .adc_d(adc_d),\r
-       .adc_clk(badc_clk),\r
-       .ssp_frame(bssp_frame),\r
-       .ssp_din(bssp_din),\r
-       .ssp_dout(bssp_dout),\r
-       .ssp_clk(bssp_clk),\r
-       .cross_hi(bcross_hi),\r
-       .cross_lo(bcross_lo),\r
-       .dbg(bdbg),\r
-       .lo_is_125khz(lo_is_125khz),\r
-       .divisor(divisor)\r
-       );\r
-\r
-       integer idx, i, adc_val=8;\r
-\r
-       // main clock\r
-       always #5 pck0 = !pck0;\r
-\r
-       task crank_dut;\r
-       begin\r
-               @(posedge adc_clk) ;\r
-               adc_d = adc_val;\r
-               adc_val = (adc_val *2) + 53;\r
-       end\r
-       endtask\r
-\r
-       initial begin\r
-\r
-               // init inputs\r
-               pck0 = 0;\r
-               adc_d = 0;\r
-               lo_is_125khz = 1;\r
-               divisor=255;  //min 19, 95=125Khz, max 255\r
-\r
-               // simulate 4 A/D cycles at 125Khz\r
-               for (i = 0 ;  i < 8 ;  i = i + 1) begin\r
-                       crank_dut;\r
-               end\r
-               $finish;\r
-       end\r
-endmodule // main\r
+`include "lo_read.v"
+/*
+       pck0                    - input main 24Mhz clock (PLL / 4)
+       [7:0] adc_d             - input data from A/D converter
+       lo_is_125khz    - input freq selector (1=125Khz, 0=136Khz)
+
+       pwr_lo                  - output to coil drivers (ssp_clk / 8)
+       adc_clk                 - output A/D clock signal
+       ssp_frame               - output SSS frame indicator (goes high while the 8 bits are shifted)
+       ssp_din                 - output SSP data to ARM (shifts 8 bit A/D value serially to ARM MSB first)
+       ssp_clk                 - output SSP clock signal 1Mhz/1.09Mhz (pck0 / 2*(11+lo_is_125khz) )
+
+       ck_1356meg              - input unused
+       ck_1356megb             - input unused
+       ssp_dout                - input unused
+       cross_hi                - input unused
+       cross_lo                - input unused
+
+       pwr_hi                  - output unused, tied low
+       pwr_oe1                 - output unused, undefined
+       pwr_oe2                 - output unused, undefined
+       pwr_oe3                 - output unused, undefined
+       pwr_oe4                 - output unused, undefined
+       dbg                             - output alias for adc_clk
+*/
+
+module testbed_lo_read;
+       reg  pck0;
+       reg  [7:0] adc_d;
+       reg  lo_is_125khz;
+       reg [15:0] divisor;
+
+       wire pwr_lo;
+       wire adc_clk;
+       wire ck_1356meg;
+       wire ck_1356megb;
+       wire ssp_frame;
+       wire ssp_din;
+       wire ssp_clk;
+       reg ssp_dout;
+       wire pwr_hi;
+       wire pwr_oe1;
+       wire pwr_oe2;
+       wire pwr_oe3;
+       wire pwr_oe4;
+       wire cross_lo;
+       wire cross_hi;
+       wire dbg;
+
+       lo_read #(5,10) dut(
+       .pck0(pck0),
+       .ck_1356meg(ck_1356meg),
+       .ck_1356megb(ck_1356megb),
+       .pwr_lo(pwr_lo),
+       .pwr_hi(pwr_hi),
+       .pwr_oe1(pwr_oe1),
+       .pwr_oe2(pwr_oe2),
+       .pwr_oe3(pwr_oe3),
+       .pwr_oe4(pwr_oe4),
+       .adc_d(adc_d),
+       .adc_clk(adc_clk),
+       .ssp_frame(ssp_frame),
+       .ssp_din(ssp_din),
+       .ssp_dout(ssp_dout),
+       .ssp_clk(ssp_clk),
+       .cross_hi(cross_hi),
+       .cross_lo(cross_lo),
+       .dbg(dbg),
+       .lo_is_125khz(lo_is_125khz),
+       .divisor(divisor)
+       );
+
+       integer idx, i, adc_val=8;
+
+       // main clock
+       always #5 pck0 = !pck0;
+
+       task crank_dut;
+       begin
+               @(posedge adc_clk) ;
+               adc_d = adc_val;
+               adc_val = (adc_val *2) + 53;
+       end
+       endtask
+
+       initial begin
+
+               // init inputs
+               pck0 = 0;
+               adc_d = 0;
+               ssp_dout = 0;
+               lo_is_125khz = 1;
+               divisor = 255;  //min 16, 95=125Khz, max 255
+
+               // simulate 4 A/D cycles at 125Khz
+               for (i = 0 ;  i < 8 ;  i = i + 1) begin
+                       crank_dut;
+               end
+               $finish;
+       end
+endmodule // main
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