Legic: rewrite reader to use xcorrelation and precise timing (#654)

[proxmark3-svn] / fpga / hi_read_tx.v

diff --git a/fpga/hi_read_tx.v b/fpga/hi_read_tx.v
index fc309cde6cedb60fd86f12a72aaeb44110f832e2..756683cdde7d906336935073bbfa1bf29745612e 100644 (file)
--- a/fpga/hi_read_tx.v
+++ b/fpga/hi_read_tx.v
@@ -71,21 +71,8 @@ always @(negedge ssp_clk)
 
 assign ssp_frame = (hi_byte_div == 3'b000);
 
-// Implement a hysteresis to give out the received signal on
-// ssp_din. Sample at fc.
-assign adc_clk = ck_1356meg;
+assign ssp_din = 1'b0;
 
-// ADC data appears on the rising edge, so sample it on the falling edge
-reg after_hysteresis;
-always @(negedge adc_clk)
-begin
-    if(& adc_d[7:0]) after_hysteresis <= 1'b1;
-    else if(~(| adc_d[7:0])) after_hysteresis <= 1'b0;
-end
-
-
-assign ssp_din = after_hysteresis;
-
-assign dbg = ssp_din;
+assign dbg = ssp_frame;
 
-endmodule
+endmodule
\ No newline at end of file