// Divide 13.56 MHz to produce various frequencies for SSP_CLK
// and modulation.
-reg [7:0] ssp_clk_divider;
+reg [8:0] ssp_clk_divider;
-always @(posedge adc_clk)
+always @(negedge adc_clk)
ssp_clk_divider <= (ssp_clk_divider + 1);
reg ssp_clk;
always @(negedge adc_clk)
begin
- if(mod_type == `FPGA_HF_SIMULATOR_MODULATE_424K_8BIT)
+ if (mod_type == `FPGA_HF_SIMULATOR_MODULATE_424K_8BIT)
// Get bit every at 53KHz (every 8th carrier bit of 424kHz)
- ssp_clk <= ssp_clk_divider[7];
- else if(mod_type == `FPGA_HF_SIMULATOR_MODULATE_212K)
+ ssp_clk <= ~ssp_clk_divider[7];
+ else if (mod_type == `FPGA_HF_SIMULATOR_MODULATE_212K)
// Get next bit at 212kHz
- ssp_clk <= ssp_clk_divider[5];
+ ssp_clk <= ~ssp_clk_divider[5];
else
// Get next bit at 424Khz
- ssp_clk <= ssp_clk_divider[4];
+ ssp_clk <= ~ssp_clk_divider[4];
end
-// Divide SSP_CLK by 8 to produce the byte framing signal; the phase of
-// this is arbitrary, because it's just a bitstream.
-// One nasty issue, though: I can't make it work with both rx and tx at
-// once. The phase wrt ssp_clk must be changed. TODO to find out why
-// that is and make a better fix.
-reg [2:0] ssp_frame_divider_to_arm;
-always @(posedge ssp_clk)
- ssp_frame_divider_to_arm <= (ssp_frame_divider_to_arm + 1);
-reg [2:0] ssp_frame_divider_from_arm;
-always @(negedge ssp_clk)
- ssp_frame_divider_from_arm <= (ssp_frame_divider_from_arm + 1);
-
-
+// Produce the byte framing signal; the phase of this signal
+// is arbitrary, because it's just a bit stream in this module.
reg ssp_frame;
-always @(ssp_frame_divider_to_arm or ssp_frame_divider_from_arm or mod_type)
- if(mod_type == `FPGA_HF_SIMULATOR_NO_MODULATION) // not modulating, so listening, to ARM
- ssp_frame = (ssp_frame_divider_to_arm == 3'b000);
- else
- ssp_frame = (ssp_frame_divider_from_arm == 3'b000);
+always @(negedge adc_clk)
+begin
+ if (mod_type == `FPGA_HF_SIMULATOR_MODULATE_212K)
+ begin
+ if (ssp_clk_divider[8:5] == 4'd1)
+ ssp_frame <= 1'b1;
+ if (ssp_clk_divider[8:5] == 4'd5)
+ ssp_frame <= 1'b0;
+ end
+ else
+ begin
+ if (ssp_clk_divider[7:4] == 4'd1)
+ ssp_frame <= 1'b1;
+ if (ssp_clk_divider[7:4] == 4'd5)
+ ssp_frame <= 1'b0;
+ end
+end
+
// Synchronize up the after-hysteresis signal, to produce DIN.
reg ssp_din;
assign pwr_oe2 = 1'b0;
-assign dbg = ssp_din;
+assign dbg = ssp_frame;
endmodule