+++ /dev/null
-#include <at91sam7s512.h>\r
-\r
-#ifndef __AT91SAM7S128_H\r
-#define __AT91SAM7S128_H\r
-\r
-/***************************************************************\r
- * Start of translation between PM3 defines and AT91 defines\r
- * TODO these should be replaced throughout the code at some stage\r
- ***************************************************************/\r
-#define PERIPH_PIOA AT91C_ID_PIOA\r
-#define PERIPH_ADC AT91C_ID_ADC\r
-#define PERIPH_SPI AT91C_ID_SPI\r
-#define PERIPH_SSC AT91C_ID_SSC\r
-#define PERIPH_PWMC AT91C_ID_PWMC\r
-#define PERIPH_UDP AT91C_ID_UDP\r
-#define PERIPH_TC1 AT91C_ID_TC1\r
-\r
-#define SSC_BASE AT91C_BASE_SSC\r
-\r
-#define WDT_CONTROL AT91C_BASE_WDTC->WDTC_WDCR\r
-\r
-#define PWM_ENABLE AT91C_BASE_PWMC->PWMC_ENA\r
-\r
-// TODO WARNING these PWM defines MUST be replaced in the code ASAP before\r
-// someone starts using a value of x other than that selected below\r
-#define PWM_CH_PERIOD(x) AT91C_BASE_PWMC_CH0->PWMC_CPRDR\r
-#define PWM_CH_COUNTER(x) AT91C_BASE_PWMC_CH0->PWMC_CCNTR\r
-#define PWM_CH_MODE(x) AT91C_BASE_PWMC_CH0->PWMC_CMR\r
-#define PWM_CH_DUTY_CYCLE(x) AT91C_BASE_PWMC_CH0->PWMC_CDTYR\r
-\r
-#define PDC_RX_POINTER(x) AT91C_BASE_PDC_SSC->PDC_RPR\r
-#define PDC_RX_COUNTER(x) AT91C_BASE_PDC_SSC->PDC_RCR\r
-#define PDC_RX_NEXT_POINTER(x) AT91C_BASE_PDC_SSC->PDC_RNPR\r
-#define PDC_RX_NEXT_COUNTER(x) AT91C_BASE_PDC_SSC->PDC_RNCR\r
-#define PDC_CONTROL(x) AT91C_BASE_PDC_SSC->PDC_PTCR\r
-// End WARNING\r
-\r
-#define DBGU_CIDR AT91C_BASE_DBGU->DBGU_CIDR\r
-\r
-#define RSTC_CONTROL AT91C_BASE_RSTC->RSTC_RCR\r
-#define RSTC_STATUS AT91C_BASE_RSTC->RSTC_RSR\r
-\r
-#define MC_FLASH_COMMAND AT91C_BASE_EFC0->EFC_FCR\r
-#define MC_FLASH_MODE0 AT91C_BASE_EFC0->EFC_FMR\r
-#define MC_FLASH_MODE1 AT91C_BASE_EFC1->EFC_FMR\r
-#define MC_FLASH_STATUS AT91C_BASE_EFC0->EFC_FSR\r
-\r
-#define ADC_CONTROL AT91C_BASE_ADC->ADC_CR\r
-#define ADC_MODE AT91C_BASE_ADC->ADC_MR\r
-#define ADC_CHANNEL_ENABLE AT91C_BASE_ADC->ADC_CHER\r
-#define ADC_STATUS AT91C_BASE_ADC->ADC_SR\r
-#define ADC_CHANNEL_DATA(x) AT91C_BASE_ADC->ADC_CDR[x]\r
-\r
-#define PIO_ENABLE AT91C_BASE_PIOA->PIO_PER\r
-#define PIO_DISABLE AT91C_BASE_PIOA->PIO_PDR\r
-#define PIO_OUTPUT_ENABLE AT91C_BASE_PIOA->PIO_OER\r
-#define PIO_OUTPUT_DISABLE AT91C_BASE_PIOA->PIO_ODR\r
-#define PIO_OUTPUT_DATA_SET AT91C_BASE_PIOA->PIO_SODR\r
-#define PIO_OUTPUT_DATA_CLEAR AT91C_BASE_PIOA->PIO_CODR\r
-#define PIO_PIN_DATA_STATUS AT91C_BASE_PIOA->PIO_PDSR\r
-#define PIO_NO_PULL_UP_ENABLE AT91C_BASE_PIOA->PIO_PPUDR\r
-#define PIO_NO_PULL_UP_DISABLE AT91C_BASE_PIOA->PIO_PPUER\r
-#define PIO_PERIPHERAL_B_SEL AT91C_BASE_PIOA->PIO_BSR\r
-#define PIO_PERIPHERAL_A_SEL AT91C_BASE_PIOA->PIO_ASR\r
-\r
-#define PMC_SYS_CLK_ENABLE AT91C_BASE_PMC->PMC_SCER\r
-#define PMC_PERIPHERAL_CLK_ENABLE AT91C_BASE_PMC->PMC_PCER\r
-#define PMC_MAIN_OSCILLATOR AT91C_BASE_PMC->PMC_MOR\r
-#define PMC_PLL AT91C_BASE_PMC->PMC_PLLR\r
-#define PMC_MASTER_CLK AT91C_BASE_PMC->PMC_MCKR\r
-#define PMC_PROGRAMMABLE_CLK_0 AT91C_BASE_PMC->PMC_PCKR[0]\r
-#define PMC_INTERRUPT_STATUS AT91C_BASE_PMC->PMC_SR\r
-\r
-#define SSC_CONTROL AT91C_BASE_SSC->SSC_CR\r
-#define SSC_CLOCK_DIVISOR AT91C_BASE_SSC->SSC_CMR\r
-#define SSC_RECEIVE_CLOCK_MODE AT91C_BASE_SSC->SSC_RCMR\r
-#define SSC_RECEIVE_FRAME_MODE AT91C_BASE_SSC->SSC_RFMR\r
-#define SSC_TRANSMIT_CLOCK_MODE AT91C_BASE_SSC->SSC_TCMR\r
-#define SSC_TRANSMIT_FRAME_MODE AT91C_BASE_SSC->SSC_TFMR\r
-#define SSC_RECEIVE_HOLDING AT91C_BASE_SSC->SSC_RHR\r
-#define SSC_TRANSMIT_HOLDING AT91C_BASE_SSC->SSC_THR\r
-#define SSC_STATUS AT91C_BASE_SSC->SSC_SR\r
-\r
-#define SPI_CONTROL AT91C_BASE_SPI->SPI_CR\r
-#define SPI_MODE AT91C_BASE_SPI->SPI_MR\r
-#define SPI_TX_DATA AT91C_BASE_SPI->SPI_TDR\r
-#define SPI_STATUS AT91C_BASE_SPI->SPI_SR\r
-#define SPI_FOR_CHIPSEL_0 AT91C_BASE_SPI->SPI_CSR[0]\r
-#define SPI_FOR_CHIPSEL_1 AT91C_BASE_SPI->SPI_CSR[1]\r
-#define SPI_FOR_CHIPSEL_2 AT91C_BASE_SPI->SPI_CSR[2]\r
-#define SPI_FOR_CHIPSEL_3 AT91C_BASE_SPI->SPI_CSR[3]\r
-\r
-#define TC1_CCR AT91C_BASE_TC1->TC_CCR\r
-#define TC1_CMR AT91C_BASE_TC1->TC_CMR\r
-#define TC1_CV AT91C_BASE_TC1->TC_CV\r
-#define TC1_RA AT91C_BASE_TC1->TC_RA\r
-#define TC1_SR AT91C_BASE_TC1->TC_SR\r
-\r
-#define PDC_RX_ENABLE AT91C_PDC_RXTEN\r
-#define PDC_RX_DISABLE AT91C_PDC_RXTDIS\r
-\r
-#define TC_CMR_ETRGEDG_RISING AT91C_TC_ETRGEDG_RISING\r
-#define TC_CMR_ABETRG AT91C_TC_ABETRG\r
-#define TC_CMR_LDRA_RISING AT91C_TC_LDRA_RISING\r
-#define TC_CMR_LDRB_RISING AT91C_TC_LDRB_RISING\r
-#define TC_CCR_CLKEN AT91C_TC_CLKEN\r
-#define TC_CCR_SWTRG AT91C_TC_SWTRG\r
-#define TC_SR_LDRAS AT91C_TC_LDRAS\r
-#define TC_CMR_ETRGEDG AT91C_TC_ETRGEDG\r
-#define TC_CCR_CLKDIS AT91C_TC_CLKDIS\r
-\r
-#define ADC_CONTROL_RESET AT91C_ADC_SWRST\r
-#define ADC_CONTROL_START AT91C_ADC_START\r
-\r
-#define SPI_CONTROL_ENABLE AT91C_SPI_SPIEN\r
-#define SPI_CONTROL_LAST_TRANSFER AT91C_SPI_LASTXFER\r
-#define SPI_CONTROL_RESET AT91C_SPI_SWRST\r
-#define SPI_CONTROL_DISABLE AT91C_SPI_SPIDIS\r
-#define SPI_STATUS_TX_EMPTY AT91C_SPI_TXEMPTY\r
-\r
-#define SSC_CONTROL_RX_ENABLE AT91C_SSC_RXEN\r
-#define SSC_CONTROL_TX_ENABLE AT91C_SSC_TXEN\r
-#define SSC_FRAME_MODE_MSB_FIRST AT91C_SSC_MSBF\r
-#define SSC_CONTROL_RESET AT91C_SSC_SWRST\r
-#define SSC_STATUS_TX_READY AT91C_SSC_TXRDY\r
-#define SSC_STATUS_RX_READY AT91C_SSC_RXRDY\r
-\r
-#define FCMD_WRITE_PAGE AT91C_MC_FCMD_START_PROG\r
-#define FLASH_PAGE_SIZE_BYTES AT91C_IFLASH_PAGE_SIZE\r
-\r
-#define RST_CONTROL_PROCESSOR_RESET AT91C_RSTC_PROCRST\r
-#define RST_STATUS_TYPE_MASK AT91C_RSTC_RSTTYP\r
-#define RST_STATUS_TYPE_WATCHDOG AT91C_RSTC_RSTTYP_WATCHDOG\r
-#define RST_STATUS_TYPE_SOFTWARE AT91C_RSTC_RSTTYP_SOFTWARE\r
-#define RST_STATUS_TYPE_USER AT91C_RSTC_RSTTYP_USER\r
-\r
-#define PMC_SYS_CLK_PROCESSOR_CLK AT91C_PMC_PCK\r
-#define PMC_SYS_CLK_UDP_CLK AT91C_PMC_UDP\r
-#define PMC_CLK_SELECTION_PLL_CLOCK AT91C_PMC_CSS_PLL_CLK\r
-#define PMC_CLK_PRESCALE_DIV_4 AT91C_PMC_PRES_CLK_4\r
-#define PMC_SYS_CLK_PROGRAMMABLE_CLK_0 AT91C_PMC_PCK0\r
-\r
-#define UDP_INTERRUPT_STATUS AT91C_BASE_UDP->UDP_ISR\r
-#define UDP_INTERRUPT_CLEAR AT91C_BASE_UDP->UDP_ICR\r
-#define UDP_FUNCTION_ADDR AT91C_BASE_UDP->UDP_FADDR\r
-#define UDP_RESET_ENDPOINT AT91C_BASE_UDP->UDP_RSTEP\r
-#define UDP_GLOBAL_STATE AT91C_BASE_UDP->UDP_GLBSTATE\r
-#define UDP_ENDPOINT_CSR(x) AT91C_BASE_UDP->UDP_CSR[x]\r
-#define UDP_ENDPOINT_FIFO(x) AT91C_BASE_UDP->UDP_FDR[x]\r
-\r
-#define UDP_CSR_CONTROL_DATA_DIR AT91C_UDP_DIR\r
-#define UDP_CSR_ENABLE_EP AT91C_UDP_EPEDS\r
-#define UDP_CSR_EPTYPE_CONTROL AT91C_UDP_EPTYPE_CTRL\r
-#define UDP_CSR_EPTYPE_INTERRUPT_IN AT91C_UDP_EPTYPE_INT_IN\r
-#define UDP_CSR_EPTYPE_INTERRUPT_OUT AT91C_UDP_EPTYPE_INT_OUT\r
-#define UDP_CSR_FORCE_STALL AT91C_UDP_FORCESTALL\r
-#define UDP_CSR_RX_HAVE_READ_SETUP_DATA AT91C_UDP_RXSETUP\r
-#define UDP_CSR_RX_PACKET_RECEIVED_BANK_0 AT91C_UDP_RX_DATA_BK0\r
-#define UDP_CSR_RX_PACKET_RECEIVED_BANK_1 AT91C_UDP_RX_DATA_BK1\r
-#define UDP_CSR_STALL_SENT AT91C_UDP_STALLSENT\r
-#define UDP_CSR_TX_PACKET AT91C_UDP_TXPKTRDY\r
-#define UDP_CSR_TX_PACKET_ACKED AT91C_UDP_TXCOMP\r
-\r
-#define UDP_FUNCTION_ADDR_ENABLED AT91C_UDP_FEN\r
-#define UDP_GLOBAL_STATE_ADDRESSED AT91C_UDP_FADDEN\r
-#define UDP_GLOBAL_STATE_CONFIGURED AT91C_UDP_CONFG\r
-#define UDP_INTERRUPT_END_OF_BUS_RESET AT91C_UDP_ENDBUSRES\r
-/***************************************************************\r
- * end of translation between PM3 defines and AT91 defines\r
- ***************************************************************/\r
-\r
-/***************************************************************\r
- * the defines below this line have no AT91 equivalents and can\r
- * be ideally moved to proxmark3.h\r
- ***************************************************************/\r
-#define WDT_HIT() WDT_CONTROL = 0xa5000001\r
-\r
-#define PWM_CH_MODE_PRESCALER(x) ((x)<<0)\r
-#define PWM_CHANNEL(x) (1<<(x))\r
-\r
-#define TC_CMR_TCCLKS_TIMER_CLOCK1 (0<<0)\r
-\r
-#define ADC_CHAN_LF 4\r
-#define ADC_CHAN_HF 5\r
-#define ADC_MODE_PRESCALE(x) ((x)<<8)\r
-#define ADC_MODE_STARTUP_TIME(x) ((x)<<16)\r
-#define ADC_MODE_SAMPLE_HOLD_TIME(x) ((x)<<24)\r
-#define ADC_CHANNEL(x) (1<<(x))\r
-#define ADC_END_OF_CONVERSION(x) (1<<(x))\r
-\r
-#define SSC_CLOCK_MODE_START(x) ((x)<<8)\r
-#define SSC_FRAME_MODE_WORDS_PER_TRANSFER(x) ((x)<<8)\r
-#define SSC_CLOCK_MODE_SELECT(x) ((x)<<0)\r
-#define SSC_FRAME_MODE_BITS_IN_WORD(x) (((x)-1)<<0)\r
-\r
-#define MC_FLASH_COMMAND_KEY ((0x5A)<<24)\r
-#define MC_FLASH_STATUS_READY (1<<0)\r
-#define MC_FLASH_MODE_FLASH_WAIT_STATES(x) ((x)<<8)\r
-#define MC_FLASH_MODE_MASTER_CLK_IN_MHZ(x) ((x)<<16)\r
-#define MC_FLASH_COMMAND_PAGEN(x) ((x)<<8)\r
-\r
-#define RST_CONTROL_KEY (0xA5<<24)\r
-\r
-#define PMC_MAIN_OSCILLATOR_ENABLE (1<<0)\r
-#define PMC_MAIN_OSCILLATOR_STABILIZED (1<<0)\r
-#define PMC_MAIN_OSCILLATOR_PLL_LOCK (1<<2)\r
-#define PMC_MAIN_OSCILLATOR_MCK_READY (1<<3)\r
-\r
-#define PMC_PLL_DIVISOR(x) (x)\r
-#define PMC_MAIN_OSCILLATOR_STARTUP_DELAY(x) ((x)<<8)\r
-#define PMC_CLK_PRESCALE_DIV_2 (1<<2)\r
-#define PMC_PLL_MULTIPLIER(x) (((x)-1)<<16)\r
-#define PMC_PLL_COUNT_BEFORE_LOCK(x) ((x)<<8)\r
-#define PMC_PLL_FREQUENCY_RANGE(x) ((x)<<14)\r
-#define PMC_PLL_USB_DIVISOR(x) ((x)<<28)\r
-\r
-#define UDP_INTERRUPT_ENDPOINT(x) (1<<(x))\r
-#define UDP_CSR_BYTES_RECEIVED(x) (((x) >> 16) & 0x7ff)\r
-\r
-#endif\r
projects / proxmark3-svn / blobdiff