iclass refactor/cleanup

[proxmark3-svn] / fpga / sim.tcl

diff --git a/fpga/sim.tcl b/fpga/sim.tcl
index 477acd1d1ca617c1b975e4e19ee6c24c0f066e5d..0ee8c0c37fe618159e2959941d0b89fb7a2982ce 100644 (file)
--- a/fpga/sim.tcl
+++ b/fpga/sim.tcl
@@ -1,27 +1,27 @@
-#------------------------------------------------------------------------------\r
-# Run the simulation testbench in ModelSim: recompile both Verilog source\r
-# files, then start the simulation, add a lot of signals to the waveform\r
-# viewer, and run. I should (TODO) fix the absolute paths at some point.\r
-#\r
-# Jonathan Westhues, Mar 2006\r
-#------------------------------------------------------------------------------\r
-\r
-vlog -work work -O0 C:/depot/proximity/mark3/fpga/fpga.v\r
-vlog -work work -O0 C:/depot/proximity/mark3/fpga/fpga_tb.v\r
-\r
-vsim work.fpga_tb\r
-\r
-add wave sim:/fpga_tb/adc_clk\r
-add wave sim:/fpga_tb/adc_d\r
-add wave sim:/fpga_tb/pwr_lo\r
-add wave sim:/fpga_tb/ssp_clk\r
-add wave sim:/fpga_tb/ssp_frame\r
-add wave sim:/fpga_tb/ssp_din\r
-add wave sim:/fpga_tb/ssp_dout\r
-\r
-add wave sim:/fpga_tb/dut/clk_lo\r
-add wave sim:/fpga_tb/dut/pck_divider\r
-add wave sim:/fpga_tb/dut/carrier_divider_lo\r
-add wave sim:/fpga_tb/dut/conf_word\r
-\r
-run 30000\r
+#------------------------------------------------------------------------------
+# Run the simulation testbench in ModelSim: recompile both Verilog source
+# files, then start the simulation, add a lot of signals to the waveform
+# viewer, and run. I should (TODO) fix the absolute paths at some point.
+#
+# Jonathan Westhues, Mar 2006
+#------------------------------------------------------------------------------
+
+vlog -work work -O0 C:/depot/proximity/mark3/fpga/fpga.v
+vlog -work work -O0 C:/depot/proximity/mark3/fpga/fpga_tb.v
+
+vsim work.fpga_tb
+
+add wave sim:/fpga_tb/adc_clk
+add wave sim:/fpga_tb/adc_d
+add wave sim:/fpga_tb/pwr_lo
+add wave sim:/fpga_tb/ssp_clk
+add wave sim:/fpga_tb/ssp_frame
+add wave sim:/fpga_tb/ssp_din
+add wave sim:/fpga_tb/ssp_dout
+
+add wave sim:/fpga_tb/dut/clk_lo
+add wave sim:/fpga_tb/dut/pck_divider
+add wave sim:/fpga_tb/dut/carrier_divider_lo
+add wave sim:/fpga_tb/dut/conf_word
+
+run 30000