\r
assign ssp_frame = (hi_byte_div == 3'b000);\r
\r
-assign ssp_din = 1'b0;\r
+// Implement a hysteresis to give out the received signal on\r
+// ssp_din. Sample at fc.\r
+assign adc_clk = ck_1356meg;\r
+\r
+// ADC data appears on the rising edge, so sample it on the falling edge\r
+reg after_hysteresis;\r
+always @(negedge adc_clk)\r
+begin\r
+ if(& adc_d[7:0]) after_hysteresis <= 1'b1;\r
+ else if(~(| adc_d[7:0])) after_hysteresis <= 1'b0;\r
+end\r
+\r
+\r
+assign ssp_din = after_hysteresis;\r
\r
assign pwr_lo = 1'b0;\r
-assign dbg = ssp_frame;\r
+assign dbg = ssp_din;\r
\r
endmodule\r