]> git.zerfleddert.de Git - proxmark3-svn/blobdiff - fpga/testbed_hi_simulate.v
Merge pull request #8 from pwpiwi/master
[proxmark3-svn] / fpga / testbed_hi_simulate.v
index 6dc30f0b394164e89f7c4bcb533c3a2260d112ae..b0672016595bd0a78e16b2a73a2c8e0ebbb36553 100644 (file)
-`include "hi_simulate.v"\r
-\r
-/*\r
-       pck0                    - input main 24Mhz clock (PLL / 4)\r
-       [7:0] adc_d             - input data from A/D converter\r
-       mod_type        - modulation type\r
-\r
-       pwr_lo                  - output to coil drivers (ssp_clk / 8)\r
-       adc_clk                 - output A/D clock signal\r
-       ssp_frame               - output SSS frame indicator (goes high while the 8 bits are shifted)\r
-       ssp_din                 - output SSP data to ARM (shifts 8 bit A/D value serially to ARM MSB first)\r
-       ssp_clk                 - output SSP clock signal\r
-\r
-       ck_1356meg              - input unused\r
-       ck_1356megb             - input unused\r
-       ssp_dout                - input unused\r
-       cross_hi                - input unused\r
-       cross_lo                - input unused\r
-\r
-       pwr_hi                  - output unused, tied low\r
-       pwr_oe1                 - output unused, undefined\r
-       pwr_oe2                 - output unused, undefined\r
-       pwr_oe3                 - output unused, undefined\r
-       pwr_oe4                 - output unused, undefined\r
-       dbg                             - output alias for adc_clk\r
-*/\r
-\r
-module testbed_hi_simulate;\r
-       reg  pck0;\r
-       reg  [7:0] adc_d;\r
-       reg  mod_type;\r
-\r
-       wire pwr_lo;\r
-       wire adc_clk;\r
-       reg ck_1356meg;\r
-       reg  ck_1356megb;\r
-       wire ssp_frame;\r
-       wire ssp_din;\r
-       wire ssp_clk;\r
-       reg  ssp_dout;\r
-       wire pwr_hi;\r
-       wire pwr_oe1;\r
-       wire pwr_oe2;\r
-       wire pwr_oe3;\r
-       wire pwr_oe4;\r
-       wire cross_lo;\r
-       wire cross_hi;\r
-       wire dbg;\r
-\r
-       hi_simulate #(5,200) dut(\r
-       .pck0(pck0),\r
-       .ck_1356meg(ck_1356meg),\r
-       .ck_1356megb(ck_1356megb),\r
-       .pwr_lo(pwr_lo),\r
-       .pwr_hi(pwr_hi),\r
-       .pwr_oe1(pwr_oe1),\r
-       .pwr_oe2(pwr_oe2),\r
-       .pwr_oe3(pwr_oe3),\r
-       .pwr_oe4(pwr_oe4),\r
-       .adc_d(adc_d),\r
-       .adc_clk(adc_clk),\r
-       .ssp_frame(ssp_frame),\r
-       .ssp_din(ssp_din),\r
-       .ssp_dout(ssp_dout),\r
-       .ssp_clk(ssp_clk),\r
-       .cross_hi(cross_hi),\r
-       .cross_lo(cross_lo),\r
-       .dbg(dbg),\r
-       .mod_type(mod_type)\r
-       );\r
-\r
-       integer idx, i;\r
-\r
-       // main clock\r
-       always #5 begin \r
-               ck_1356megb = !ck_1356megb;\r
-               ck_1356meg = ck_1356megb;\r
-       end\r
-\r
-       always begin \r
-               @(negedge adc_clk) ;\r
-               adc_d = $random;\r
-       end\r
-\r
-       //crank DUT\r
-       task crank_dut;\r
-               begin\r
-                       @(negedge ssp_clk) ;\r
-                       ssp_dout = $random;\r
-               end\r
-       endtask\r
-\r
-       initial begin\r
-\r
-               // init inputs\r
-               ck_1356megb = 0;\r
-               // random values\r
-               adc_d = 0;\r
-               ssp_dout=1;\r
-\r
-               // shallow modulation off\r
-               mod_type=0;\r
-               for (i = 0 ;  i < 16 ;  i = i + 1) begin\r
-                       crank_dut;\r
-               end\r
-\r
-               // shallow modulation on\r
-               mod_type=1;\r
-               for (i = 0 ;  i < 16 ;  i = i + 1) begin\r
-                       crank_dut;\r
-               end\r
-               $finish;\r
-       end\r
-       \r
-endmodule // main\r
-\r
+`include "hi_simulate.v"
+
+/*
+       pck0                    - input main 24Mhz clock (PLL / 4)
+       [7:0] adc_d             - input data from A/D converter
+       mod_type        - modulation type
+
+       pwr_lo                  - output to coil drivers (ssp_clk / 8)
+       adc_clk                 - output A/D clock signal
+       ssp_frame               - output SSS frame indicator (goes high while the 8 bits are shifted)
+       ssp_din                 - output SSP data to ARM (shifts 8 bit A/D value serially to ARM MSB first)
+       ssp_clk                 - output SSP clock signal
+
+       ck_1356meg              - input unused
+       ck_1356megb             - input unused
+       ssp_dout                - input unused
+       cross_hi                - input unused
+       cross_lo                - input unused
+
+       pwr_hi                  - output unused, tied low
+       pwr_oe1                 - output unused, undefined
+       pwr_oe2                 - output unused, undefined
+       pwr_oe3                 - output unused, undefined
+       pwr_oe4                 - output unused, undefined
+       dbg                             - output alias for adc_clk
+*/
+
+module testbed_hi_simulate;
+       reg  pck0;
+       reg  [7:0] adc_d;
+       reg  mod_type;
+
+       wire pwr_lo;
+       wire adc_clk;
+       reg ck_1356meg;
+       reg  ck_1356megb;
+       wire ssp_frame;
+       wire ssp_din;
+       wire ssp_clk;
+       reg  ssp_dout;
+       wire pwr_hi;
+       wire pwr_oe1;
+       wire pwr_oe2;
+       wire pwr_oe3;
+       wire pwr_oe4;
+       wire cross_lo;
+       wire cross_hi;
+       wire dbg;
+
+       hi_simulate #(5,200) dut(
+       .pck0(pck0),
+       .ck_1356meg(ck_1356meg),
+       .ck_1356megb(ck_1356megb),
+       .pwr_lo(pwr_lo),
+       .pwr_hi(pwr_hi),
+       .pwr_oe1(pwr_oe1),
+       .pwr_oe2(pwr_oe2),
+       .pwr_oe3(pwr_oe3),
+       .pwr_oe4(pwr_oe4),
+       .adc_d(adc_d),
+       .adc_clk(adc_clk),
+       .ssp_frame(ssp_frame),
+       .ssp_din(ssp_din),
+       .ssp_dout(ssp_dout),
+       .ssp_clk(ssp_clk),
+       .cross_hi(cross_hi),
+       .cross_lo(cross_lo),
+       .dbg(dbg),
+       .mod_type(mod_type)
+       );
+
+       integer idx, i;
+
+       // main clock
+       always #5 begin 
+               ck_1356megb = !ck_1356megb;
+               ck_1356meg = ck_1356megb;
+       end
+
+       always begin 
+               @(negedge adc_clk) ;
+               adc_d = $random;
+       end
+
+       //crank DUT
+       task crank_dut;
+               begin
+                       @(negedge ssp_clk) ;
+                       ssp_dout = $random;
+               end
+       endtask
+
+       initial begin
+
+               // init inputs
+               ck_1356megb = 0;
+               // random values
+               adc_d = 0;
+               ssp_dout=1;
+
+               // shallow modulation off
+               mod_type=0;
+               for (i = 0 ;  i < 16 ;  i = i + 1) begin
+                       crank_dut;
+               end
+
+               // shallow modulation on
+               mod_type=1;
+               for (i = 0 ;  i < 16 ;  i = i + 1) begin
+                       crank_dut;
+               end
+               $finish;
+       end
+       
+endmodule // main
+
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