memset(dest,0,n);\r
\r
if(at134khz) {\r
+ FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz\r
FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER | FPGA_LF_READER_USE_134_KHZ);\r
} else {\r
+ FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz\r
FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER | FPGA_LF_READER_USE_125_KHZ);\r
}\r
\r
\r
//-----------------------------------------------------------------------------\r
// Read an ADC channel and block till it completes, then return the result\r
-// in ADC units (0 to 1023). Also a routine to average sixteen samples and\r
+// in ADC units (0 to 1023). Also a routine to average 32 samples and\r
// return that.\r
//-----------------------------------------------------------------------------\r
static int ReadAdc(int ch)\r
\r
return (a + 15) >> 5;\r
}\r
+
+/*
+ * Sweeps the useful LF range of the proxmark from
+ * 46.8kHz (divisor=255) to 600kHz (divisor=19) and
+ * reads the voltage in the antenna: the result is a graph
+ * which should clearly show the resonating frequency of your
+ * LF antenna ( hopefully around 90 if it is tuned to 125kHz!)
+ */\r
+void SweepLFrange()\r
+{\r
+ BYTE *dest = (BYTE *)BigBuf;\r
+ int i;\r
+\r
+ // clear buffer\r
+ memset(BigBuf,0,sizeof(BigBuf));\r
+\r
+ FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);\r
+ for (i=255; i>19; i--) {\r
+ FpgaSendCommand(FPGA_CMD_SET_DIVISOR, i);\r
+ SpinDelay(20);\r
+ dest[i] = (137500 * AvgAdc(4)) >> 18;\r
+ }\r
+}\r
\r
void MeasureAntennaTuning(void)\r
{\r
UsbCommand c;\r
\r
// Let the FPGA drive the low-frequency antenna around 125 kHz.\r
+ FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz\r
FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER | FPGA_LF_READER_USE_125_KHZ);\r
SpinDelay(20);\r
vLf125 = AvgAdc(4);\r
vLf125 = (137500 * vLf125) >> 10;\r
\r
// Let the FPGA drive the low-frequency antenna around 134 kHz.\r
+ FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz\r
FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER | FPGA_LF_READER_USE_134_KHZ);\r
SpinDelay(20);\r
vLf134 = AvgAdc(4);\r
PIO_OUTPUT_DISABLE = (1 << GPIO_SSC_CLK);\r
\r
#define SHORT_COIL() LOW(GPIO_SSC_DOUT)\r
-#define OPEN_COIL() HIGH(GPIO_SSC_DOUT)\r
+#define OPEN_COIL() HIGH(GPIO_SSC_DOUT)\r
\r
i = 0;\r
for(;;) {\r
int m=0, n=0, i=0, idx=0, found=0, lastval=0;\r
DWORD hi=0, lo=0;\r
\r
+ FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz\r
FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER | FPGA_LF_READER_USE_125_KHZ);\r
\r
// Connect the A/D to the peak-detected low-frequency path.\r
dest[i++]=dest[idx-1];\r
dest[i++]=dest[idx-1];\r
break;\r
- // When a logic 0 is immediately followed by the start of the next transmisson \r
+ // When a logic 0 is immediately followed by the start of the next transmisson\r
// (special pattern) a pattern of 4 bit duration lengths is created.\r
case 4:\r
dest[i++]=dest[idx-1];\r
break;\r
\r
case CMD_READER_ISO_15693:\r
- ReaderIso15693(c->ext1); \r
+ ReaderIso15693(c->ext1);\r
break;\r
\r
case CMD_SIMTAG_ISO_15693:\r
- SimTagIso15693(c->ext1); \r
+ SimTagIso15693(c->ext1);\r
break;\r
\r
-\r
case CMD_ACQUIRE_RAW_ADC_SAMPLES_ISO_14443:\r
AcquireRawAdcSamplesIso14443(c->ext1);\r
break;\r
+
+ case CMD_READ_SRI512_TAG:
+ ReadSRI512Iso14443(c->ext1);
+ break;
\r
case CMD_READER_ISO_14443a:\r
- ReaderIso14443a(c->ext1); \r
+ ReaderIso14443a(c->ext1);\r
break;\r
\r
case CMD_SNOOP_ISO_14443:\r
LCDReset();\r
break;\r
\r
+ case CMD_SWEEP_LF:\r
+ SweepLFrange();\r
+ break;\r
+\r
+ case CMD_SET_LF_DIVISOR:\r
+ FpgaSendCommand(FPGA_CMD_SET_DIVISOR, c->ext1);\r
+ break;\r
+\r
case CMD_LCD:\r
LCDSend(c->ext1);\r
break;\r