adc_d, adc_clk,\r
ssp_frame, ssp_din, ssp_dout, ssp_clk,\r
cross_hi, cross_lo,\r
- dbg\r
+ dbg, divisor\r
);\r
input pck0, ck_1356meg, ck_1356megb;\r
output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;\r
output ssp_frame, ssp_din, ssp_clk;\r
input cross_hi, cross_lo;\r
output dbg;\r
+ input [7:0] divisor;\r
\r
-// No logic, straight through.\r
+reg [7:0] pck_divider;\r
+reg ant_lo;\r
\r
+// this task runs on the rising egde of pck0 clock (24Mhz) and creates ant_lo\r
+// which is high for (divisor+1) pck0 cycles and low for the same duration\r
+// ant_lo is therefore a 50% duty cycle clock signal with a frequency of\r
+// 12Mhz/(divisor+1) which drives the antenna as well as the ADC clock adc_clk\r
+always @(posedge pck0)\r
+begin\r
+ if(pck_divider == divisor[7:0])\r
+ begin\r
+ pck_divider <= 8'd0;\r
+ ant_lo = !ant_lo;\r
+ end\r
+ else\r
+ begin\r
+ pck_divider <= pck_divider + 1;\r
+ end\r
+end\r
+\r
+// the antenna is modulated when ssp_dout = 1, when 0 the\r
+// antenna drivers stop modulating and go into listen mode\r
assign pwr_oe3 = 1'b0;\r
-assign pwr_oe1 = 1'b1;\r
-assign pwr_oe2 = 1'b1;\r
-assign pwr_oe4 = 1'b1;\r
-assign pwr_lo = 1'b0;\r
+assign pwr_oe1 = ssp_dout;\r
+assign pwr_oe2 = ssp_dout;\r
+assign pwr_oe4 = ssp_dout;\r
+assign pwr_lo = ant_lo && ssp_dout;\r
assign pwr_hi = 1'b0;\r
assign adc_clk = 1'b0;\r
assign ssp_din = cross_lo;\r