#include "crapto1.h"
#include "mifareutil.h"
+#define SHORT_COIL() LOW(GPIO_SSC_DOUT)
+#define OPEN_COIL() HIGH(GPIO_SSC_DOUT)
+
void LFSetupFPGAForADC(int divisor, bool lf_field)
{
FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
void DoAcquisition125k_internal(int trigger_threshold, bool silent)
{
uint8_t *dest = mifare_get_bigbufptr();
- int n = 8000;
- int i;
-
+ int n = 24000;
+ int i = 0;
memset(dest, 0x00, n);
- i = 0;
+
for(;;) {
if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
AT91C_BASE_SSC->SSC_THR = 0x43;
void ModThenAcquireRawAdcSamples125k(int delay_off, int period_0, int period_1, uint8_t *command)
{
- int at134khz;
/* Make sure the tag is reset */
FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
SpinDelay(2500);
+ int divisor_used = 95; // 125 KHz
// see if 'h' was specified
- if (command[strlen((char *) command) - 1] == 'h')
- at134khz = TRUE;
- else
- at134khz = FALSE;
- if (at134khz)
- FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
- else
- FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
+ if (command[strlen((char *) command) - 1] == 'h')
+ divisor_used = 88; // 134.8 KHz
+ FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor_used);
FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
-
// Give it a bit of time for the resonant antenna to settle.
SpinDelay(50);
+
+
// And a little more time for the tag to fully power up
SpinDelay(2000);
FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
LED_D_OFF();
SpinDelayUs(delay_off);
- if (at134khz)
- FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
- else
- FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
+ FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor_used);
FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
LED_D_ON();
FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
LED_D_OFF();
SpinDelayUs(delay_off);
- if (at134khz)
- FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
- else
- FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
+ FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor_used);
FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
// now do the read
- DoAcquisition125k();
+ DoAcquisition125k(-1);
}
/* blank r/w tag data stream
{
if (b&(1<<i)) {
// stop modulating antenna
- LOW(GPIO_SSC_DOUT);
+ SHORT_COIL();
SpinDelayUs(1000);
// modulate antenna
- HIGH(GPIO_SSC_DOUT);
+ OPEN_COIL();
SpinDelayUs(1000);
} else {
// stop modulating antenna
- LOW(GPIO_SSC_DOUT);
+ SHORT_COIL();
SpinDelayUs(300);
// modulate antenna
- HIGH(GPIO_SSC_DOUT);
+ OPEN_COIL();
SpinDelayUs(1700);
}
}
void SimulateTagLowFrequency(int period, int gap, int ledcontrol)
{
- int i;
- uint8_t *tab = (uint8_t *)BigBuf;
-
+ int i = 0;
+ uint8_t *buf = (uint8_t *)BigBuf;
+
FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
- FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT);
-
- AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK;
-
- AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
- AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK;
-
-#define SHORT_COIL() LOW(GPIO_SSC_DOUT)
-#define OPEN_COIL() HIGH(GPIO_SSC_DOUT)
-
- i = 0;
- for(;;) {
- while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) {
- if(BUTTON_PRESS()) {
- DbpString("Stopped");
- return;
- }
- WDT_HIT();
+ FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
+ //FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT);
+ FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
+
+ // Connect the A/D to the peak-detected low-frequency path.
+ //SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
+
+ // Configure output and enable pin that is connected to the FPGA (for modulating)
+ AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK;
+ AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT; // (PIO_PER) PIO Enable Register ,
+ AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT; // (PIO_OER) Output Enable Register
+ AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK; // (PIO_ODR) Output Disable Register
+
+ // Give it a bit of time for the resonant antenna to settle.
+ SpinDelay(150);
+
+ while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)); // wait for ssp_clk to go high
+ while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK); // wait for ssp_clk to go low
+
+ while(!BUTTON_PRESS()) {
+ WDT_HIT();
+
+ // PIO_PDSR = Pin Data Status Register
+ // GPIO_SSC_CLK = SSC Transmit Clock
+ while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) { // wait for ssp_clk to go high
+ if(BUTTON_PRESS()) {
+ DbpString("Stopped at 0");
+ FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
+ return;
+ }
+ WDT_HIT();
}
- if (ledcontrol)
- LED_D_ON();
-
- if(tab[i])
- OPEN_COIL();
- else
- SHORT_COIL();
-
- if (ledcontrol)
- LED_D_OFF();
-
- while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) {
- if(BUTTON_PRESS()) {
- DbpString("Stopped");
+ // PIO_CODR = Clear Output Data Register
+ // PIO_SODR = Set Output Data Register
+ //#define LOW(x) AT91C_BASE_PIOA->PIO_CODR = (x)
+ //#define HIGH(x) AT91C_BASE_PIOA->PIO_SODR = (x)
+
+ if ( buf[i] > 0 ){
+ HIGH(GPIO_SSC_DOUT);
+ //FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
+ //FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
+ } else {
+ LOW(GPIO_SSC_DOUT);
+ //FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
+ }
+
+ while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) { // wait for ssp_clk to go low
+ if(BUTTON_PRESS()) {
+ DbpString("Stopped at 1");
+ FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
return;
}
WDT_HIT();
- }
-
- i++;
+ }
+
+ //SpinDelayUs(512);
+
+ ++i;
if(i == period) {
i = 0;
if (gap) {
- SHORT_COIL();
- SpinDelayUs(gap);
- }
+ // turn of modulation
+ LOW(GPIO_SSC_DOUT);
+ // wait
+ SpinDelay(gap);
+ }
}
}
+ DbpString("Stopped");
+ FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
+ return;
}
#define DEBUG_FRAME_CONTENTS 1
if (ledcontrol)
LED_A_ON();
+
SimulateTagLowFrequency(n, 0, ledcontrol);
if (ledcontrol)
size_t size=0,idx=0; //, found=0;
uint32_t hi2=0, hi=0, lo=0;
+ // Configure to go in 125Khz listen mode
+ LFSetupFPGAForADC(0, true);
while(!BUTTON_PRESS()) {
- // Configure to go in 125Khz listen mode
- LFSetupFPGAForADC(0,true);
-
WDT_HIT();
if (ledcontrol) LED_A_ON();
- DoAcquisition125k();
+ DoAcquisition125k_internal(-1,true);
size = sizeof(BigBuf);
// FSK demodulator
size = fsk_demod(dest, size);
- WDT_HIT();
// we now have a set of cycle counts, loop over previous results and aggregate data into bit patterns
// 1->0 : fc/8 in sets of 6
idx+=sizeof(frame_marker_mask);
while(dest[idx] != dest[idx+1] && idx < size-2)
- { // Keep going until next frame marker (or error)
+ {
+ // Keep going until next frame marker (or error)
// Shift in a bit. Start by shifting high registers
hi2=(hi2<<1)|(hi>>31);
hi=(hi<<1)|(lo>>31);
}
//Dbprintf("Num shifts: %d ", numshifts);
// Hopefully, we read a tag and hit upon the next frame marker
+ if(idx + sizeof(frame_marker_mask) < size)
+ {
if ( memcmp(dest+idx, frame_marker_mask, sizeof(frame_marker_mask)) == 0)
{
if (hi2 != 0){
}
}
+ }
+
// reset
hi2 = hi = lo = 0;
numshifts = 0;
size_t size=0, idx=0;
uint32_t code=0, code2=0;
+ // Configure to go in 125Khz listen mode
+ LFSetupFPGAForADC(0, true);
while(!BUTTON_PRESS()) {
-
- // Configure to go in 125Khz listen mode
- LFSetupFPGAForADC(0,true);
-
WDT_HIT();
if (ledcontrol) LED_A_ON();
- DoAcquisition125k(true);
+ DoAcquisition125k_internal(-1,true);
size = sizeof(BigBuf);
// FSK demodulator
size = fsk_demod(dest, size);
- WDT_HIT();
// we now have a set of cycle counts, loop over previous results and aggregate data into bit patterns
// 1->0 : fc/8 in sets of 7
projects / proxmark3-svn / blobdiff