+
+////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+// PM3 -> Reader, internal timing:
+// a timer for the 1172 cycles fdt (Frame Delay Time). Start the timer with a rising edge of the reader's signal.
+// set fdt_elapsed when we no longer need to delay data. Set fdt_indicator when we can start sending data.
+// Note: the FPGA only takes care for the 1172 delay. To achieve an additional 1236-1172=64 ticks delay, the ARM must send
+// a correction bit (before the start bit). The correction bit will be coded as 00010000, i.e. it adds 4 bits to the
+// transmission stream, causing the required additional delay.
+reg [10:0] fdt_counter;
+reg fdt_indicator, fdt_elapsed;
+reg [3:0] mod_sig_flip;
+reg [3:0] sub_carrier_cnt;
+
+// we want to achieve a delay of 1172. The RF part already has delayed the reader signals's rising edge
+// by 9 ticks, the ADC took 3 ticks and there is always a delay of 32 ticks by the mod_sig_buf. Therefore need to
+// count to 1172 - 9 - 3 - 32 = 1128
+`define FDT_COUNT 11'd1128
+
+// The ARM must not send too early, otherwise the mod_sig_buf will overflow, therefore signal that we are ready
+// with fdt_indicator. The mod_sig_buf can buffer 29 excess data bits, i.e. a maximum delay of 29 * 16 = 464 adc_clk ticks.
+// fdt_indicator is assigned to sendbit after at least 1 tick, the transfer to ARM needs minimum 8 ticks. Response from
+// ARM could appear at ssp_dout 8 ticks later.
+// 1128 - 464 - 1 - 8 - 8 = 647
+`define FDT_INDICATOR_COUNT 11'd647
+// Note: worst case, assignment to sendbit takes 15 ticks more, and transfer to ARM needs 7*16 = 112 ticks more.
+// When the ARM's response then appears, the fdt_count is already 647 + 15 + 112 = 774, which still allows the ARM a possible
+// response window of 1128 - 774 = 354 ticks.
+
+// reset on a pause in listen mode. I.e. the counter starts when the pause is over:
+assign fdt_reset = ~after_hysteresis && mod_type == `TAGSIM_LISTEN;
+
+always @(negedge adc_clk)
+begin
+ if (fdt_reset)