-MEMORY \r
-{\r
- /* AT91SAM7S256 has 256k Flash and 64k RAM */\r
- /* Important note: the correct ORIGIN for bootphase1 is 0x00100000 and for bootphase2 is 0x00100200\r
- However, this will confuse the currently deployed flash code which expects logical and and not\r
- physical addresses and performs no sanity checks at all. If confronted with physical addresses, \r
- it will happily erase everything and brick the device. So for the time being pretend these addresses\r
- to start at 0x0 while updating all the flash code with proper sanity checks, then come back later and\r
- fix the addresses. -- Henryk Plötz <henryk@ploetzli.ch> 2009-08-27 */\r
- bootphase1 : ORIGIN = 0x00000000, LENGTH = 0x200 /* Phase 1 bootloader: Copies real bootloader to RAM */\r
- bootphase2 : ORIGIN = 0x00000200, LENGTH = 0x2000 - 0x200 /* Main bootloader code, stored in Flash, executed from RAM */\r
- ram : ORIGIN = 0x00200000, LENGTH = 32K\r
-}\r
-\r
-\r
-SECTIONS\r
-{\r
- . = 0;\r
- \r
- bootphase1 : {\r
- *(.startup) \r
- *(.bootphase1)\r
- } >bootphase1\r
- \r
- bootphase2 : {\r
- __bootphase2_start__ = .;\r
- *(.startphase2)\r
- *(.text)\r
- *(.glue_7)\r
- *(.rodata)\r
- *(.data)\r
- . = ALIGN( 32 / 8 );\r
- __bootphase2_end__ = .;\r
- } >ram AT>bootphase2\r
- \r
- .bss : {\r
- __bss_start__ = .; \r
- *(.bss)\r
- } >ram\r
- \r
- . = ALIGN( 32 / 8 );\r
- __bss_end__ = .;\r
-}\r
+/*
+-----------------------------------------------------------------------------
+ This code is licensed to you under the terms of the GNU GPL, version 2 or,
+ at your option, any later version. See the LICENSE.txt file for the text of
+ the license.
+-----------------------------------------------------------------------------
+ Bootrom linker script
+-----------------------------------------------------------------------------
+*/
+
+INCLUDE ../common/ldscript.common
+
+PHDRS
+{
+ phase1 PT_LOAD;
+ phase2 PT_LOAD;
+ bss PT_LOAD;
+}
+
+ENTRY(flashstart)
+SECTIONS
+{
+ .bootphase1 : {
+ *(.startup)
+
+ . = ALIGN(4);
+ _version_information_start = .;
+ KEEP(*(.version_information));
+
+ . = LENGTH(bootphase1) - 0x4;
+ LONG(_version_information_start);
+ } >bootphase1 :phase1
+
+ .bootphase2 : {
+ *(.startphase2)
+ *(.text)
+ *(.text.*)
+ *(.eh_frame)
+ *(.glue_7)
+ *(.glue_7t)
+ *(.rodata)
+ *(.rodata.*)
+ *(.data)
+ *(.data.*)
+ . = ALIGN(4);
+ } >ram AT>bootphase2 :phase2
+
+ __bootphase2_src_start__ = LOADADDR(.bootphase2);
+ __bootphase2_start__ = ADDR(.bootphase2);
+ __bootphase2_end__ = __bootphase2_start__ + SIZEOF(.bootphase2);
+
+ .bss : {
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss.*)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ } >ram AT>ram :bss
+
+ .commonarea (NOLOAD) : {
+ *(.commonarea)
+ } >commonarea
+}