chg 'hf mf chk':

[proxmark3-svn] / fpga / hi_simulate.v

diff --git a/fpga/hi_simulate.v b/fpga/hi_simulate.v
index 8d70bb1b85f6131469a9b1cb615d56ffba3382eb..de58a74ec73af60429a6055cb494cfcbf4824911 100644 (file)
--- a/fpga/hi_simulate.v
+++ b/fpga/hi_simulate.v
@@ -16,29 +16,20 @@
 // Jonathan Westhues, October 2006
 //-----------------------------------------------------------------------------
 
-// possible mod_types:
-`define NO_MODULATION        3'b000
-`define MODULATE_BPSK        3'b001
-`define MODULATE_212K        3'b010
-`define MODULATE_424K        3'b100
-`define MODULATE_424K_8BIT   3'b101
-
 module hi_simulate(
-    pck0, ck_1356meg, ck_1356megb,
+    ck_1356meg,
     pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
     adc_d, adc_clk,
     ssp_frame, ssp_din, ssp_dout, ssp_clk,
-    cross_hi, cross_lo,
     dbg,
     mod_type
 );
-    input pck0, ck_1356meg, ck_1356megb;
+    input ck_1356meg;
     output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
     input [7:0] adc_d;
     output adc_clk;
     input ssp_dout;
     output ssp_frame, ssp_din, ssp_clk;
-    input cross_hi, cross_lo;
     output dbg;
     input [2:0] mod_type;
 
@@ -49,8 +40,8 @@ assign adc_clk = ck_1356meg;
 
 always @(negedge adc_clk)
 begin
-    if(& adc_d[7:5]) after_hysteresis = 1'b1;
-    else if(~(| adc_d[7:5])) after_hysteresis = 1'b0;
+    if(& adc_d[7:5]) after_hysteresis = 1'b1;           // if (adc_d >= 224)
+    else if(~(| adc_d[7:5])) after_hysteresis = 1'b0;   // if (adc_d <= 31)
 end
 
 
@@ -65,10 +56,10 @@ reg ssp_clk;
 
 always @(negedge adc_clk)
 begin
-    if(mod_type == `MODULATE_424K_8BIT)
+    if(mod_type == `FPGA_HF_SIMULATOR_MODULATE_424K_8BIT)
       // Get bit every at 53KHz (every 8th carrier bit of 424kHz)
       ssp_clk <= ssp_clk_divider[7];
-    else if(mod_type == `MODULATE_212K)
+    else if(mod_type == `FPGA_HF_SIMULATOR_MODULATE_212K)
       // Get next bit at 212kHz
       ssp_clk <= ssp_clk_divider[5];
     else
@@ -92,7 +83,7 @@ always @(negedge ssp_clk)
 
 reg ssp_frame;
 always @(ssp_frame_divider_to_arm or ssp_frame_divider_from_arm or mod_type)
-    if(mod_type == `NO_MODULATION) // not modulating, so listening, to ARM
+    if(mod_type == `FPGA_HF_SIMULATOR_NO_MODULATION) // not modulating, so listening, to ARM
         ssp_frame = (ssp_frame_divider_to_arm == 3'b000);
     else
         ssp_frame = (ssp_frame_divider_from_arm == 3'b000);
@@ -104,14 +95,14 @@ always @(posedge ssp_clk)
 
 // Modulating carrier frequency is fc/64 (212kHz) to fc/16 (848kHz). Reuse ssp_clk divider for that.
 reg modulating_carrier;
-always @(mod_type or ssp_clk or ssp_dout)
-    if (mod_type == `NO_MODULATION)
+always @(*)
+    if (mod_type == `FPGA_HF_SIMULATOR_NO_MODULATION)
         modulating_carrier <= 1'b0;                          // no modulation
-    else if (mod_type == `MODULATE_BPSK)
+    else if (mod_type == `FPGA_HF_SIMULATOR_MODULATE_BPSK)
         modulating_carrier <= ssp_dout ^ ssp_clk_divider[3]; // XOR means BPSK
-    else if (mod_type == `MODULATE_212K)
+    else if (mod_type == `FPGA_HF_SIMULATOR_MODULATE_212K)
         modulating_carrier <= ssp_dout & ssp_clk_divider[5]; // switch 212kHz subcarrier on/off
-    else if (mod_type == `MODULATE_424K || mod_type == `MODULATE_424K_8BIT)
+    else if (mod_type == `FPGA_HF_SIMULATOR_MODULATE_424K || mod_type == `FPGA_HF_SIMULATOR_MODULATE_424K_8BIT)
         modulating_carrier <= ssp_dout & ssp_clk_divider[4]; // switch 424kHz modulation on/off
     else
         modulating_carrier <= 1'b0;                           // yet unused