Added FPGA passthrough mode for TI tags

[proxmark3-svn] / fpga / fpga.v

diff --git a/fpga/fpga.v b/fpga/fpga.v
index 2a2269464a6589491bf218eff3e216d846f6cae7..2fb0ed7869a58578579fa8025b63747d21066781 100644 (file)
--- a/fpga/fpga.v
+++ b/fpga/fpga.v
@@ -13,6 +13,7 @@
 //-----------------------------------------------------------------------------\r
 \r
 `include "lo_read.v"\r
+`include "lo_passthru.v"\r
 `include "lo_simulate.v"\r
 `include "hi_read_tx.v"\r
 `include "hi_read_rx_xcorr.v"\r
@@ -122,6 +123,15 @@ lo_read lr(
        lo_is_125khz, divisor\r
 );\r
 \r
+lo_passthru lp(\r
+       pck0, ck_1356meg, ck_1356megb,\r
+       lp_pwr_lo, lp_pwr_hi, lp_pwr_oe1, lp_pwr_oe2, lp_pwr_oe3, lp_pwr_oe4,\r
+       adc_d, lp_adc_clk,\r
+       lp_ssp_frame, lp_ssp_din, ssp_dout, lp_ssp_clk,\r
+       cross_hi, cross_lo,\r
+       lp_dbg\r
+);\r
+\r
 lo_simulate ls(\r
        pck0, ck_1356meg, ck_1356megb,\r
        ls_pwr_lo, ls_pwr_hi, ls_pwr_oe1, ls_pwr_oe2, ls_pwr_oe3, ls_pwr_oe4,\r
@@ -178,20 +188,20 @@ hi_iso14443a hisn(
 //   011 --  HF reader, receiving from tag, correlating as it goes; frequency selectable\r
 //   100 --  HF simulated tag\r
 //   101 --  HF ISO14443-A\r
-//   110 --  unused\r
+//   110 --  LF passthrough\r
 //   111 --  everything off\r
 \r
-mux8 mux_ssp_clk       (major_mode, ssp_clk,   lr_ssp_clk,   ls_ssp_clk,   ht_ssp_clk,   hrxc_ssp_clk,   hs_ssp_clk,   hisn_ssp_clk,   1'b0, 1'b0);\r
-mux8 mux_ssp_din       (major_mode, ssp_din,   lr_ssp_din,   ls_ssp_din,   ht_ssp_din,   hrxc_ssp_din,   hs_ssp_din,   hisn_ssp_din,   1'b0, 1'b0);\r
-mux8 mux_ssp_frame     (major_mode, ssp_frame, lr_ssp_frame, ls_ssp_frame, ht_ssp_frame, hrxc_ssp_frame, hs_ssp_frame, hisn_ssp_frame, 1'b0, 1'b0);\r
-mux8 mux_pwr_oe1       (major_mode, pwr_oe1,   lr_pwr_oe1,   ls_pwr_oe1,   ht_pwr_oe1,   hrxc_pwr_oe1,   hs_pwr_oe1,   hisn_pwr_oe1,   1'b0, 1'b0);\r
-mux8 mux_pwr_oe2       (major_mode, pwr_oe2,   lr_pwr_oe2,   ls_pwr_oe2,   ht_pwr_oe2,   hrxc_pwr_oe2,   hs_pwr_oe2,   hisn_pwr_oe2,   1'b0, 1'b0);\r
-mux8 mux_pwr_oe3       (major_mode, pwr_oe3,   lr_pwr_oe3,   ls_pwr_oe3,   ht_pwr_oe3,   hrxc_pwr_oe3,   hs_pwr_oe3,   hisn_pwr_oe3,   1'b0, 1'b0);\r
-mux8 mux_pwr_oe4       (major_mode, pwr_oe4,   lr_pwr_oe4,   ls_pwr_oe4,   ht_pwr_oe4,   hrxc_pwr_oe4,   hs_pwr_oe4,   hisn_pwr_oe4,   1'b0, 1'b0);\r
-mux8 mux_pwr_lo                (major_mode, pwr_lo,    lr_pwr_lo,    ls_pwr_lo,    ht_pwr_lo,    hrxc_pwr_lo,    hs_pwr_lo,    hisn_pwr_lo,    1'b0, 1'b0);\r
-mux8 mux_pwr_hi                (major_mode, pwr_hi,    lr_pwr_hi,    ls_pwr_hi,    ht_pwr_hi,    hrxc_pwr_hi,    hs_pwr_hi,    hisn_pwr_hi,    1'b0, 1'b0);\r
-mux8 mux_adc_clk       (major_mode, adc_clk,   lr_adc_clk,   ls_adc_clk,   ht_adc_clk,   hrxc_adc_clk,   hs_adc_clk,   hisn_adc_clk,   1'b0, 1'b0);\r
-mux8 mux_dbg           (major_mode, dbg,       lr_dbg,       ls_dbg,       ht_dbg,       hrxc_dbg,       hs_dbg,       hisn_dbg,       1'b0, 1'b0);\r
+mux8 mux_ssp_clk               (major_mode, ssp_clk,   lr_ssp_clk,   ls_ssp_clk,   ht_ssp_clk,   hrxc_ssp_clk,   hs_ssp_clk,   hisn_ssp_clk,   lp_ssp_clk,   1'b0);\r
+mux8 mux_ssp_din               (major_mode, ssp_din,   lr_ssp_din,   ls_ssp_din,   ht_ssp_din,   hrxc_ssp_din,   hs_ssp_din,   hisn_ssp_din,   lp_ssp_din,   1'b0);\r
+mux8 mux_ssp_frame     (major_mode, ssp_frame, lr_ssp_frame, ls_ssp_frame, ht_ssp_frame, hrxc_ssp_frame, hs_ssp_frame, hisn_ssp_frame, lp_ssp_frame, 1'b0);\r
+mux8 mux_pwr_oe1               (major_mode, pwr_oe1,   lr_pwr_oe1,   ls_pwr_oe1,   ht_pwr_oe1,   hrxc_pwr_oe1,   hs_pwr_oe1,   hisn_pwr_oe1,   lp_pwr_oe1,   1'b0);\r
+mux8 mux_pwr_oe2               (major_mode, pwr_oe2,   lr_pwr_oe2,   ls_pwr_oe2,   ht_pwr_oe2,   hrxc_pwr_oe2,   hs_pwr_oe2,   hisn_pwr_oe2,   lp_pwr_oe2,   1'b0);\r
+mux8 mux_pwr_oe3               (major_mode, pwr_oe3,   lr_pwr_oe3,   ls_pwr_oe3,   ht_pwr_oe3,   hrxc_pwr_oe3,   hs_pwr_oe3,   hisn_pwr_oe3,   lp_pwr_oe3,   1'b0);\r
+mux8 mux_pwr_oe4               (major_mode, pwr_oe4,   lr_pwr_oe4,   ls_pwr_oe4,   ht_pwr_oe4,   hrxc_pwr_oe4,   hs_pwr_oe4,   hisn_pwr_oe4,   lp_pwr_oe4,   1'b0);\r
+mux8 mux_pwr_lo                        (major_mode, pwr_lo,    lr_pwr_lo,    ls_pwr_lo,    ht_pwr_lo,    hrxc_pwr_lo,    hs_pwr_lo,    hisn_pwr_lo,    lp_pwr_lo,    1'b0);\r
+mux8 mux_pwr_hi                        (major_mode, pwr_hi,    lr_pwr_hi,    ls_pwr_hi,    ht_pwr_hi,    hrxc_pwr_hi,    hs_pwr_hi,    hisn_pwr_hi,    lp_pwr_hi,    1'b0);\r
+mux8 mux_adc_clk               (major_mode, adc_clk,   lr_adc_clk,   ls_adc_clk,   ht_adc_clk,   hrxc_adc_clk,   hs_adc_clk,   hisn_adc_clk,   lp_adc_clk,   1'b0);\r
+mux8 mux_dbg                           (major_mode, dbg,       lr_dbg,       ls_dbg,       ht_dbg,       hrxc_dbg,       hs_dbg,       hisn_dbg,       lp_dbg,       1'b0);\r
 \r
 // In all modes, let the ADC's outputs be enabled.\r
 assign adc_noe = 1'b0;\r