Added FPGA passthrough mode for TI tags

[proxmark3-svn] / fpga / lo_passthru.v

diff --git a/fpga/lo_passthru.v b/fpga/lo_passthru.v
new file mode 100644 (file)
index 0000000..3814269
--- /dev/null
+++ b/fpga/lo_passthru.v
@@ -0,0 +1,35 @@
+//-----------------------------------------------------------------------------\r
+// For reading TI tags, we need to place the FPGA in pass through mode\r
+// and pass everything through to the ARM\r
+//-----------------------------------------------------------------------------\r
+\r
+module lo_passthru(\r
+    pck0, ck_1356meg, ck_1356megb,\r
+    pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,\r
+    adc_d, adc_clk,\r
+    ssp_frame, ssp_din, ssp_dout, ssp_clk,\r
+    cross_hi, cross_lo,\r
+    dbg\r
+);\r
+    input pck0, ck_1356meg, ck_1356megb;\r
+    output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;\r
+    input [7:0] adc_d;\r
+    output adc_clk;\r
+    input ssp_dout;\r
+    output ssp_frame, ssp_din, ssp_clk;\r
+    input cross_hi, cross_lo;\r
+    output dbg;\r
+\r
+// No logic, straight through.\r
+\r
+assign pwr_oe3 = 1'b0;\r
+assign pwr_oe1 = 1'b1;\r
+assign pwr_oe2 = 1'b1;\r
+assign pwr_oe4 = 1'b1;\r
+assign pwr_lo = 1'b0;\r
+assign pwr_hi = 1'b0;\r
+assign adc_clk = 1'b0;\r
+assign ssp_din = cross_lo;\r
+assign dbg = cross_lo;\r
+\r
+endmodule\r