Added LF frequency adjustments from d18c7db, cleaned up code,

[proxmark3-svn] / fpga / fpga.v

diff --git a/fpga/fpga.v b/fpga/fpga.v
index cbebc3955e102d566aa410fcc0d80bdfd5a6fc37..2a2269464a6589491bf218eff3e216d846f6cae7 100644 (file)
--- a/fpga/fpga.v
+++ b/fpga/fpga.v
@@ -21,7 +21,7 @@
 `include "util.v"\r
 \r
 module fpga(\r
 `include "util.v"\r
 \r
 module fpga(\r

-       spck, miso, mosi, ncs,\r
+       spcki, miso, mosi, ncs,\r

        pck0i, ck_1356meg, ck_1356megb,\r
        pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,\r
        adc_d, adc_clk, adc_noe,\r
        pck0i, ck_1356meg, ck_1356megb,\r
        pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,\r
        adc_d, adc_clk, adc_noe,\r


@@ -29,7 +29,7 @@ module fpga(
        cross_hi, cross_lo,\r
        dbg\r
 );\r
        cross_hi, cross_lo,\r
        dbg\r
 );\r

-       input spck, mosi, ncs;\r
+       input spcki, mosi, ncs;\r

        output miso;\r
        input pck0i, ck_1356meg, ck_1356megb;\r
        output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;\r
        output miso;\r
        input pck0i, ck_1356meg, ck_1356megb;\r
        output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;\r


@@ -40,11 +40,16 @@ module fpga(
        input cross_hi, cross_lo;\r
        output dbg;\r
 \r
        input cross_hi, cross_lo;\r
        output dbg;\r
 \r

+//assign pck0 = pck0i;\r

        IBUFG #(.IOSTANDARD("DEFAULT") ) pck0b(\r
                .O(pck0),\r
                .I(pck0i)\r
        );\r
        IBUFG #(.IOSTANDARD("DEFAULT") ) pck0b(\r
                .O(pck0),\r
                .I(pck0i)\r
        );\r

-//assign pck0 = pck0i;\r
+//assign spck = spcki;\r
+       IBUFG #(.IOSTANDARD("DEFAULT") ) spckb(\r
+               .O(spck),\r
+               .I(spcki)\r
+       );\r

 //-----------------------------------------------------------------------------\r
 // The SPI receiver. This sets up the configuration word, which the rest of\r
 // the logic looks at to determine how to connect the A/D and the coil\r
 //-----------------------------------------------------------------------------\r
 // The SPI receiver. This sets up the configuration word, which the rest of\r
 // the logic looks at to determine how to connect the A/D and the coil\r


@@ -52,7 +57,8 @@ module fpga(
 // to the configuration bits, for use below.\r
 //-----------------------------------------------------------------------------\r
 \r
 // to the configuration bits, for use below.\r
 //-----------------------------------------------------------------------------\r
 \r

-reg [7:0] conf_word_shift;\r
+reg [15:0] shift_reg;\r
+reg [7:0] divisor;\r

 reg [7:0] conf_word;\r
 \r
 // We switch modes between transmitting to the 13.56 MHz tag and receiving\r
 reg [7:0] conf_word;\r
 \r
 // We switch modes between transmitting to the 13.56 MHz tag and receiving\r


@@ -60,15 +66,18 @@ reg [7:0] conf_word;
 // glitching, or else we will glitch the transmitted carrier.\r
 always @(posedge ncs)\r
 begin\r
 // glitching, or else we will glitch the transmitted carrier.\r
 always @(posedge ncs)\r
 begin\r

-       conf_word <= conf_word_shift;\r
+       case(shift_reg[15:12])\r
+               4'b0001: conf_word <= shift_reg[7:0];\r
+               4'b0010: divisor <= shift_reg[7:0];\r
+       endcase\r

 end\r
 \r
 always @(posedge spck)\r
 begin\r
        if(~ncs)\r
        begin\r
 end\r
 \r
 always @(posedge spck)\r
 begin\r
        if(~ncs)\r
        begin\r

-               conf_word_shift[7:1] <= conf_word_shift[6:0];\r
-               conf_word_shift[0] <= mosi;\r
+               shift_reg[15:1] <= shift_reg[14:0];\r
+               shift_reg[0] <= mosi;\r

        end\r
 end\r
 \r
        end\r
 end\r
 \r


@@ -110,7 +119,7 @@ lo_read lr(
        lr_ssp_frame, lr_ssp_din, ssp_dout, lr_ssp_clk,\r
        cross_hi, cross_lo,\r
        lr_dbg,\r
        lr_ssp_frame, lr_ssp_din, ssp_dout, lr_ssp_clk,\r
        cross_hi, cross_lo,\r
        lr_dbg,\r

-       lo_is_125khz\r
+       lo_is_125khz, divisor\r

 );\r
 \r
 lo_simulate ls(\r
 );\r
 \r
 lo_simulate ls(\r