Added LF frequency adjustments from d18c7db, cleaned up code,

[proxmark3-svn] / fpga / lo_read.v

diff --git a/fpga/lo_read.v b/fpga/lo_read.v
index 9c3edb2258fcf23638c499d4a02426fa1859dd70..d7b45cb5927fd00a96480e210b649cd818df0fc5 100644 (file)
--- a/fpga/lo_read.v
+++ b/fpga/lo_read.v
@@ -1,6 +1,6 @@
 //-----------------------------------------------------------------------------\r
 // The way that we connect things in low-frequency read mode. In this case\r
-// we are generating the 134 kHz or 125 kHz carrier, and running the \r
+// we are generating the 134 kHz or 125 kHz carrier, and running the\r
 // unmodulated carrier at that frequency. The A/D samples at that same rate,\r
 // and the result is serialized.\r
 //\r
@@ -14,7 +14,7 @@ module lo_read(
     ssp_frame, ssp_din, ssp_dout, ssp_clk,\r
     cross_hi, cross_lo,\r
     dbg,\r
-    lo_is_125khz\r
+    lo_is_125khz, divisor\r
 );\r
     input pck0, ck_1356meg, ck_1356megb;\r
     output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;\r
@@ -25,6 +25,7 @@ module lo_read(
     input cross_hi, cross_lo;\r
     output dbg;\r
     input lo_is_125khz;\r
+    input [7:0] divisor;\r
 \r
 // The low-frequency RFID stuff. This is relatively simple, because most\r
 // of the work happens on the ARM, and we just pass samples through. The\r
@@ -38,65 +39,39 @@ module lo_read(
 // 125 kHz by dividing by a further factor of (8*12*2), or ~134 kHz by\r
 // dividing by a factor of (8*11*2) (for 136 kHz, ~2% error, tolerable).\r
 \r
-reg [3:0] pck_divider;\r
-reg clk_lo;\r
-\r
-always @(posedge pck0)\r
-begin\r
-    if(lo_is_125khz)\r
-    begin\r
-        if(pck_divider == 4'd11)\r
-        begin\r
-            pck_divider <= 4'd0;\r
-            clk_lo = !clk_lo;\r
-        end\r
-        else\r
-            pck_divider <= pck_divider + 1;\r
-    end\r
-    else\r
-    begin\r
-        if(pck_divider == 4'd10)\r
-        begin\r
-            pck_divider <= 4'd0;\r
-            clk_lo = !clk_lo;\r
-        end\r
-        else\r
-            pck_divider <= pck_divider + 1;\r
-    end\r
-end\r
-\r
-reg [2:0] carrier_divider_lo;\r
-\r
-always @(posedge clk_lo)\r
-begin\r
-    carrier_divider_lo <= carrier_divider_lo + 1;\r
-end\r
-\r
-assign pwr_lo = carrier_divider_lo[2];\r
-\r
-// This serializes the values returned from the A/D, and sends them out\r
-// over the SSP.\r
-\r
 reg [7:0] to_arm_shiftreg;\r
+reg [7:0] pck_divider;\r
+reg [6:0] ssp_divider;\r
+reg ant_lo;\r
 \r
-always @(posedge clk_lo)\r
+always @(posedge pck0)\r
 begin\r
-    if(carrier_divider_lo == 3'b000)\r
-        to_arm_shiftreg <= adc_d;\r
-    else\r
-        to_arm_shiftreg[7:1] <= to_arm_shiftreg[6:0];\r
+       if(pck_divider == 8'd0)\r
+               begin\r
+                       pck_divider <= divisor[7:0];\r
+                       ant_lo = !ant_lo;\r
+                       if(ant_lo == 1'b0)\r
+                       begin\r
+                           ssp_divider <= 7'b0011111;\r
+                               to_arm_shiftreg <= adc_d;\r
+                       end\r
+               end\r
+       else\r
+       begin\r
+               pck_divider <= pck_divider - 1;\r
+               if(ssp_divider[6] == 1'b0)\r
+               begin\r
+                       if (ssp_divider[1:0] == 1'b11) to_arm_shiftreg[7:1] <= to_arm_shiftreg[6:0];\r
+                       ssp_divider <= ssp_divider - 1;\r
+               end\r
+       end\r
 end\r
 \r
-assign ssp_clk = clk_lo;\r
-assign ssp_frame = (carrier_divider_lo == 3'b001);\r
 assign ssp_din = to_arm_shiftreg[7];\r
-\r
-// The ADC converts on the falling edge, and our serializer loads when\r
-// carrier_divider_lo == 3'b000.\r
-assign adc_clk = ~carrier_divider_lo[2];\r
-\r
+assign ssp_clk = pck_divider[1];\r
+assign ssp_frame = ~ssp_divider[5];\r
 assign pwr_hi = 1'b0;\r
-\r
+assign pwr_lo = ant_lo;\r
+assign adc_clk = ~ant_lo;\r
 assign dbg = adc_clk;\r
-\r
 endmodule\r