-reg [3:0] pck_divider;\r
-reg clk_lo;\r
-\r
-always @(posedge pck0)\r
-begin\r
- if(lo_is_125khz)\r
- begin\r
- if(pck_divider == 4'd11)\r
- begin\r
- pck_divider <= 4'd0;\r
- clk_lo = !clk_lo;\r
- end\r
- else\r
- pck_divider <= pck_divider + 1;\r
- end\r
- else\r
- begin\r
- if(pck_divider == 4'd10)\r
- begin\r
- pck_divider <= 4'd0;\r
- clk_lo = !clk_lo;\r
- end\r
- else\r
- pck_divider <= pck_divider + 1;\r
- end\r
-end\r
-\r
-reg [2:0] carrier_divider_lo;\r
-\r
-always @(posedge clk_lo)\r
-begin\r
- carrier_divider_lo <= carrier_divider_lo + 1;\r
-end\r
-\r
-assign pwr_lo = carrier_divider_lo[2];\r
-\r
-// This serializes the values returned from the A/D, and sends them out\r
-// over the SSP.\r
-\r