}
}
- cmd_send(CMD_MEASURED_ANTENNA_TUNING, vLf125 | (vLf134<<16), vHf, peakf | (peakv<<16), LF_Results, 256);
+ cmd_send(CMD_MEASURED_ANTENNA_TUNING, vLf125>>1 | (vLf134>>1<<16), vHf, peakf | (peakv>>1<<16), LF_Results, 256);
FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
LED_B_OFF();
return;
// Reset SSC
AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST;
+ // Configure MUX
+ AT91C_BASE_PIOA->PIO_OER =
+ GPIO_MUXSEL_HIPKD |
+ GPIO_MUXSEL_LOPKD |
+ GPIO_MUXSEL_LORAW |
+ GPIO_MUXSEL_HIRAW;
+
+ AT91C_BASE_PIOA->PIO_PER =
+ GPIO_MUXSEL_HIPKD |
+ GPIO_MUXSEL_LOPKD |
+ GPIO_MUXSEL_LORAW |
+ GPIO_MUXSEL_HIRAW;
+
+ // set pins LOW
+ LOW(GPIO_MUXSEL_HIPKD);
+ LOW(GPIO_MUXSEL_LOPKD);
+ LOW(GPIO_MUXSEL_HIRAW);
+ LOW(GPIO_MUXSEL_LORAW);
+
// Load the FPGA image, which we have stored in our flash.
// (the HF version by default)
FpgaDownloadAndGo(FPGA_BITSTREAM_HF);