PHDRS
{
- fpgaimage PT_LOAD FLAGS(4);
- text PT_LOAD;
+ text PT_LOAD FLAGS(5);
data PT_LOAD;
bss PT_LOAD;
}
ENTRY(Vector)
SECTIONS
{
- .fpgaimage : {
- *(fpga_bit.data)
- } >fpgaimage :fpgaimage
-
.start : {
*(.startos)
} >osimage :text
.text : {
+ KEEP(*(stage1_image))
*(.text)
*(.text.*)
*(.eh_frame)
.rodata : {
*(.rodata)
*(.rodata.*)
- *(.version_information)
+ *(fpga_all_bit.data)
+ KEEP(*(.version_information))
+ . = ALIGN(8);
} >osimage :text
- . = ALIGN(4);
-
.data : {
+ KEEP(*(compressed_data))
*(.data)
*(.data.*)
+ *(.ramfunc)
. = ALIGN(4);
} >ram AT>osimage :data
__data_src_start__ = LOADADDR(.data);
__data_start__ = ADDR(.data);
__data_end__ = __data_start__ + SIZEOF(.data);
+ __os_size__ = SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.rodata);
.bss : {
__bss_start__ = .;