// If bytereversal is set: reverse the byte order in each 4-byte word\r
static void DownloadFPGA(const char *FpgaImage, int FpgaImageLen, int bytereversal)\r
{\r
- int i;\r
+ int i=0;\r
\r
PIO_OUTPUT_ENABLE = (1 << GPIO_FPGA_ON);\r
PIO_ENABLE = (1 << GPIO_FPGA_ON);\r
- PIO_OUTPUT_DATA_SET = (1 << GPIO_FPGA_ON);\r
+ HIGH(GPIO_FPGA_ON); // ensure everything is powered on\r
\r
SpinDelay(50);\r
\r
LED_D_ON();\r
\r
+ // These pins are inputs\r
+ PIO_OUTPUT_DISABLE = (1 << GPIO_FPGA_NINIT) | (1 << GPIO_FPGA_DONE);\r
+ // PIO controls the following pins\r
+ PIO_ENABLE = (1 << GPIO_FPGA_NINIT) | (1 << GPIO_FPGA_DONE);\r
+ // Enable pull-ups\r
+ PIO_NO_PULL_UP_DISABLE = (1 << GPIO_FPGA_NINIT) | (1 << GPIO_FPGA_DONE);\r
+\r
+ // setup initial logic state\r
HIGH(GPIO_FPGA_NPROGRAM);\r
LOW(GPIO_FPGA_CCLK);\r
LOW(GPIO_FPGA_DIN);\r
+ // These pins are outputs\r
PIO_OUTPUT_ENABLE = (1 << GPIO_FPGA_NPROGRAM) |\r
(1 << GPIO_FPGA_CCLK) |\r
(1 << GPIO_FPGA_DIN);\r
- SpinDelay(1);\r
\r
+ // enter FPGA configuration mode\r
LOW(GPIO_FPGA_NPROGRAM);\r
SpinDelay(50);\r
HIGH(GPIO_FPGA_NPROGRAM);\r
\r
+ i=100000;\r
+ // wait for FPGA ready to accept data signal\r
+ while ((i) && ( !(PIO_PIN_DATA_STATUS & (1<<GPIO_FPGA_NINIT) ) ) ) {\r
+ i--;\r
+ }\r
+\r
+ // crude error indicator, leave both red LEDs on and return\r
+ if (i==0){\r
+ LED_C_ON();\r
+ LED_D_ON();\r
+ return;\r
+ }\r
+\r
if(bytereversal) {\r
/* This is only supported for DWORD aligned images */\r
if( ((int)FpgaImage % sizeof(DWORD)) == 0 ) {\r
/* Explanation of the magic in the above line: \r
* i^0x3 inverts the lower two bits of the integer i, counting backwards\r
* for each 4 byte increment. The generated sequence of (i++)^3 is\r
- * 3 2 1 0 7 6 5 4 11 10 9 8 15 14 13 12 etc. pp.
+ * 3 2 1 0 7 6 5 4 11 10 9 8 15 14 13 12 etc. pp. \r
*/\r
}\r
} else {\r
DownloadFPGA_byte(*FpgaImage++);\r
}\r
\r
+ // continue to clock FPGA until ready signal goes high\r
+ i=100000;\r
+ while ( (i--) && ( !(PIO_PIN_DATA_STATUS & (1<<GPIO_FPGA_DONE) ) ) ) {\r
+ HIGH(GPIO_FPGA_CCLK);\r
+ LOW(GPIO_FPGA_CCLK);\r
+ }\r
+ // crude error indicator, leave both red LEDs on and return\r
+ if (i==0){\r
+ LED_C_ON();\r
+ LED_D_ON();\r
+ return;\r
+ }\r
LED_D_OFF();\r
}\r
\r