]> git.zerfleddert.de Git - proxmark3-svn/blobdiff - armsrc/lfops.c
BUG: don't try to fix things that ain't broken.. or not. My try for a fix ended...
[proxmark3-svn] / armsrc / lfops.c
index c80caf776b323d600453b62c557c5f4e4d90778f..0755e1e5a73c5fc5c8072b07e54438a70e5cf73b 100644 (file)
@@ -449,61 +449,78 @@ void WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc)
        DbpString("Now use tiread to check");
 }
 
+
+        
+// PIO_CODR = Clear Output Data Register
+// PIO_SODR = Set Output Data Register
+//#define LOW(x)        AT91C_BASE_PIOA->PIO_CODR = (x)
+//#define HIGH(x)       AT91C_BASE_PIOA->PIO_SODR = (x)
 void SimulateTagLowFrequency(int period, int gap, int ledcontrol)
 {
        int i = 0;
-       uint8_t *buff = (uint8_t *)BigBuf;
+       uint8_t *buf = (uint8_t *)BigBuf;
 
        FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
        FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
        FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT);
+       
+       // Connect the A/D to the peak-detected low-frequency path.
        SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
 
-       // Configure output and enable pin that is connected to the FPGA (for modulating)
-       AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK;    
-       AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
+       // Now set up the SSC to get the ADC samples that are now streaming at us.
+       FpgaSetupSsc();
        
-       AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK;
+       // Configure output and enable pin that is connected to the FPGA (for modulating)
+       // AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK; // (PIO_PER) PIO Enable Register
+       // AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;    // (PIO_OER) Output Enable Register
+       // AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK;     // (PIO_ODR) Output Disable Register
 
-       // Give it a bit of time for the resonant antenna to settle.
-       SpinDelay(30);
+       AT91C_BASE_PIOA->PIO_OER = GPIO_PCK0;
+       
+       while(!BUTTON_PRESS()) { 
+               WDT_HIT();
 
-       for(;;) { 
-               
-               while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) {
+               // PIO_PDSR = Pin Data Status Register  
+               // GPIO_SSC_CLK  = SSC Transmit Clock
+               // wait ssp_clk == high
+               while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) {  
                         if(BUTTON_PRESS()) {
                                 DbpString("Stopped at 0");
-                                FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
                                 return;
                         }
                         WDT_HIT();
                }
-        
-               if ( buff[i] )
+               
+               if ( buf[i] > 0 ){
                        OPEN_COIL();
-               else
+               } else {
                        SHORT_COIL();
-       
-                while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) {
+               }
+          
+          DbpString("Enter Sim3");
+           // wait ssp_clk == low
+                while( (AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) ) {  
                         if(BUTTON_PRESS()) {
-                               DbpString("Stopped at 1");
-                               FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
+                               DbpString("stopped at 1");
                                return;
                        }
                        WDT_HIT();
-                }
-        
+               }
+               
+               DbpString("Enter Sim4 ");
+               //SpinDelayUs(512);
+               
                ++i;
                if(i == period) {
                        i = 0;
                        if (gap) {
-                               // turn of modulation
                                SHORT_COIL();
-                               // wait
-                               SpinDelay(gap);
+                               SpinDelay(gap);                         
                        } 
                }
        }
+       DbpString("Stopped");
+       return;
 }
 
 #define DEBUG_FRAME_CONTENTS 1
Impressum, Datenschutz