--- /dev/null
+//-----------------------------------------------------------------------------\r
+//\r
+// Jonathan Westhues, April 2006\r
+//-----------------------------------------------------------------------------\r
+\r
+module hi_read_rx_xcorr(\r
+ pck0, ck_1356meg, ck_1356megb,\r
+ pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,\r
+ adc_d, adc_clk,\r
+ ssp_frame, ssp_din, ssp_dout, ssp_clk,\r
+ cross_hi, cross_lo,\r
+ dbg,\r
+ xcorr_is_848, snoop\r
+);\r
+ input pck0, ck_1356meg, ck_1356megb;\r
+ output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;\r
+ input [7:0] adc_d;\r
+ output adc_clk;\r
+ input ssp_dout;\r
+ output ssp_frame, ssp_din, ssp_clk;\r
+ input cross_hi, cross_lo;\r
+ output dbg;\r
+ input xcorr_is_848, snoop;\r
+\r
+// Carrier is steady on through this, unless we're snooping.\r
+assign pwr_hi = ck_1356megb & (~snoop);\r
+assign pwr_oe1 = 1'b0;\r
+assign pwr_oe2 = 1'b0;\r
+assign pwr_oe3 = 1'b0;\r
+assign pwr_oe4 = 1'b0;\r
+\r
+reg ssp_clk;\r
+reg ssp_frame;\r
+\r
+reg fc_div_2;\r
+always @(posedge ck_1356meg)\r
+ fc_div_2 = ~fc_div_2;\r
+\r
+reg adc_clk;\r
+\r
+always @(xcorr_is_848 or fc_div_2 or ck_1356meg)\r
+ if(xcorr_is_848)\r
+ // The subcarrier frequency is fc/16; we will sample at fc, so that \r
+ // means the subcarrier is 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 ...\r
+ adc_clk <= ck_1356meg;\r
+ else\r
+ // The subcarrier frequency is fc/32; we will sample at fc/2, and\r
+ // the subcarrier will look identical.\r
+ adc_clk <= fc_div_2;\r
+\r
+// When we're a reader, we just need to do the BPSK demod; but when we're an\r
+// eavesdropper, we also need to pick out the commands sent by the reader,\r
+// using AM. Do this the same way that we do it for the simulated tag.\r
+reg after_hysteresis, after_hysteresis_prev;\r
+reg [11:0] has_been_low_for;\r
+always @(negedge adc_clk)\r
+begin\r
+ if(& adc_d[7:0]) after_hysteresis <= 1'b1;\r
+ else if(~(| adc_d[7:0])) after_hysteresis <= 1'b0;\r
+\r
+ if(after_hysteresis)\r
+ begin\r
+ has_been_low_for <= 7'b0;\r
+ end\r
+ else\r
+ begin\r
+ if(has_been_low_for == 12'd4095)\r
+ begin\r
+ has_been_low_for <= 12'd0;\r
+ after_hysteresis <= 1'b1;\r
+ end\r
+ else\r
+ has_been_low_for <= has_been_low_for + 1;\r
+ end\r
+end\r
+\r
+// Let us report a correlation every 4 subcarrier cycles, or 4*16 samples,\r
+// so we need a 6-bit counter.\r
+reg [5:0] corr_i_cnt;\r
+reg [5:0] corr_q_cnt;\r
+// And a couple of registers in which to accumulate the correlations.\r
+reg signed [15:0] corr_i_accum;\r
+reg signed [15:0] corr_q_accum;\r
+reg signed [7:0] corr_i_out;\r
+reg signed [7:0] corr_q_out;\r
+\r
+// ADC data appears on the rising edge, so sample it on the falling edge\r
+always @(negedge adc_clk)\r
+begin\r
+ // These are the correlators: we correlate against in-phase and quadrature\r
+ // versions of our reference signal, and keep the (signed) result to\r
+ // send out later over the SSP.\r
+ if(corr_i_cnt == 7'd63)\r
+ begin\r
+ if(snoop)\r
+ begin\r
+ corr_i_out <= {corr_i_accum[12:6], after_hysteresis_prev};\r
+ corr_q_out <= {corr_q_accum[12:6], after_hysteresis};\r
+ end\r
+ else\r
+ begin\r
+ // Only correlations need to be delivered.\r
+ corr_i_out <= corr_i_accum[13:6];\r
+ corr_q_out <= corr_q_accum[13:6];\r
+ end\r
+\r
+ corr_i_accum <= adc_d;\r
+ corr_q_accum <= adc_d;\r
+ corr_q_cnt <= 4;\r
+ corr_i_cnt <= 0;\r
+ end\r
+ else\r
+ begin\r
+ if(corr_i_cnt[3])\r
+ corr_i_accum <= corr_i_accum - adc_d;\r
+ else\r
+ corr_i_accum <= corr_i_accum + adc_d;\r
+\r
+ if(corr_q_cnt[3])\r
+ corr_q_accum <= corr_q_accum - adc_d;\r
+ else\r
+ corr_q_accum <= corr_q_accum + adc_d;\r
+\r
+ corr_i_cnt <= corr_i_cnt + 1;\r
+ corr_q_cnt <= corr_q_cnt + 1;\r
+ end\r
+\r
+ // The logic in hi_simulate.v reports 4 samples per bit. We report two\r
+ // (I, Q) pairs per bit, so we should do 2 samples per pair.\r
+ if(corr_i_cnt == 6'd31)\r
+ after_hysteresis_prev <= after_hysteresis;\r
+\r
+ // Then the result from last time is serialized and send out to the ARM.\r
+ // We get one report each cycle, and each report is 16 bits, so the\r
+ // ssp_clk should be the adc_clk divided by 64/16 = 4.\r
+\r
+ if(corr_i_cnt[1:0] == 2'b10)\r
+ ssp_clk <= 1'b0;\r
+\r
+ if(corr_i_cnt[1:0] == 2'b00)\r
+ begin\r
+ ssp_clk <= 1'b1;\r
+ // Don't shift if we just loaded new data, obviously.\r
+ if(corr_i_cnt != 7'd0)\r
+ begin\r
+ corr_i_out[7:0] <= {corr_i_out[6:0], corr_q_out[7]};\r
+ corr_q_out[7:1] <= corr_q_out[6:0];\r
+ end\r
+ end\r
+\r
+ if(corr_i_cnt[5:2] == 4'b000 || corr_i_cnt[5:2] == 4'b1000)\r
+ ssp_frame = 1'b1;\r
+ else\r
+ ssp_frame = 1'b0;\r
+\r
+end\r
+\r
+assign ssp_din = corr_i_out[7];\r
+\r
+assign dbg = corr_i_cnt[3];\r
+\r
+// Unused.\r
+assign pwr_lo = 1'b0;\r
+\r
+endmodule\r
projects / proxmark3-svn / blobdiff